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TPA3140D2
SLOS882B – JANUARY 2015 – REVISED DECEMBER 2017
TPA3140D2 10-W Inductor Free Stereo (BTL) Class-D Audio Amplifier with Ultra Low
EMIand AGL
1 Features
3 Description
•
The TPA3140D2 is an efficient, Class-D audio power
amplifier for driving bridged-tied stereo speakers at
up to 10 W, 6 Ω, or 8 Ω (per channel).
1
•
•
•
•
•
•
•
•
•
•
•
•
2x10 W/ch into 6-Ω Loads at 10% THD+N from a
12-V Supply
2x10 W/ch into 8-Ω Loads at 10% THD+N from a
13-V Supply
Up to 90% Efficient Class-D Operation (8 Ω)
Eliminates Need for Heat Sinks
12 V
4.8
BTL, PVCC ≤ 12 V
3.2
PBTL, PVCC > 12 V
2.5
Minimum load resistance, RL
–0.3
–0.3
PBTL, PVCC ≤ 12 V
AVCC + 0.3
V
10
V/ms
GVDD + 0.3
V
100
V/ms
6.3
V
Ω
1.8
Continuous total power dissipation
See the Thermal Information Table
Operating free-air temperature range, TA (4)
–40
85
°C
Temperature range
–65
150
°C
Storage temperature range, Tstg
–65
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100 kΩ resister in series
with the pins.
The voltage slew rate of these pins must be restricted to no more than 100 V/ms. For higher slew rates, use a 100 kΩ resister in series
with the pins.
The TPA3140D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101
(2)
±250
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
4.5
14.4
V
2
AVCC
V
VCC
Supply voltage
PVCC, AVCC
VIH
High-level input voltage
SD, 1SPW
VIL
Low-level input voltage
SD, 1SPW
0.8
V
VOL
Low-level output voltage
FAULT, RPULL-UP=100 k, PVCC=14.4 V
0.8
V
IIH
High-level input current
SD, 1SPW, VI = 2 V, AVCC = 12 V
50
µA
IIL
Low-level input current
SD, 1SPW, VI = 0.8 V, AVCC = 12 V
5
µA
TA
Operating free-air temperature (1)
–40
85
°C
-40
150
°C
TJ
(1)
Operating junction temperature
(1)
The TPA3140D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
7.4 Thermal Information
TPA3140D2
THERMAL METRIC
(1)
PWP (HTSSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
37.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
19.4
°C/W
RθJB
Junction-to-board thermal resistance
16.6
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
16.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC CHARACTERISTICS, TA = 25°C, AVCC = PVCC = 12 V, RL = 6 Ω, using the TPA3140D2 EVM which is available at ti.com. (unless otherwise noted)
| VOS |
Class-D output offset voltage (measured
differentially)
VI = 0 V, Gain = 36 dB
1.5
15
mV
ICC
Quiescent supply current
SD = 2 V, no load, 10 µF + 680 nF Output Filter
35
40
mA
ICC(SD)
Quiescent supply current in shutdown mode
SD = 0.8 V, no load
40
60
µA
rDS(on)
Drain-source on-state resistance
IO = 500 mA, TJ = 25°C High Side
Excluding Metal and
Low side
Bond Wire Resistance
240
GAIN = 0 V (GND)
19
20
21
GAIN = 2.3 V (1/3·GVDD)
25
26
27
GAIN = 4.6 V (2/3·GVDD)
31
32
33
GAIN = 6.9 V (GVDD)
35
36
37
G
Gain
ton
Turn-on time
SD = 2 V
14
tOFF
Turn-off time
SD = 0.8 V
2.5
GVDD
Gate drive supply
IGVDD = 2 mA
DC detect time
VRINN = 3.1 V and VRINN = 2.9 V, or VRINN = 2.9 V and
VRINN = 3.1 V
tDCDET
6
mΩ
240
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6.4
6.9
950
dB
ms
µs
7.4
V
ms
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC CHARACTERISTICS, TA = 25°C, AVCC = PVCC = 12 V, RL = 6 Ω, using the TPA3140D2 EVM which is available at ti.com. (unless otherwise noted)
PSRR
Power supply ripple rejection
200-mVPP ripple at 1 kHz,
Gain = 20 dB, Inputs ac-coupled to GND
PO
Continuous output power
PO
Continuous output power
PO
–65
dB
THD+N = 10%, f = 1 kHz
10
W
THD+N = 10%, f = 1 kHz, PVCC = 13 V, RL = 8 Ω
10
W
Continuous output power, PBTL (mono)
THD+N = 10%, f = 1 kHz, PVCC = 13 V, RL = 4 Ω
20
W
IO
Maximum output current
f = 1 kHz, RL=3 Ω
3.1
A
THD+N
Total harmonic distortion + noise
f = 1 kHz, PO = 5 W (half-power)
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB, Spread
Spectrum off
65
µV
–80
dBV
Crosstalk
VO = 1 Vrms, Gain = 20 dB, f = 1 kHz
–75
dB
SNR
Signal-to-noise ratio
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted, Spread Spectrum off
102
dB
OTE
Thermal trip point
150
°C
15
°C
125
°C
0.06%
Thermal hysteresis
TFB
Thermal foldback trip point
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
fOSC
Oscillator frequency
250
310
350
kHz
fOSC, SS
Oscillator frequency, Spread Spectrum ON
255
315
355
kHz
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7.7 Typical Characteristics
All Measurements taken at 20dB closed loop gain, 1-kHz audio, TA = 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3140D2 EVM, which is available at ti.com.
10
10
1W
2.5W
5W
1W
2.5W
5W
1
THD + N (%)
THD + N (%)
1
0.1
0.01
0.1
0.01
0.001
20
50
100
200
500 1k
2k
Frequency (Hz)
5k
10k
0.001
20
20k
50
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 1 W, 2.5 W, 5 W
5k
10k
20k
D002
10
20 Hz
1 kHz
20 Hz
1 kHz
1
THD + N (%)
THD + N (%)
500 1k
2k
Frequency (Hz)
Figure 2. Total Harmonic Distortion vs Frequency, 1SPW
(BTL)
10
0.1
0.01
10m 20m
50m 100m200m 500m 1
Output Power (W)
2
5
10
1
0.1
0.01
10m 20m
20
D003
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 20 Hz, 1 kHz, 6.7 kHz
18
14
Power @ 10% THD + N (W)
16
14
12
10
8
6
4
2
5
10
20
D004
Figure 4. Total Harmonic Distortion + Noise vs Output
Power, 1SPW (BTL)
20
16
50m 100m200m 500m 1
Output Power (W)
AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 20 Hz, 1 kHz, 6.7 kHz
Figure 3. Total Harmonic Distortion + Noise vs Output
Power, 1SPW (BTL)
Power @ 10% THD + N (W)
200
AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 1 W, 2.5 W, 5 W
Figure 1. Total Harmonic Distortion vs Frequency, 1SPW
(BTL)
12
10
8
6
4
2
2
0
0
4
5
6
7
8
9
10 11
Supply Voltage (V)
12
13
14
15
4
5
D005
AVCC=PVCC = 4.5 V to 14.4 V, Load = 6 Ω + 47 µH, AGL + PLIM
disable (LIMRATE = GND, LIMTHRES = GVDD)
Figure 5. Output Power vs Supply Voltage, 1SPW (BTL)
8
100
D001
6
7
8
9
10 11
Supply Voltage (V)
12
13
14
15
D006
AVCC=PVCC = 4.5 V to 14.4 V, Load = 8 Ω + 66 µH, AGL + PLIM
disable (LIMRATE = GND, LIMTHRES = GVDD)
Figure 6. Output Power vs Supply Voltage, 1SPW (BTL)
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Typical Characteristics (continued)
All Measurements taken at 20dB closed loop gain, 1-kHz audio, TA = 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3140D2 EVM, which is available at ti.com.
28
40
24
20
100
90
80
0
16
-20
12
-40
Efficiency (%)
20
Phase (°)
Gain (dB)
70
60
50
40
30
20
PVcc = 6V
PVcc = 12V
PVcc = 14.4V
10
8
20
0
-60
50
100 200
500 1k
Frequency
2k
5k
10k
0
20k
2.5
5
7.5 10 12.5 15 17.5
Total Output Power (W)
D007
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH (device pins)
20
22.5
25
D008
AVCC=PVCC = 6 V, 12 V, 14.4 V, Load = 6 Ω + 47 µH, AGL +
PLIM disable (LIMRATE = GND, LIMTHRES = GVDD)
Figure 7. Gain/Phase vs Frequency (BTL)
Figure 8. Efficiency vs Output Power, 1SPW (BTL)
100
0
90
-10
-20
80
-30
Crosstalk (dB)
Efficiency (%)
70
60
50
40
30
-40
-50
-60
-70
-80
-90
20
PVcc = 6V
PVcc = 13V
PVcc = 14.4V
10
-100
0
2.5
5
7.5
10 12.5 15 17.5
Output Power (W)
20
22.5
Ch 1
Ch 2
-110
-120
20
0
25
50
100
200
D009
AVCC=PVCC= 6 V, 13 V, 14.4 V, Load = 8 Ω + 66 µH, AGL +
PLIM disable (LIMRATE = GND, LIMTHRES = GVDD)
500 1k
2k
Frequency (Hz)
5k
10k
20k
D010
AVCC=PVCC = 12 V, 1 W, Load = 6 Ω + 47 µH
Figure 10. Crosstalk vs Frequency, 1SPW (BTL)
Figure 9. Efficiency vs Output Power, 1SPW (BTL)
0
10
5
-10
-30
THD + N (%)
PVcc PSRR (dB)
-20
-40
-50
-60
0.2
0.1
0.05
0.02
0.01
0.005
-70
-80
-90
-100
20
2
1
0.5
1W
5W
10 W
50
100
200
500 1k
2k
Frequency (Hz)
5k
10k
20k
0.002
0.001
20
D011
AVCC=PVCC = 12 V, Load = 4 Ω + 33 µH
50
100
200
500 1k
2k
Frequency (Hz)
5k
10k
20k
D012
AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 1 W, 2.5 W, 10 W
Figure 11. Supply Ripple Rejection Ratio vs Frequency
(BTL)
Figure 12. Total Harmonic Distortion + Noise vs Frequency,
1SPW (PBTL)
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Typical Characteristics (continued)
All Measurements taken at 20dB closed loop gain, 1-kHz audio, TA = 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3140D2 EVM, which is available at ti.com.
10
30
27
Power @ 10% THD + N (W)
THD + N (%)
20 Hz
1 kHz
1
0.1
24
21
18
15
12
9
6
3
0.01
10m 20m
0
50m 100m200m 500m 1
2
Output Power (W)
5
10
20
4
5
6
7
8
9
10 11
Supply Voltage (V)
D013
AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 20 Hz, 1 kHz, 6.7 kHz
Figure 13. Total Harmonic Distortion + Noise vs Output
Power, 1SPW (PBTL)
12
13
14
15
D014
AVCC=PVCC = 4.5 V to 14.4 V, Load = 4 Ω + 33 µH, AGL + PLIM
disable (LIMRATE = GND, LIMTHRES = GVDD)
Figure 14. Output Power vs Supply Voltage, 1SPW (PBTL)
100
90
80
Efficiency (%)
70
60
50
40
30
20
PVcc = 6V
PVcc = 13V
PVcc = 14.4V
10
0
0
2.5
5
7.5 10 12.5 15 17.5
Total Output Power (W)
20
22.5
25
D015
AVCC=PVCC = 6 V, 13 V, 14.4 V, Load = 4 Ω + 33 µH, AGL + PLIM disable (LIMRATE = GND, LIMTHRES =
GVDD)
Figure 15. Efficiency vs Output Power, 1SPW (PBTL)
8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications and Typical
Characteristics.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. An AES-17 pre analyzer filter is recommended to use for ClassD amplifier measurements. In absence of such filter, a 30-kHz low-pass filter (10 Ω + 47 nF) can be used to
reduce the out of band noise remaining on the amplifier outputs.
10
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9 Detailed Description
9.1 Overview
To facilitate system design, the TPA3140D2 needs only a single power supply between 4.5 V and 14.4 V for
operation. An internal voltage regulator provides suitable voltage levels for the gate driver, digital, and lowvoltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, as in the high-side gate drive,
is accommodated by built-in bootstrap circuitry with integrated boot strap diodes requiring only an external
capacitor for each half-bridge.
The audio signal path, including the gate drive and output stage, is designed as identical, independent fullbridges. All decoupling capacitors should be placed as close to their associated pins as possible. In general, the
physical loop with the power supply pins, decoupling capacitors and GND return path to the device pins must be
kept as short as possible and with as little area as possible to minimize induction (see reference board
documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BSXX) to the power-stage output pin (OUTXX). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap
pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential
and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching
frequencies in the range of 310 kHz, use ceramic capacitors with at least 220-nF capacitance, size 0603 or 0805,
for the bootstrap supply. These capacitors ensure sufficient energy storage, even during clipped low frequency
audio signals, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of its
ON cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. For optimal electrical performance, EMI compliance, and system reliability, each PVCC
pin should be decoupled with ceramic capacitors that are placed as close as possible to each supply pin. It is
recommended to follow the PCB layout of the TPA3140D2 reference design. For additional information on
recommended power supply and required components, see the application diagrams in this data sheet.
The PVCC power supply should have low output impedance and low noise. The power-supply ramp and SD
release sequence is not critical for device reliability as facilitated by the internal power-on-reset circuit, but it is
recommended to release SD after the power supply is settled for minimum turn on audible artifacts.
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9.2 Functional Block Diagram
GVDD
PVCCL
BSPL
PVCCL
PBTL Select
OUTPL FB
Gate
Drive
OUTPL
OUTPL FB
LINP
Gain
Control
GND
PWM
Logic
PLIMIT
GVDD
LINN
PVCCL
BSNL
PVCCL
OUTNL FB
OUTNL FB
FAULT
Gate
Drive
OUTNL
SD
GAIN
TTL
Buffer
SC Detect
GND
Gain
Control
Spread Spectrum
Control
SSCTRL
Ramp
Generator
Biases and
References
Startup Protection
Logic
DC Detect
Thermal
Detect
UVLO/OVLO
LIMITER
Reference
LIMRES
GVDD
AVCC
PVCCL
BSNR
AVDD
PVCCL
LDO
Regulator
GVDD
Gate
Drive
GVDD
OUTNR
OUTNR FB
OUTNR FB
RINN
Gain
Control
PLIMIT
GND
PWM
Logic
GVDD
RINP
PVCCL
BSPR
PVCCL
OUTNR FB
Gate
Drive
OUTPR
PBTL Select
OUTPR FB
GND
9.3 Feature Description
9.3.1 Gain Setting via GAIN Pin
The gain of the TPA3140D2 is set by a voltage applied to the GAIN pin, which is set by a resistor voltage divider
with GVDD as supply voltage. The resistance of the voltage divider should be a minimum of 100 kΩ in order not
to overload the GVDD regulator of TPA3140D2.
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Feature Description (continued)
/SD
/FAULT
LINP
LINN
LIMRATE
GAIN
SSCTRL
LIMTHRES
GVDD
AGND
RINN
RINP
1SPW
AVCC
Figure 16. GAIN Pin Voltage Programming by GVDD Resistor Divider
The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside
the amplifier. This causes the input impedance (Zi) to be dependent on the gain setting. The actual gain settings
are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance
from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
The selected input gain is latched at device start up and cannot be changed when SD is high.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 7.2 kΩ, which is the absolute minimum input impedance of the TPA3140D2. At the lower gain
settings, the input impedance could increase as high as 72 kΩ.
Table 1. Gain Setting
AMPLIFIER GAIN (dB)
INPUT IMPEDANCE (kΩ)
TYP
TYP
0 V (GND)
20
60
2.3 V (1/3·GVDD)
26
30
4.6 V (2/3·GVDD)
32
15
6.9 V (GVDD)
36
9
GAIN PIN VOLTAGE
9.3.2
SD Operation
The TPA3140D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SD input pin should be held high (see
specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the
outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier
operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply voltage.
9.3.3 Gain Limit Control, LIMTHRES and LIMRATE
The TPA3140D2 has built-in gain limiters with two operation modes for load and system protection: Voltage
limiting and temperature limiting. The voltage limiting mode controls the TPA3140D2 voltage gain to limit the
output signal without signal clipping, and the temperature control mode limits the device power dissipation to
keep the die temperature within recommended operating conditions. Both voltage limiter and thermal limiter
attack and release speeds (time per 0.5dB gain step) are controlled by the LIMRATE pin:
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Table 2. Speaker Guard AGL Settings
LIMRATE
VOLTAGE
MODE
AGL ATTACK
TIME
TFB ATTACK TIME
AGL/TFB
RELEASE TIME
GVDD
FAST
40 µs
200 ms
400 ms
2/3·GVDD
MEDIUM
80 µs
400 ms
800 ms
1/3·GVDD
SLOW
160 µs
800 ms
1600 ms
GND
PLIMIT
DISABLED
DISABLED
DISABLED
LIMRATE accepts a 4-level input signal to setup operation. When LIMRATE is connected to GND, the voltage
limiter function is changed to a hard clip action to control the maximum output voltage.
9.3.4 SPEAKERGUARD Automatic Gain Limit, AGL
The TPA3140D2 has a built-in SpeakerGuard AGL to limit excessive output voltage to a non clipping output
signal. When an excessive level input signal is sent to TPA3140D2, the SpeakerGuard AGL will automatically
reduce the amplifier gain to maintain maximum unclipped output signal to preserve high audio quality and to
protect the attached speaker from excessive power. The AGL works with a fast attack speed and a slower
release speed to achieve maximum protection and a minimum number of audible artifacts.
input signal
attack level
release level
output signal
Figure 17. AGL Attack and Release Thresholds
When the input level multiplied by the TPA3140D2 closed loop gain exceeds the limiter threshold set by the
LIMTHRES pin voltage, the TPA3140D2 closed loop gain is reduced by a single or by multiple 0.5-dB steps until
the output signal voltage gets below the level set by the LIMTHRES pin voltage, or if a –12.0-dB gain reduction
limit is reached. When the output voltage gets below the release threshold, the TPA3140D2 closed loop gain is
increased by a single or by multiple 0.5-dB steps until the release threshold is reached, or the closed loop gain is
at its nominal closed loop gain level. The AGL gain adjustment is applied with a ramp speed selectable by the
LIMRATE pin setting.
14
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input signal
thermal
warning
attack time
release time
gain
release level
attack level
output signal
Figure 18. AGL Attack and Release Slopes
9.3.5 Thermal Foldback, TFB
The TPA3140D2 Thermal Foldback, TFB, is designed to protect the TPA3140D2 from excessive die temperature
in case the device is operated beyond the recommended temperature or power limit, or with a weaker thermal
system than recommended. The TFB works by reducing the on die power dissipation by reducing the
TPA3140D2 closed loop gain in steps of 0.5 dB if the temperature trig point is exceeded. Once the die
temperature drops below the TFB trig point, the TPA3140D2 closed loop gain is increased by a single or by
multiple 0.5-dB steps until either the TFB trig point is reached, the closed loop gain attains the nominal closed
loop gain level, or a maximum of 12-dB attenuation is reached, in which case the closed loop gain will be
decreased again. The TFB gain adjustment is applied with a ramp speed selectable by the LIMRATE pin setting
as shown in Table 2.
9.3.6 PLIMIT
The PLIMIT operation will, if selected, limit the output voltage level to a voltage level below the supply rail. In this
case the amplifier operates as if it was powered by a lower supply voltage, and thereby limiting the output power
by voltage clipping. PLIMIT threshold is set by the LIMTHRES pin voltage.
Figure 19. PLIMIT Circuit Operation
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9.3.7 LIMTHRES
The AGL and PLIMIT voltage threshold is set by the applied LIMTHRES voltage. The LIMTHRES voltage is set
by a voltage divider from GVDD to GND. The limiting is done by limiting the amplifier output voltage to a fixed
maximum value. This limit can be thought of as a "virtual" voltage rail, which is lower than the PVCC supply. This
virtual rail is 4 times the voltage at the LIMTHRES pin. This output voltage can be used to calculate the
maximum output voltage (unclipped using AGL and clipped using PLIMIT) and power for a given LIMTHRES
voltage and speaker impedance.
POUT
§§
RL
¨¨
¨¨ R 2 ˜ R
S
©© L
2 ˜ RL
2
·
·
¸¸ ˜ VP ¸
¸
¹
¹ ,
for unclipped power
(1)
Where:
RS is the total series resistance including RDS(on), and any resistance in the output filter.
RL is the load resistance.
VP is the peak amplitude of the output possible within the supply rail.
VP = 4 × LIMTHRES voltage if VP < PVCC
POUT = Maximum unclipped output power. 10%THD using PLIMIT: 1.25 × PMAX (unclipped)
Increasing the LIMTHRES voltage from a given value increases the maximum output voltage swing until it equals
PVCC. Adjusting LIMTHRES to a higher value will disable both the AGL and PLIMIT function and will offer
highest available output power, however it is always advised to use the LIMTHRES function if PVCC is higher
than the nominal value to prevent shutdown due to over current protection or to reduce frequency of thermal
foldback events. To disable the AGL or PLIMIT function, the LIMTHRES pin is simply connected to GVDD.
/SD
/FAULT
LINP
LINN
LIMRATE
GAIN
SSCTRL
LIMTHRES
GVDD
AGND
RINN
RINP
1SPW
AVCC
Figure 20. LIMHTRES Pin Voltage Programming by GVDD Resistor Divider
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Table 3. LIMTHRES Typical Operation
LIMTHRES
VOLTAGE (V)
R to GND
R to GVDD
OUTPUT
POWER (W),
UNCLIPPED,
AGL
OUTPUT
POWER (W),
10% THD,
PLIMIT
PVCC = 12 V,
RL = 6 Ω
1.9
33 kΩ
82 kΩ
4.75
6
PVCC = 12 V,
RL = 6 Ω
2.2
39 kΩ
82 kΩ
6.5
8
PVCC = 12 V,
RL = 6 Ω
2.5
39 kΩ
68 kΩ
8
10
PVCC = 14.4
V, RL = 8 Ω
2.2
39 kΩ
82 kΩ
4.75
6
PVCC = 14.4
V, RL = 8 Ω
2.5
39 kΩ
68 kΩ
6.5
8
PVCC = 14.4
V, RL = 8 Ω
2.8
47 kΩ
68 kΩ
8
10
TEST
CONDITIONS
()
space
5
5
AGL, UNCLIPPED, 8Ÿ
PLIMIT, 10% THD, 6Ÿ
4
LIMTHRES [V]
LIMTHRES [V]
AGL, UNCLIPPED, 6Ÿ
PLIMIT, 10% THD, 8Ÿ
4
3
2
3
2
1
1
0
0
0
2
4
6
8
Max Output Power [W]
10
0
12
2
4
Figure 21. Max Output Power vs LIMTHRES, 8 Ω, PVCC =
13 V
6
8
10
Max Output Power [W]
C003
12
C002
Figure 22. Max Output Power vs LIMTHRES, 6 Ω, PVCC =
12 V
9.3.8 Spread Spectrum and De-Phase Control
The TPA3140D2 has built-in spread spectrum control of the oscillator frequency and de-phase of the PWM
outputs to improve EMI performance. Two spread spectrum schemes can be selected, and for operation without
spread spectrum, de-phase can be turned off.
De-phase inverts the phase of the output PWM such that the idle output PWM waveforms of the two audio
channels are inverted. De-phase does not affect the audio signal, or its polarity.
Spread spectrum mode and de-phase is selected by the applied SSCTRL voltage.
Table 4. Gain Setting
SSCTRL PIN VOLTAGE
SPREAD SPECTRUM
MODULATION
DE-PHASE
0 V (GND)
OFF
OFF
2.3 V (1/3·GVDD)
OFF
ON
4.6 V (2/3·GVDD)
SS1 MODULATION
ON
6.9 V (GVDD)
SS2 MODULATION
ON
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9.3.9 GVDD Supply
The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply
the voltage divider circuits for LIMRATE, LIMTHRES, GAIN, and SSCTRL programming voltages.. Add a 1-μF
capacitor to ground at this pin.
9.3.10 DC Detect
The TPA3140D2 has circuitry which will protect the speakers from DC current which might occur due to defective
capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on
the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the
state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVCC supply. Cycling SD will
NOT clear a DC detect fault.
A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example,
+57%, -43%) for more than 950 msec at the same polarity. This feature protects the speaker from large DC
currents or AC currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low
at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive
and negative inputs to avoid nuisance DC detect faults.
The minimum differential input voltages required to trigger the DC detect are show in Table 5. The inputs must
remain at or above the voltage listed in the table for more than 950 msec to trigger the DC detect.
Table 5. DC Detect Threshold, PVCC=12V
AV(dB)
Vin (mV, differential)
Vout (V, differential)
20
260
2.6
26
130
2.6
32
65
2.6
36
40
2.6
9.3.11 PBTL Select
The TPA3140D2 offers the feature of parallel BTL operation with two outputs of each channel connected directly.
If the LINP and LINN input pins (pin 3 and 4) are tied low, the positive and negative outputs of each channel (left
and right) are synchronized and in phase. To operate in this PBTL (mono) mode, tie LINP and LINN inputs low to
GND and apply the input signal to the RINP and RINN inputs and place the speaker between the LEFT and
RIGHT outputs with OUTPL connected to OUTNL and OUTPR connected to OUTNR to parallel the output half
bridges for highest power efficiency. For an example of the PBTL connection, see the schematic in the Typical
Applications section.
9.3.12 Short-Circuit Protection and Automatic Recovery Feature
The TPA3140D2 has protection from overcurrent conditions caused by a short circuit on the output stage. The
short circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a
Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin
through the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the short-circuit
protection latch.
9.3.13 Thermal Protection
Thermal protection on the TPA3140D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a
latched fault.
Thermal protection faults are reported on the FAULT pin.
If automatic recovery from the thermal protection latch is desired, connect the FAULT pin directly to the SD pin.
This allows the FAULT pin function to automatically drive the SD pin low which clears the thermal protection
latch.
18
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9.4 Device Functional Modes
The TPA3140D2 has the option of running in either BD modulation or 1SPW modulation; this is set by the 1SPW
pin.
1SPW = GND: BD-modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
No Output
OUTP- OUTN
0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP - OUTN
0V
- PVCC
Speaker
Current
0A
Figure 23. BD Mode Modulation
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Device Functional Modes (continued)
1SPW = HIGH: 1SPW-modulation
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty
in THD degradation and more attention required in the output filter selection. In 1SPW mode the outputs operate
at ~15% modulation during idle conditions. When an audio signal is applied one output will decrease and one will
increase. The decreasing output signal will quickly rail to GND at which point all the audio modulation takes place
through the rising output. The result is that only one output is switching during a majority of the audio cycle.
Efficiency is improved in this mode due to the reduction of switching losses. The THD penalty in 1SPW mode is
minimized by the high performance feedback loop. The resulting audio signal at each half output has a
discontinuity each time the output rails to GND. This can cause ringing in the audio reconstruction filter unless
care is taken in the selection of the filter components and type of filter used.
OUTP
OUTN
OUTP -OUTN
No Output
0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP -OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP -OUTN
0V
- PVCC
Speaker
Current
0A
Figure 24. 1SPW Mode Modulation
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPA3140D2 is designed for use in inductor free applications with limited distance wire length) between
amplifier and speakers like in TV sets, sound docks and Bluetooth speakers. The TPA3140D2 can either be
configured in stereo or mono mode, depending on output power conditions. Depending on output power
requirements and necessity for (speaker) load protection, the built in AGL or PLIMIT circuit can be used to
control system power, see functional description of these features.
10.2 Typical Applications
PVCC
1nF
100nF
100µF
GND
FB
10k
/SD
/SHUTDOWN
/FAULT
1µF
IN_LEFT
3
LINN
4
LIMRATE
5
GAIN
6
SSCTRL
7
56k
LIMTHRES
33k
28
PVCC
27
BSPL
26
LINP
1µF
GND
39k
PVCC
1
2
33k
33k
GND
GVDD
1µF
1µF
GND
RINN
RINP
IN_RIGHT
1µF
1SPW
AVCC
GND
TPA3140D2
8
9
10
11
12
13
14
25
24
23
22
21
20
19
18
17
16
15
1nF
220nF
OUTPL
GND
GND
GND
1nF
OUTNL
FB
220nF
BSNL
BSNR
OUTNR
220nF
FB
GND
GND
OUTPR
1nF
BSPR
PVCC
220nF
GND
PVCC
1nF
1µF
FB
GND
10R
PVCC
1nF
100nF
100µF
GND
Figure 25. Stereo Class-D Amplifier with BTL Output and Single-Ended Inputs with Spread Spectrum
Modulation
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Typical Applications (continued)
PVCC
1nF
10k
/SD
/SHUTDOWN
/FAULT
PVCC
1
2
LINP
3
4
LIMRATE
5
GND
GAIN
39k
56k
SSCTRL
6
7
TPA3140D2
LIMTHRES
33k
33k
33k
1µF
GND
8
GVDD
9
GND
1µF
RINN
1µF
1SPW
RINP
IN
AVCC
GND
25
24
23
22
21
20
10
11
12
13
14
19
18
17
16
15
470nF
OUTPL
GND
100µF
GND
28
PVCC
27
BSPL
26
LINN
100nF
FB
GND
OUTNL
BSNL
1nF
BSNR
OUTNR
GND
GND
GND
1nF
OUTPR
FB
BSPR
PVCC
470nF
PVCC
1µF
GND
10R
PVCC
1nF
100nF
100µF
GND
(1)
100-kΩ resistor is needed if the PVCC slew rate is more than 10 V/ms.
Figure 26. Stereo Class-D Amplifier with PBTL Output and Single-Ended Input with Spread Spectrum
Modulation
10.2.1 Design Requirements
10.2.1.1 PCB Material Recommendation
FR-4 Glass Epoxy material with 1 oz. (35 µm) is recommended for use with the TPA3140D2. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance). It is recommended to use several GND underneath the device thermal pad for
thermal coupling to a bottom side copper GND plane for best thermal performance.
10.2.1.2 PVCC Capacitor Recommendation
The large capacitors used in conjunction with each full-bridge, are referred to as the PVCC Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 100 μF, 16 V will support most applications
with 12-V power supply. 25-V capacitor rating is recommended for power supply voltage higher than 12-V. For
The PVCC capacitors should be low ESR type because they are used in a circuit associated with high-speed
switching.
10.2.1.3 Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the ceramic capacitors that are placed on the power supply to each full-bridge. They must withstand
the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and
the ripple current created by high power output. A minimum voltage rating of 16 V is required for use with a 12-V
power supply.
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Typical Applications (continued)
10.2.2 Detailed Design Procedure
A rising-edge transition on SD input allows the device to start switching. It is recommended to ramp the PVCC
voltage to its desired value before releasing SD for minimum audible artefacts.
The device is non-inverting the audio signal from input to output.
The GVDD pin is not recommended to be used as a voltage source for external circuitry.
10.2.2.1 Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3140D2 amplifier it is possible to design a
high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to
accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite
bead used in the filter.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to
the operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have
emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the
range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,
the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead's
current handling capability by measuring the resonant frequency of the filter output at low power and at maximum
power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of
ferrite beads which have been tested and work well with the TPA3140D2 include NFZ2MSM series from Murata.
A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class D outputs to
ground. Suggested values for a simple RC series snubber network would be 10 Ω in series with a 330-pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the GND or the thermal pad beneath the
chip.
10.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3140D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
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Typical Applications (continued)
10.2.2.3 When to Use an Output Filter for EMI Suppression
The TPA3140D2 has been tested with a simple ferrite bead filter for a variety of applications including long
speaker wires up to 100 cm and high power. The TPA3140D2 EVM passes FCC Class B specifications under
these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic
second order Butterworth filter similar to those shown in the figures below can be used.
Some systems have little power supply decoupling from the AC line but are also subject to line conducted
interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these
cases, it LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using
low frequency ferrite material can also be effective at preventing line conducted interference.
33 mH
OUTP
L1
C2
1 mF
33 mH
OUTN
L2
C3
1 mF
Figure 27. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
L1
C2
2.2 mF
15 mH
OUTN
L2
C3
2.2 mF
Figure 28. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 6 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 29. Typical Ferrite Chip Bead Filter (Chip Bead Example: )
10.2.2.4 Input Resistance
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the
largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or
cutoff frequency may change when changing gain steps.
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Typical Applications (continued)
Zf
Ci
IN
Input
Signal
Zi
The -3-dB frequency can be calculated using Equation 2. Use the Zi values given in Table 1.
f =
1
2p Zi Ci
(2)
10.2.2.5 Input Capacitor, Ci
In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a highpass filter with the corner frequency determined in Equation 3.
-3 dB
fc =
1
2p Zi Ci
fc
(3)
The value of Ci is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where Zi is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
Ci =
1
2p Zi fc
(4)
In this example, Ci is 0.13 µF; so, one would likely choose a value of 0.15 μF as this value is commonly used. If
the gain is known and is constant, use Zi from Table 1 to calculate Ci. A further consideration for this capacitor is
the leakage path from the input source through the input network (Ci) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.
10.2.2.6 BSN and BSP Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 0.22-μF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 0.22-μF capacitor must be
connected from OUTPx to BSPx, and one 0.22-μF capacitor must be connected from OUTNx to BSNx. (See the
application circuit diagram in Figure 25.)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
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Typical Applications (continued)
10.2.2.7 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3140D2 with a differential source, connect the positive lead of the audio source to the INP input and
the negative lead from the audio source to the INN input. To use the TPA3140D2 with a single-ended source, ac
ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply
the audio source to either input. In a single-ended input application, the unused input should be ac grounded at
the audio source instead of at the device input for best noise performance. For good transient performance, the
impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input dc blocking capacitors to become completely charged during the 14 ms power-up time. If the input
capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching
which can result in pop if the input components are not well matched.
10.2.2.8 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
26
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Typical Applications (continued)
10.2.3 Application Performance Curves
10.2.3.1 EN55013 Radiated Emissions Results
60
60
50
50
40
Limit (dBPV/m)
Limit (dBPV/m)
TPA3140D2 EVM, PVCC = 12 V, 8-Ω load, up to 1 meter speaker cable, Spread Spectrum enabled, PO = 1.25 W
30
20
10
40
30
20
10
0
0
Limit
Peaks
-10
0.03
1
0.1
Frequency (GHz)
Limit
Peaks
-10
0.03
CISPR Class B 3m 30-1000MHz Scan#7- TPA3140D2 EVM with
8R Load, Different ferrite choke, Murata 601FB+1nF, 1-meter
cable, Battery supply, SS-TRI, BD, 1.25W, Spkr Wire Config2
0.1
Frequency (GHz)
1
CISPR Class B 3m 30-1000MHz Scan#7- TPA3140D2 EVM with
8R Load, Different ferrite choke, Murata 601FB+1nF, 1-meter
cable, Battery supply, SS-TRI, BD, 1.25W, Spkr Wire Config2
Figure 30. Radiated Emission - Horizontal
Figure 31. Radiated Emission - Vertical
Table 6. Radiated Emission - Horizontal
Table 7. Radiated Emission - Vertical
TURN
TABLE
DEGREES
TOWER
cm
FREQUENCY
MHz
LIMIT
dBµV/m
PEAKS
dBµV/m
Q-PEAK
dBµV/m
MARGIN
dB
–18.482
44.9
100
56.841
40.457
26.213
27.058
–18.271
326.9
100
241.9
47.457
19.429
20.430
FREQUENCY
MHz
LIMIT
dBµV/m
PEAKS
dBµV/m
Q-PEAK
dBµV/m
MARGIN
dB
166.246
40.457
21.781
21.975
237.372
47.457
29.330
29.186
TURN
TABLE
DEGREES
TOWER
cm
–13.399
54
100
–27.027
–0.1
100
space
10.2.3.2 EN55022 Conducted Emissions Results
TV (40 inch) from the major TV manufacturer, TPA3140D2 EVM, PVCC = 12 V, 8-Ω speakers, Spread Spectrum enabled, PO
= 1.25 W
80
60
50
40
60
50
40
30
30
20
20
10
0.15
1
Frequency (MHz)
10
Quasi Peak Limit
Average Limit
Peak Readings
70
Amplitude (dBPV)
Amplitude (dBPV)
80
Quasi Peak Limit
Average Limit
Peak Readings
70
10
0.15
30
1
10
30
Frequency (MHz)
CISPR Class B 0.150-30MHz Idle Mode. SS0, Triangular, BD,
1.25 Watt
CISPR Class B 0.150-30MHz Idle Mode. SS0, Triangular, BD,
1.25 Watt
Figure 32. Conducted Emission - Line
Figure 33. Conducted Emission - Neutral
Table 8. Conducted Emission - Line
Table 9. Conducted Emission - Neutral
FREQUENCY
MHz
QP
LIMIT
dBµV
AVE
LIMIT
dBµV
AVE
READINGS
dBµV
AVE
MARGIN
dB
QP
READINGS
dBµV
QP
MARGIN
dB
FREQUENCY
MHz
QP
LIMIT
dBµV
AVE
LIMIT
dBµV
AVE
READINGS
dBµV
AVE
MARGIN
dB
QP
READINGS
dBµV
QP
MARGIN
dB
0.156
65.83
55.83
33.774
–22.056
45.956
–19.873
0.158
65.785
55.785
34.022
–21.763
45.398
–20.387
0.552
56
46
28.872
–17.128
39.164
–16.836
0.554
56
46
29.574
–16.426
40.485
–15.515
0.806
56
46
21.341
–24.659
29.585
–26.415
0.735
56
46
22.652
–23.348
32.52
–23.48
0.95
56
46
22.678
–23.322
31.471
–24.529
0.918
56
46
22.699
–23.301
31.849
–24.151
1.485
56
46
22.622
–23.378
31.082
–24.918
1.402
56
46
23.264
–22.736
32.173
–23.827
1.976
56
46
20.952
–25.048
29.849
–26.151
7.806
60
50
28.006
–21.994
35.214
–24.786
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11 Power Supply Recommendations
11.1 Power Supply Decoupling, CS
The TPA3140D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. Optimum decoupling is
achieved by using a network of capacitors of different types that target specific types of noise on the power
supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper
trace inductances as well as lead frame capacitance, a good quality low equivalent-series-resistance (ESR)
ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be placed as close to
the device PVCC pins and system ground (either GND pins or thermal pad) as possible. For mid-frequency noise
due to filter resonances or PWM switching transients as well as digital hash on the line, another good quality
capacitor typically 0.1 μF to 1 µF placed as close as possible to the device PVCC leads works best. For filtering
lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 μF or greater placed near the audio
power amplifier is recommended. The 220-μF capacitor also serves as a local storage capacitor for supplying
current during large signal transients on the amplifier outputs. The PVCC pins provide the power to the output
transistors, so a 220-µF or larger capacitor should be placed on each PVCC pin. A 10-µF capacitor on the AVCC
pin is adequate. Also, a small decoupling resistor between AVCC and PVCC can be used to keep high frequency
class-D noise from entering the linear input amplifiers.
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12 Layout
12.1 Layout Guidelines
The TPA3140D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the printed
circuit board. The following suggestions will help to meet EMC requirements.
• Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC pins as possible. Large (220 µF or greater) bulk power supply decoupling capacitors should be
placed near the TPA3140D2 on the PVCCL and PVCCR supplies. Local, high-frequency bypass capacitors
should be placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad
directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor
between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1μF and 1μF also of good
quality to the PVCC connections at each end of the chip.
• Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
• Grounding—The AVCC (pin 14) decoupling capacitor should be connected to ground (GND). The PVCC
decoupling capacitors should connect to GND. Analog ground and power ground should be connected at the
thermal pad, which should be used as a central ground connection or star ground for the TPA3140D2.
• Output filter—The ferrite EMI filter (Figure 29) should be placed as close to the output pins as possible for the
best EMI performance. The LC filter (Figure 27 and Figure 28) should be placed close to the outputs. The
capacitors used in both the ferrite and LC filters should be grounded to power ground.
• Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35 mm. Seven rows
of solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application
Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB
footprints, see figures at the end of this data sheet.
For an example layout, see the TPA3140D2 Evaluation Module (TPA3140D2 EVM) User Manual. Both the EVM
user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com.
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12.2 Layout Example
100PF
100nF
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
2118
9
20
10
19
11
18
12
17
13
16
14
15
FB
1nF
1nF
0.22PF
1nF
FB
0.22PF
0.22PF
FB
1nF
1PF
0.22PF
1nF
1nF
FB
1PF
100nF
100PF
Top Layer Ground and Thermal Pad
Via to Bottom Ground Plane
Pad to Top Layer Ground Pour
Top Layer Signal Traces
Figure 34. BTL Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
TPA3140D2EVM User's Guide (SLOU405)
PowerPAD™ Thermally Enhanced Package Application Report (SLMA002)
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
SpeakerGuard, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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12-Dec-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA3140D2PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TPA3140D2
TPA3140D2PWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TPA3140D2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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