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TPA6133A2
SLOS821B – JUNE 2013 – REVISED SEPTEMBER 2014
TPA6133A2 138-mW DirectPath™ Stereo Headphone Amplifier
1 Features
3 Description
•
The TPA6133A2 is a stereo DirectPath™ headphone
amplifier with GPIO control. The TPA6133A2 has
minimal quiescent current consumption, with a typical
IDD of 4.2 mA, making it optimal for portable
applications. The GPIO control allows the device to
be put in a low power shutdown mode.
1
•
•
•
•
•
•
•
DirectPath™ Ground-Referenced Outputs
– Eliminates Output DC Blocking Capacitors
– Reduces Board Area
– Reduces Component Height and Cost
– Full Bass Response Without Attenuation
Power Supply Voltage Range: 2.5 V to 5.5 V
High Power Supply Rejection Ratio
(>100 dB PSRR)
Differential Inputs for Maximum Noise Rejection
(69 dB CMRR)
High-Impedance Outputs When Disabled
Advanced Pop and Click Suppression Circuitry
GPIO Control for Shutdown
20 Pin, 4 mm x 4 mm WQFN Package
The TPA6133A2 is a high fidelity amplifier with an
SNR of 93 dB. A PSRR greater than 100 dB enables
direct-to-battery connections without compromising
the listening experience. The output noise of 12
μVrms (typical A-weighted) provides a minimal noise
background during periods of silence. Configurable
differential inputs and high CMRR allow for maximum
noise rejection in the noisy environment of a mobile
device.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
2 Applications
TPA6133A2
•
•
•
•
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Mobile Phones
Audio Headsets
Notebook Computers
High Fidelity Applications
WQFN (20)
4.00 mm x 4.00 mm
4 Simplified Application Diagram
GPIO
VBAT
2.2KQ
Audio Source
TEST1
SD
TEST2
0.47uF
LEFT_OUTM
LEFTINM
0.47uF
RIGHT_OUTM
0.47uF
0.47uF
RIGHT_OUTP
HPLEFT
LEFTINP
LEFT_OUTP
HPRIGHT
RIGHTINM
GND
RIGHTINP
GND
CPP
CPN
CPVSS
VDD
VDD
VBAT
1uF
1uF
1uF
1uF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA6133A2
SLOS821B – JUNE 2013 – REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Application Diagram............................
Revision History.....................................................
Pin Configuration and Functions .........................
Specification...........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 17
11.1 Layout Guidelimes ................................................ 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1 Trademarks ........................................................... 18
12.2 Electrostatic Discharge Caution ............................ 18
12.3 Glossary ................................................................ 18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2014) to Revision B
Page
•
Changed "PIN QFN" To: "NUMBER" in the Pin Functions table............................................................................................ 3
•
Added a NOTE to the Applications and Implementation section ........................................................................................ 13
•
Added new paragraph to the Application Information section.............................................................................................. 13
Changes from Original (June 2013) to Revision A
Page
•
Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Added the Device Information Table ..................................................................................................................................... 1
•
Moved "Minimum Load Impedance" From the Absolute Maximum Ratings table To the Recommended Operating
Conditions table ...................................................................................................................................................................... 4
•
Added the Thermal Information Table ................................................................................................................................... 4
•
Changed text in the Overview section From: "toggling the SD pin to logic 1." To: "asserting the SD pin to logic 1." ......... 10
•
Changed text in the Headphone Amplifier section From: "the output signal is severely clipped" To: "power
consumption will be higher" .................................................................................................................................................. 11
•
Added the Optional Test Setup section................................................................................................................................ 15
•
Added the Layout Example image ...................................................................................................................................... 17
2
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6 Pin Configuration and Functions
VDD
GND
CPP
CPN
CPVSS
RTJ Package
(Top VIEW)
20
19
18
17
16
LEFTINM
1
15
CPVSS
LEFTINP
2
14
HPLEFT
GND
3
13
GND
RIGHTINP
4
12
VDD
RIGHTINM
5
11
HPRIGHT
Top View
10
GND
9
GND
8
TEST1
7
TEST2
SD
6
Pin Functions
PIN
NUMBER
INPUT,
OUTPUT,
POWER
LEFTINM
1
I
Left channel negative differential input. Impedance must be matched to LEFTINP. Connect the left
input to LEFTINM when using single-ended inputs.
LEFTINP
2
I
Left channel positive differential input. Impedance must be matched to LEFTINM. AC ground
LEFTINP near signal source while maintaining matched impedance to LEFTINM when using singleended inputs.
RIGHTINP
4
I
Right channel positive differential input. Impedance must be matched to RIGHTINM. AC ground
RIGHTINP near signal source while maintaining matched impedance to RIGHTINM when using
single-ended inputs.
3, 9, 10, 13
P
Analog ground. Must be connected to common supply GND. It is recommended that this pin be
used to decouple VDD for analog. Use pin 13 to decouple pin 12 on the QFN package.
RIGHTINM
5
I
Right channel negative differential input. Impedance must be matched to RIGHTINP. Connect the
right input to RIGHTINM when using single-ended inputs.
SD
6
I
Shutdown. Active low logic. 5V tolerant input.
TEST2
7
I
Factory test pins. Pull up to VDD supply. See Applications Diagram.
TEST1
8
I
Factory test pins. Pull up to VDD supply. See Applications Diagram.
HPRIGHT
11
O
Headphone light channel output. Connect to the right terminal of the headphone jack.
VDD
12
P
Analog VDD. VDD must be connected to common VDD supply. Decouple with its own 1-μF capacitor
to analog ground (pin 13).
HPLEFT
14
O
Headphone left channel output. Connect to left terminal of headphone jack.
CPVSS
15, 16
P
Negative supply generated by the charge pump. Decouple to pin 19 or a GND plane. Use a 1 μF
capacitor.
CPN
17
P
Charge pump flying capacitor negative terminal. Connect one side of the flying capacitor to CPN.
CPP
18
P
Charge pump flying capacitor positive terminal. Connect one side of the flying capacitor to CPP.
GND
19
P
Charge pump ground. GND must be connected to common supply GND. It is recommended that
this pin be decoupled to the VDD of the charge pump pin (pin 20 on the QFN).
VDD
20
P
Charge pump voltage supply. VDD must be connected to the common VDD voltage supply. Decouple
to GND (pin 19 ) with its own 1 μF capacitor.
Die Pad
P
Solder the thermal pad on the bottom of the QFN package to the GND plane of the PCB. It is
required for mechanical stability and will enhance thermal performance.
NAME
GND
Thermal pad
DESCRIPTION
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7 Specification
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range, TA = 25°C (unless otherwise noted)
Supply voltage, VDD
RIGHTINx, LEFTINx
Input voltage
MAX
UNIT
6
V
CPVSS-0.2 V to minimum of
(3.6 V, VDD+0.2 V)
SD, TEST1, TEST2
Output continuous total power dissipation
MIN
–0.3
–0.3
7
V
See the Thermal Information Table
Operating free-air temperature range, TA
–40
85
°C
Operating junction temperature range, TJ
–40
150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
Electrostatic discharge
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
MIN
MAX
UNIT
–65
150
°C
–3
3
kV
–750
750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Supply voltage, VDD
VIH
High-level input voltage
TEST1, TEST2, SD
VIL
Low-level input voltage
SD
TA
MIN
MAX
2.5
5.5
1.3
12.8
Operating free-air temperature
–40
V
V
0.35
Minimum Load Impedance
UNIT
V
Ω
85
°C
7.4 Thermal Information
THERMAL METRIC (1)
RTJ
20 PINS
RθJA
Junction-to-ambient thermal resistance
34.8
RθJC(top)
Junction-to-case (top) thermal resistance
32.5
RθJB
Junction-to-board thermal resistance
11.6
ψJT
Junction-to-top characterization parameter
0.4
ψJB
Junction-to-board characterization parameter
11.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.1
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
|VOS|
Output offset voltage
VDD = 2.5 V to 5.5 V, inputs grounded
135
400
μV
PSRR
DC Power supply rejection ratio VDD = 2.5 V to 5.5 V, inputs grounded
–101
-85
dB
CMRR
Common mode rejection ratio
VDD = 2.5 V to 5.5 V
|IIH|
High-level input current
VDD = 5.5 V, VI = VDD
|IIL|
Low-level input current
VDD = 5.5 V, VI = 0 V
IDD
Supply current
–69
TEST1, TEST2
dB
1
SD
10
SD
VDD = 2.5 V to 5.5 V, SD = VDD
Shutdown mode, VDD = 2.5V to 5.5 V, SD = 0 V
µA
1
µA
4.2
6
mA
0.08
1
µA
7.6 Operating Characteristics
VDD = 3.6 V , TA = 25°C, RL = 16 Ω (unless otherwise noted)
PARAMETER
PO
Output power
TEST CONDITIONS
Stereo, Outputs out of phase,
THD = 1%, f = 1 kHz, Gain = +4 dB
MIN
63
VDD = 3.6V
133
VDD = 5V
142
f = 100 Hz
THD+N
Total harmonic distortion
plus noise
PO = 35 mW
Supply ripple rejection ratio
Av
Channel DC Gain
ΔAv
Gain matching
f = 1 kHz
0.007%
f = 20 kHz
0.0021%
-94.3
200 mVpp ripple, f = 1 kHz
Noise output voltage
fosc
Charge pump switching
frequency
SNR
UNIT
mW
-85
-92
200 mVpp ripple, f = 20 kHz
-77.1
SD = VDD
1.597
dB
V/V
0.1%
Slew rate
Vn
MAX
0.0096%
200 mVpp ripple, f = 217 Hz
kSVR
TYP
VDD = 2.5V
VDD = 3.6V, A-weighted, Gain = +4 dB
300
0.4
V/µs
12
µVRMS
381
500
kHz
Start-up time from shutdown
4.8
ms
Differential input impedance
36.6
kΩ
Signal-to-noise ratio
Thermal shutdown
ZO
HW Shutdown HP output
impedance
CO
Output capacitance
Po = 35 mW
93
dB
Threshold
180
°C
Hysteresis
35
°C
112
Ω
80
pF
SD = 0 V, measured output to ground.
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7.7 Typical Characteristics
Table 1. Table of Graphs
Figure
Total harmonic distortion + noise
versus Output power
Figure 1–Figure 4
Total harmonic distortion + noise
versus Frequency
Figure 5–Figure 12
Supply voltage rejection ratio
versus Frequency
Figure 13-Figure 14
Common mode rejection ratio
versus Frequency
Figure 15-Figure 16
Crosstalk
versus Frequency
Figure 17-Figure 18
C(PUMP, DECOUPLE, ,BYPASS, CPVSS) = 1 μF, CI = 2.2 µF.
All THD + N graphs taken with outputs out of phase (unless otherwise noted).
10
10
VDD = 3.6V
f = 1kHz
RL = 16
Stereo
VDD = 3.6V
f = 1kHz
RL = 32
Stereo
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
Out of Phase
Out of Phase
In Phase
0.001
0.01
0.1
In Phase
0.001
0.01
1
0.1
Output Power (W)
1
Output Power (W)
C007
C007
Figure 1. Total Harmonic Distortion + Noise vs Output
Power
Figure 2. Total Harmonic Distortion + Noise vs Output
Power
10
10
VDD = 2.5V
f = 1kHz
RL = 16
Stereo
VDD = 2.5V
f = 1kHz
RL = 32
Stereo
1
THD+N (%)
THD+N (%)
1
0.1
VDD = 2.5V
0.01
0.1
VDD = 2.5V
0.01
VDD = 3.0V
VDD = 3.0V
VDD = 3.6V
VDD = 3.6V
VDD = 5.0V
0.001
0.001
0.01
0.1
VDD = 5.0V
1
0.001
0.001
Output Power (W)
0.1
1
Output Power (W)
C006
Figure 3. Total Harmonic Distortion + Noise vs Output
Power
6
0.01
C006
Figure 4. Total Harmonic Distortion + Noise vs Output
Power
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All THD + N graphs taken with outputs out of phase (unless otherwise noted).
1
1
VDD = 2.5V
RL = 16
VDD = 3.0V
RL = 16
THD+N (%)
0.1
THD+N (%)
0.1
0.01
0.01
Po = 1mW
Po = 5mW
Po = 4mW
Po = 20mW
Po = 20mW
Po = 40mW
0.001
0.001
20
200
2k
20k
20
200
Frequency (Hz)
2k
20k
Frequency (Hz)
C004
C004
Figure 5. Total Harmonic Distortion + Noise vs Frequency
Figure 6. Total Harmonic Distortion + Noise vs Frequency
1
1
VDD = 3.6V
RL = 16
VDD = 5.0V
RL = 16
THD+N (%)
0.1
THD+N (%)
0.1
0.01
0.01
Po = 5mW
Po = 5mW
Po = 35mW
Po = 50mW
Po = 70mW
Po = 80mW
0.001
0.001
20
200
2k
20k
20
200
Frequency (Hz)
2k
20k
Frequency (Hz)
C004
C004
Figure 7. Total Harmonic Distortion + Noise vs Frequency
Figure 8. Total Harmonic Distortion + Noise vs Frequency
1
1
VDD = 2.5V
RL = 32
VDD = 3.0V
RL = 32
THD+N (%)
0.1
THD+N (%)
0.1
0.01
0.01
Po = 1mW
Po = 5mW
Po = 4mW
Po = 20mW
Po = 20mW
Po = 40mW
0.001
0.001
20
200
2k
20k
20
Frequency (Hz)
200
2k
20k
Frequency (Hz)
C004
Figure 9. Total Harmonic Distortion + Noise vs Frequency
C004
Figure 10. Total Harmonic Distortion + Noise vs Frequency
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All THD + N graphs taken with outputs out of phase (unless otherwise noted).
1
1
VDD = 3.6V
RL = 32
VDD = 5.0V
RL = 32
THD+N (%)
0.1
THD+N (%)
0.1
0.01
0.01
Po = 5mW
Po = 5mW
Po = 35mW
Po = 50mW
Po = 70mW
Po = 80mW
0.001
0.001
20
200
2k
20k
20
200
Frequency (Hz)
2k
20k
Frequency (Hz)
C004
C004
Figure 11. Total Harmonic Distortion + Noise vs Frequency
Figure 12. Total Harmonic Distortion + Noise vs Frequency
0
0
-20
VDD = 5.0V
-40
-60
-80
-100
VDD = 2.5V
Vrip = 0.1VPK
RL = 32
Ci = 1µF
Stereo
VDD = 3.6V
Supply Voltage Rejection Ratio (dB)
-20
Supply Voltage Rejection Ratio (dB)
VDD = 2.5V
Vrip = 0.1VPK
RL = 16
Ci = 1µF
Stereo
VDD = 3.6V
VDD = 5.0V
-40
-60
-80
-100
-120
-120
20
200
2k
20k
20
200
Frequency (Hz)
2k
20k
Frequency (Hz)
C010
C010
Figure 13. Supply Voltage Rejection Ratio vs Frequency
Figure 14. Supply Voltage Rejection Ratio vs Frequency
0
0
VDD = 3.6V
VDD = 5.0V
-20
-30
-40
-50
-60
-70
VDD = 3.6V
VDD = 5.0V
-20
-30
-40
-50
-60
-70
-80
-80
20
200
2k
20k
20
Frequency (Hz)
200
2k
20k
Frequency (Hz)
C010
Figure 15. Common Mode Rejection Ratio vs Frequency
8
VDD = 2.5V
Vo = 0.1Vrms
RL = 32
Ci = 1µF
Stereo
-10
Common-mode Rejection Ratio (dB)
-10
Common-mode Rejection Ratio (dB)
VDD = 2.5V
Vo = 0.1Vrms
RL = 16
Ci = 1µF
Stereo
C010
Figure 16. Common Mode Rejection Ratio vs Frequency
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All THD + N graphs taken with outputs out of phase (unless otherwise noted).
0
0
-10
VDD = 3.6V
-10
-20
-20
-30
-30
-40
-50
VDD = 3.6V
VDD = 5.0V
-40
-50
-60
-60
-70
-70
-80
VDD = 2.5V
Vo = 1Vrms
RL = 32
Ci = 1µF
Stereo
VDD = 5.0V
Crosstalk (dB)
Crosstalk (dB)
VDD = 2.5V
Vo = 1Vrms
RL = 16
Ci = 1µF
Stereo
-80
20
200
2k
20k
20
Frequency (Hz)
200
2k
20k
Frequency (Hz)
C010
Figure 17. Crosstalk vs Frequency
C010
Figure 18. Crosstalk vs Frequency
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8 Detailed Description
8.1 Overview
Headphone channels and the charge pump are activated by asserting the SD pin to logic 1. The charge pump
generates a negative supply voltage for the output amplifiers. This allows a 0 V bias at the outputs, eliminating
the need for bulky output capacitors. The thermal block detects faults and shuts down the device before damage
occurs. The current limit block prevents the output current from getting high enough to damage the device. The
De-Pop block eliminates audible pops during power-up, power-down, and amplifier enable and disable events.
8.2 Functional Block Diagram
TEST2
TEST1
LEFTINM
HPLEFT
LEFT
LEFTINP
INPUT
STAGE
DEPOP
RIGHTINM
HPRIGHT
RIGHT
RIGHTINP
THERMAL
CURRENT
LIMIT
CPP
SD
CHARGE
PUMP
CPN
POWER
MANAGEMENT
SHUTDOWN
CONTROL
CPVSS
VDD
10
GND
VDD
GND
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8.3 Feature Description
8.3.1 Headphone Amplifiers
Single-supply headphone amplifiers typically require dc-blocking capacitors. The capacitors are required because
most headphone amplifiers have a dc bias on the outputs pin. If the dc bias is not removed, power consumption
will be higher, and large amounts of dc current rush through the headphones, potentially damaging them. The top
drawing in Figure 19 illustrates the conventional headphone amplifier connection to the headphone jack and
output signal.
DC blocking capacitors are often large in value. The headphone speakers (typical resistive values of 16 Ω or 32
Ω) combine with the dc blocking capacitors to form a high-pass filter. Equation 1 shows the relationship between
the load impedance (RL), the capacitor (CO), and the cutoff frequency (fC).
1
fc +
2pRLC O
(1)
CO can be determined using Equation 2, where the load impedance and the cutoff frequency are known.
1
CO +
2pRLf c
(2)
If fc is low, the capacitor must then have a large value because the load resistance is small. Large capacitance
values require large package sizes. Large package sizes consume PCB area, stand high above the PCB,
increase cost of assembly, and can reduce the fidelity of the audio output signal.
Two different headphone amplifier applications are available that allow for the removal of the output dc blocking
capacitors. The capless amplifier architecture is implemented in the same manner as the conventional amplifier
with the exception of the headphone jack shield pin. This amplifier provides a reference voltage, which is
connected to the headphone jack shield pin. This is the voltage on which the audio output signals are centered.
This voltage reference is half of the amplifier power supply to allow symmetrical swing of the output voltages. Do
not connect the shield to any GND reference or large currents will result. The scenario can happen if, for
example, an accessory other than a floating GND headphone is plugged into the headphone connector. See the
second block diagram and waveform in Figure 19.
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Feature Description (continued)
Conventional
VDD
CO
VOUT
CO
VDD/2
GND
Capless
VDD
VOUT
VBIAS
GND
VBIAS
DirectPath
TM
VDD
GND
VSS
Figure 19. Amplifier Applications
The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump
to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by
the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at
zero volts with the capability to swing to the positive rail or negative rail. The DirectPath™ amplifier requires no
output dc blocking capacitors, and does not place any voltage on the sleeve. The bottom block diagram and
waveform of Figure 19 illustrate the ground-referenced headphone architecture. This is the architecture of the
TPA6133A2.
8.4 Device Functional Modes
8.4.1 Modes of Operation
The TPA6133A2 supports two modes of operation. When the SD pin is driven to logic 0, the device is in low
power mode where the charge pump is powered down, the headphone channel is disabled and the outputs are
pulled to ground. When the SD pin is driven to logic 1, the device enters an active mode with charge pump
powered up and headphone channel enabled with channel gain of +4dB. The transition from inactive to active
and active to inactive states is done softly to avoid audible artifacts.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPA6133A2 is a stereo DirectPath™ headphone amplifier with GPIO control. The TPA6133A2 has minimal
quiescent current consumption, with a typical IDD of 4.2 mA, making it optimal for portable applications.
9.2 Typical Application
VDD
Figure 20 shows a typical application circuit for the TPA6133A2 with a stereo headphone jack and supporting
power supply decupling capacitors.
CPN
CPP
VDD
20
19
18
CPVSS
1uF
GND
1uF
17
16
1
15
LEFTINM
CPVSS
0.47uF
1uF
2
14
LEFTINP
HPLEFT
0.47uF
Top View
3
13
GND
VDD
GND
4
12
RIGHTINP
VDD
0.47uF
1uF
5
11
RIGHTINM
HPRIGHT
0.47uF
GND
10
GND
9
TEST1
8
TEST2
7
SD
6
VDD
SD
2.2KQ
Figure 20. Simplified Applications Circuit
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 2. Design Parameters
DESIGN PARAMTER
EXAMPLE VALUE
Input voltage
2.5 V – 5.5 V
Minimum current limit
4 mA
Maximum current limit
6 mA
9.2.2 Detailed Design Procedure
9.2.2.1 Input-Blocking Capacitors
DC input-blocking capacitors block the dc portion of the audio source, and allow the inputs to properly bias.
Maximum performance is achieved when the inputs of the TPA6133A2 are properly biased. Performance issues
such as pop are optimized with proper input capacitors.
The dc input-blocking capacitors may be removed provided the inputs are connected differentially and within the
input common mode range of the amplifier, the audio signal does not exceed ±3 V, and pop performance is
sufficient.
CIN is a theoretical capacitor used for mathematical calculations only. Its value is the series combination of the dc
input-blocking capacitors, C(DCINPUT-BLOCKING). Use Equation 3 to determine the value of C(DCINPUT-BLOCKING). For
example, if CIN is equal to 0.22 μF, then C(DCINPUT-BLOCKING) is equal to about 0.47 μF.
1 C
CIN =
(DCINPUT-BLOCKING)
2
(3)
The two C(DCINPUT-BLOCKING) capacitors form a high-pass filter with the input impedance of the TPA6133A2. Use
Equation 3 to calculate CIN, then calculate the cutoff frequency using CIN and the differential input impedance of
the TPA6133A2, RIN, using Equation 4. Note that the differential input impedance changes with gain. The
frequency and/or capacitance can be determined when one of the two values are given.
1
1
fc IN +
or C IN + 2p fc R
2p RIN C IN
IN IN
(4)
If a high pass filter with a -3 dB point of no more than 20 Hz is desired over all gain settings, the minimum
impedance would be used in the above equation. The capacitor value by the above equation would be 0.215 μF.
However, this is CIN, and the desired value is for C(DCINPUT-BLOCKING). Multiplying CIN by 2 yields 0.43 μF, which is
close to the standard capacitor value of 0.47 μF. Place 0.47 μF capacitors at each input terminal of the
TPA6133A2 to complete the filter.
9.2.2.2 Charge Pump Flying Capacitor and CPVSS Capacitor
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The CPVSS capacitor must be at least equal to the flying capacitor in order to allow maximum charge transfer.
Low ESR capacitors are an ideal selection, and a value of 1 µF is typical.
9.2.2.3 Decoupling Capacitors
The TPA6133A2 is a DirectPath™ headphone amplifier that requires adequate power supply decoupling to
ensure that the noise and total harmonic distortion (THD) are low. Use good low equivalent-series-resistance
(ESR) ceramic capacitors, typically 1.0 µF. Find the smallest package possible, and place as close as possible to
the device VDD lead. Placing the decoupling capacitors close to the TPA6133A2 is important for the performance
of the amplifier. Use a 10 μF or greater capacitor near the TPA6133A2 to filter lower frequency noise signals.
The high PSRR of the TPA6133A2 will make the 10 μF capacitor unnecessary in most applications.
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9.2.2.4 Optional Test Setup
TPA6133A2
CI
+
Audio Precision
Measurement
Output
LEFTINM
HPLEFT
+
Rseries
CI
LEFTINP
-
Load
Low Pass
Filter
Audio Precision
Measurement
Input
VDD
GND
1 Pf
+
External Power
Supply
-
Figure 21. Test Setup
NOTE
Separate power supply decoupling caps are used on all VDD and CPVSS Pins
The low pass filter is used to remove harmonic content above the audible range.
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9.2.3 Application Curves
1
Output
SD
Disable
0.75
Voltage - V
0.5
0.25
0
-0.25
-0.5
-0.75
-1
0
200m
400m
600m
800m
1m
1.2m
1.4m
1.6m
1.8m
2m
7m
8m
9m
10m
t - Time - s
Figure 22. Shutdown Time
1
Output
0.75
SD Enable
Voltage - V
0.5
0.25
0
-0.25
-0.5
-0.75
-1
0
1m
2m
3m
4m
5m
6m
t - Time - s
Figure 23. Startup Time
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range of 2.5 V to 5.5 V. Therefore, the output
voltage range of power supply should be within this range and well regulated. The current capability of upper
power should not exceed the max current limit of the power switch.
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11 Layout
11.1 Layout Guidelimes
11.1.1 Exposed Pad On TPA6133A2RTJ Package
• Solder the exposed metal pad on the TPA6133A2RTJ QFN package to the a pad on the PCB. The pad on
the PCB may be grounded or may be allowed to float (not be connected to ground or power).
• If the pad is grounded, it must be connected to the same ground as the GND pins (3, 9, 10, 13, and 19). See
the layout and mechanical drawings at the end of the datasheet for proper sizing.
• Soldering the thermal pad improves mechanical reliability, improves grounding of the device, and enhances
thermal conductivity of the package.
11.1.2 GND Connections
• The GND pin for charge pump should be decoupled to the charge pump VDD pin, and the GND pin adjacent
to the Analog VDD pin should be separately decoupled to each other.
11.2 Layout Example
It is recommended to place a top layer ground pour for
shielding around TPA6130A2 and connect to lower main PCB
ground plane by multiple vias
Minimize charge pump cap series resistance.
Keep close to pins with zero vias.
Place decoupling caps as close to
1uf
TPA6120A2 pins as possible
VDD
1uf
20
0.47uf
19
18
17
16
TPA6133A2
1
15
HPLEFT
1uf
2
14
3
13
4
12
5
11
0.47uf
Audio
Source
VDD
HPRIGHT
0.47uf
1uf
6
7
8
9
10
0.47uf
VDD
Keep vias to ground plane away from
top layer ground pads to distribute
inductances
SD
Top Layer Ground Pour and PowerPad
Pad to top layer ground pour
Top Layer Signal Traces
Via to bottom Ground Plane
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12 Device and Documentation Support
12.1 Trademarks
DirectPath is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPA6133A2RTJR
ACTIVE
QFN
RTJ
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SIZ
Samples
TPA6133A2RTJT
ACTIVE
QFN
RTJ
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SIZ
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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