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TPD1E10B09-Q1
SLVSDN8A – AUGUST 2016 – REVISED SEPTEMBER 2016
TPD1E10B09-Q1 1-Channel ESD in 0402 Package With 10-pF Capacitance and 9-V
Breakdown
1 Features
3 Description
•
•
The TPD1E10B09-Q1 device is a bidirectional
electrostatic discharge (ESD) transient voltage
suppression (TVS) diode in a small 0402 industry
standard package. This TVS protection diode is
convenient for component placement in space-saving
applications and features low RDYN and high IEC
rating. The TPD1E10B09-Q1 is rated to dissipate
ESD strikes above the maximum level specified in the
IEC 61000-4-2 international standard (Level 4)
offering ±20-kV contact discharge and ±20-kV IEC
air-gap protection. ESD voltages can easily reach 5kV and during extreme conditions these voltages can
be significantly higher, causing damages to many
integrated circuits. For example, in a low humidity
environment voltages can exceed 20-kV.
1
•
•
•
•
•
•
•
•
•
AEC-Q101 Qualified
IEC 61000-4-2 Level 4 ESD Protection
– ±20-kV Contact Discharge
– ±20-kV Air-Gap Discharge
ISO 10605 (330pF, 330Ω) ESD Protection
– ±8-kV Contact Discharge
– ±15-kV Air-Gap Discharge
IEC 61000-4-5 Surge Protection
– 4.5 A (8/20 µs)
I/O Capacitance 10 pF (Typical)
RDYN: 0.5 Ω (Typical)
DC Breakdown Voltage ±9.5 V (Minimum)
Ultra Low Leakage Current 100 nA (Maximum)
13-V Clamping Voltage (Typical at IPP = 1 A)
Industrial Temperature Range: –40°C to +125°C
Space-Saving 0402 Footprint
The low dynamic resistance (0.5 Ω) and low clamping
voltage (13 V at 1-A IPP) ensures system level
protection against transient events, providing robust
protection on designs that are exposed to ESD
events. This device also features a 10-pF IO
capacitance making it ideal for audio lines, push
buttons, memory interfaces, or GPIOs.
2 Applications
•
•
This device is also available without automotive
qualification: TPD1E10B09.
End Equipment:
– Head Unit
– Premium Audio
– External Amplifier
– Body Control Module
– Gateway
– Telematics
– Camera Module
Interfaces:
– Audio Lines
– Pushbuttons
– Memory Interface
– GPIO
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPD1E10B09-Q1
X1SON (2)
0.60 mm × 1.00 mm
TPD1E10B09(2)
X1SON (2)
0.60 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) This device is not part of the TPD1E10B09-Q1 datasheet,
please see TPD1E10B09 for all electrical parameters and
device characteristics
Application Schematic
IO Line 1
IO Line 2
Connector
(Source of ESD)
1
1
2
2
ESD Sensitive Device
GND Line
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD1E10B09-Q1
SLVSDN8A – AUGUST 2016 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings—AEC Specification .............................
ESD Ratings—IEC Specification ..............................
ESD Ratings—ISO Specification ..............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application .................................................. 10
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Example .................................................... 12
11 Device and Documentation Support ................. 13
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
12 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
Changes from Original (August 2016) to Revision A
•
2
Page
Changed device status from Product Preview to Production Data ........................................................................................ 1
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SLVSDN8A – AUGUST 2016 – REVISED SEPTEMBER 2016
5 Pin Configuration and Functions
DPY Package
2-Pin X1SON
Top View
1
2
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
IO
I/O
2
GND
Ground
ESD protected I/O
Ground. Connect to ground
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TPD1E10B09-Q1
SLVSDN8A – AUGUST 2016 – REVISED SEPTEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MAX
UNIT
IPP
Peak pulse current (tp = 8/20 µs, positive)
MIN
5.5
A
IPP
Peak pulse current (tp = 8/20 µs, negative)
4.5
A
PPP
Peak pulse power (tp = 8/20 µs)
90
W
P
Power Dissipation (2)
162
mW
Tstg
(1)
(2)
Operating temperature
–40
125
°C
Storage temperature
–65
155
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Max junction temperature: 125°C; power dissipation calculated at 25°C ambient temperature using JEDEC High K board Standard. Not
to be used for steady state power dissipation in the breakdown region.
6.2 ESD Ratings—AEC Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2500
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 Contact Discharge
±20000
IEC 61000-4-2 Air-Gap Discharge
±20000
UNIT
V
6.4 ESD Ratings—ISO Specification
VALUE
V(ESD)
Electrostatic discharge
ISO 10605 (330 pF, 330 Ω) Contact Discharge
±8000
ISO 10605 (330 pF, 330 Ω) Air-Gap Discharge
±15000
UNIT
V
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
TA
Operating free-air temperature
Operating voltage
Pin 1 to 2 or pin 2 to 1
MIN
MAX
UNIT
–40
125
°C
–9
9
V
6.6 Thermal Information
TPD1E10B09-Q1
THERMAL METRIC (1)
DPY (X1SON)
UNIT
2 PINS
RθJA
Junction-to-ambient thermal resistance
615.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
404.8
°C/W
RθJB
Junction-to-board thermal resistance
493.3
°C/W
ψJT
Junction-to-top characterization parameter
127.7
°C/W
ψJB
Junction-to-board characterization parameter
493.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VRWM
Reverse stand-off voltage
Pin 1 to 2 or pin 2 to 1
ILEAK
Leakage current
Pin 1 = 5 V, pin 2 = 0 V
VClamp1,2
Clamp voltage with ESD strike on pin 1, pin 2
grounded
IPP = 1 A, tp = 8/20 μs (1)
13
IPP = 5 A, tp = 8/20 μs (1)
17
VClamp2,1
Clamp voltage with ESD strike on pin 2, pin 1
grounded
IPP = 1 A, tp = 8/20 μs (1)
13
IPP = 4.5 A, tp = 8/20 μs (1)
20
RDYN
Dynamic resistance
Pin 1 to pin 2 (2)
0.5
(2)
0.5
CIO
I/O capacitance
VIO = 2.5 V; f = 1 MHz
VBR1,2
Break-down voltage, pin 1 to pin 2
IIO = 1 mA
9.5
V
VBR2,1
Break-down voltage, pin 2 to pin 1
IIO = 1 mA
9.5
V
(1)
(2)
Pin 2 to pin 1
9
V
100
nA
10
V
V
Ω
pF
Non-repetitive current pulse 8/20 µs exponentially decaying waveform according to IEC 61000-4-5.
Extraction of RDYN using least squares fit of TLP characteristics from IPP = 10 A to IPP = 20 A.
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6.8 Typical Characteristics
10
80
0
70
-10
60
-20
Amplitude (V)
50
40
30
-30
-40
-50
20
-60
10
-70
0
-80
-10
-15
15
45
75
105
135
Time (nS)
165
195
-90
-15
225
30
27
27
24
24
21
21
18
15
12
105
135
Time (nS)
165
195
225
15
12
9
9
6
6
3
3
0
0
3
6
9
12
15
18
Voltage (V)
21
24
27
30
0
Figure 3. Transmission Line Pulse (TLP) Waveform Pin 1 to
Pin 2
800x10
-6
600x10-6
Current (A)
400x10-6
200x10-6
0x100
-200x10-6
-400x10-6
-600x10-6
-800x10-6
-1x10-3
-14 -12 -10 -8
-6
-4
-2 0 2
Voltage (V)
Figure 5. IV Curve
4
6
8
10 12 14
3
6
9
12
15
18
Voltage (V)
21
24
27
30
Figure 4. Transmission Line Pulse (TLP) Waveform Pin 2 to
Pin 1
1x10-3
Current (A)
75
18
0
6
45
Figure 2. ESD Clamp Voltage –8-kV Contact ESD
30
Current (A)
Current (A)
Figure 1. ESD Clamp Voltage 8-kV Contact ESD
15
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10
15
20
25
30
Time (nS)
35
140
Current (A) 130
Power (W) 120
110
100
90
80
70
60
50
40
30
20
10
0
40
45
50
Power (W)
Amplitude (V)
90
Figure 6. Positive Surge Waveform 8/20 µs
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0
5
10
15
20
25
30
Time (nS)
35
140
Current (A) 130
Power (W) 120
110
100
90
80
70
60
50
40
30
20
10
0
40
45
50
Capacitance (pF)
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Power (W)
Current (A)
Typical Characteristics (continued)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
Figure 7. Negative Surge Waveform 8/20 µs
0.5
1
1.5
2
2.5
3
VBIAS (V)
3.5
4
4.5
5
Figure 8. Pin Capacitance Across VBIAS
3
0
-3
-6
Gain (dB)
-9
-12
-15
-18
-21
-24
-27
-30
-33
103
104
105
106
107
Frequency (Hz)
108
109
1010
D001
Figure 9. Insertion Loss
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TPD1E10B09-Q1
SLVSDN8A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7 Detailed Description
7.1 Overview
The TPD1E10B09-Q1 is a single-channel ESD TVS that provides ±20-kV IEC 61000-4-2 (Level 4) contact and
air-gap ESD protection. The 10-pF back-to-back diode architecture is suitable for signals that range from –9 V to
9 V and supports data rates up to 500 Mbps. The industry-standard 0402 package is convenient for placement in
applications with limited space.
7.2 Functional Block Diagram
1
2
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
The TPD1E10B09-Q1 is a bidirectional TVS with high ESD protection level. This device protects circuit from ESD
strikes up to ±20-kV contact and ±20-kV air-gap specified in the IEC 61000-4-2 level 4 international standard.
The device can also handle up to 4.5-A surge current (IEC 61000-4-5 8/20 µs). The I/O capacitance of 10 pF
supports a data rate up to 500 Mbps. This clamping device has a small dynamic resistance of 0.5 Ω typically.
This makes the clamping voltage low when the device is actively protecting other circuits. For example, the
clamping voltage is only 13 V when the device is taking 1-A transient current. The breakdown is bidirectional so
that this protection device is a good fit for GPIO, especially audio lines which carry bidirectional signals. Low
leakage allows the diode to conserve power when working below the VRWM. The industrial temperature range of
–40°C to +125°C makes this ESD device work at extensive temperatures in most environments. The spacesaving 0402 package can fit into small electronic devices like mobile equipment and wearables.
7.3.1 AEC-Q101 Qualified
This device is qualified to AEC-Q101 standards and is qualified to operate from –40°C to +125°C.
7.3.2 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±20-kV contact and ±20-kV air according to the IEC 61000-4-2
standard. An ESD-surge clamp diverts the current to ground.
7.3.3 ISO 10605 ESD Protection
The I/O pins can withstand ESD events at least ±8-kV contact and ±15-kV air according to the ISO 10605 (330
pF, 330 Ω) standard. An ESD-surge clamp diverts the current to ground.
7.3.4 IEC 61000-4-5 Surge Protection
The IO pins can withstand surge events up to 5.5 A positive and 4.5 A negative (8/20 μs waveform). An ESDsurge clamp diverts this current to ground.
7.3.5 IO Capacitance
The capacitance between the I/O pins 10 pF. This capacitance support data rates up to 500 Mbps.
8
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Feature Description (continued)
7.3.6 Dynamic Resistance
The IO pins feature an ESD clamp that has a low RDYN of 0.50 Ω which prevents system damage during ESD
events.
7.3.7 DC Breakdown Voltage
The DC breakdown voltage between the IO pins is a minimum of 9.5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of 9 V.
7.3.8 Ultra Low Leakage Current
The IO pins feature an ultra-low leakage current of 100 nA (maximum) with a bias of 5 V.
7.3.9 Clamping Voltage
The IO pins feature an ESD clamp that is capable of clamping the voltage to 13 V (IPP = 1 A) and 17 V (IPP = 5
A).
7.3.10 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
7.3.11 Space-Saving Footprint
This device features a space-saving, industry standard 0402 footprint.
7.4 Device Functional Modes
The TPD1E10B09-Q1 is a passive clamp that has low leakage during normal operation when the voltage
between pin 1 and pin 2 is below VRWM and activates when the voltage between pin 1 and pin 2 goes above VBR.
During IEC ESD events, transient voltages as high as ±20 kV can be clamped between the two pins. When the
voltages on the protected lines fall below the trigger voltage, the device reverts back to the low leakage passive
state.
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TPD1E10B09-Q1
SLVSDN8A – AUGUST 2016 – REVISED SEPTEMBER 2016
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The The TPD1E10B09-Q1 is a single-channel back-to-back diode that protects one bidirectional signal line from
electrostatic discharge and surge pulses. Because the diode is bidirectional, the TPD1E10B09-Q1 protects
signals that have positive or negative polarity. During normal operation, the diode behaves as a 10-pF
capacitance to ground. Board layout is critical for optimal performance of any diode.
Placement: The diode must be placed very close to the external connector for optimal performance. Ideally, the
diode must be placed on the line that it is protecting.
Layout: Pin 1 of the diode must be right over the protected signal line. There must a thick and short trace from
pin 2 to ground. An example is shown in the Layout section.
8.2 Typical Application
A system with a human interface is vulnerable to large system-level ESD strikes that standard ICs cannot
survive. TVS ESD protection diodes are typically used to suppress ESD at these connectors. The TPD1E10B09Q1 is a single-channel ESD protection device containing back-to-back TVS diodes, which is typically used to
provide a path to ground for dissipating ESD events on bidirectional signal lines between a human interface
connector and a system. As the current from ESD passes through the device, only a small voltage drop is
present across the diode structure. This is the voltage presented to the protected IC. The low RDYN of the
triggered TVS holds this voltage, VCLAMP, to a tolerable level to the protected IC.
L Audio IN
Audio Amplifier
Class AB
(ESD Sensitive)
L Audio
L
GND
R Audio IN
Speaker
Connector
(Source of ESD)
1
1
R Audio
Audio Amplifier
Class AB
(ESD Sensitive)
R
GND
2
GND
2
Copyright © 2016, Texas Instruments Incorporated
Figure 10. Typical Application Schematic
8.2.1 Design Requirements
For this design example, two TPD1E10B09-Q1s are used to protect left and right audio channels. Table 1 lists
the known system parameters for this audio application.
Table 1. Design Parameters
DESIGN PARAMETER
10
VALUE
Audio amplifier class
AB
Audio signal voltage range
–8 V to 8 V
Audio frequency content
20 Hz to 20 kHz
Required IEC 61000-4-2 ESD protection
±15-kV Contact, ±15-kV Air-Gap
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8.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon; the designer must make sure:
• The voltage range on the protected line does not exceed the reverse standoff voltage of the TVS diode(s)
(VRWM).
• The operating frequency is supported by the I/O capacitance, CIO, of the TVS diode.
• The IEC 61000-4-2 protection requirement is covered by the IEC performance of the TVS diode.
For this application, the audio signal voltage range is –8 V to 8 V. The VRWM for the TVS is –9.5 V to 9.5 V;
therefore, the bidirectional TVS does not break down during normal operation, and normal operation of the audio
signal is not affected due to the signal voltage range. In this application, a bidirectional TVS like the
TPD1E10B09-Q1 is required.
Next, consider the frequency content of this audio signal. In this application with the class AB amplifier, the
frequency content is from 20 Hz to 20 kHz; ensure that the TVS I/O capacitance does not distort this signal by
filtering it. With the TPD1E10B09-Q1 typical capacitance of 10 pF, which leads to a typical cutoff frequency of
just under 500 MHz, this diode has sufficient bandwidth to pass the audio signal without distorting it.
Finally, the human interface in this application requires protection for ±15-kV Contact and ±15-kV Air-Gap ESD,
which is above the standard Level 4 IEC 61000-4-2 system-level ESD protection. A standard TVS cannot survive
this level of IEC ESD stress. However, the TPD1E10B09-Q1 can survive at least ±20-kV Contact and ±20-kV AirGap ESD. Therefore, the device can provide sufficient ESD protection for the interface, even though the
requirements are stringent. For any TVS diode to provide its full range of ESD protection capabilities, as well as
to minimize the noise and EMI disturbances the board will see during ESD events, it is crucial that a system
designer uses proper board layout of their TVS ESD protection diodes. See the Layout section for instructions on
properly laying out the TPD1E10B09-Q1.
90
10
80
0
70
-10
60
-20
Amplitude (V)
Amplitude (V)
8.2.3 Application Curves
50
40
30
-30
-40
-50
20
-60
10
-70
0
-80
-10
-15
15
45
75
105
135
Time (nS)
165
195
225
Figure 11. ESD Clamp Voltage 8-kV Contact ESD
-90
-15
15
45
75
105
135
Time (nS)
165
195
225
Figure 12. ESD Clamp Voltage –8-kV Contact ESD
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9 Power Supply Recommendations
This device is a passive TVS diode-based ESD protection device, so there is no need to power it. Do not violate
the maximum specifications for each pin.
10 Layout
10.1 Layout Guidelines
•
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Use rounded corners with the largest radii possible on the protected traces between the TVS and the
connector, thus eliminating any sharp corners.
– Electric fields tend to build up on corners, increasing EMI coupling.
If pin 1 or pin 2 is connected to ground, use a thick and short trace for this return path.
10.2 Layout Example
To connector
To protected IC
Place pin 1 on the signal line
Minimum
distance
from
connector
(source of
ESD)
Thick and short return path to GND
Figure 13. Layout Example
12
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• TPD1E10B09-Q1 Evaluation Module
• Reading and Understanding an ESD Protection Datasheet
• ESD Layout Guide
• ESD PROTECTION DIODES EVM
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPD1E10B09-Q1
13
TPD1E10B09-Q1
SLVSDN8A – AUGUST 2016 – REVISED SEPTEMBER 2016
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPD1E10B09-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD1E10B09QDPYRQ1
ACTIVE
X1SON
DPY
2
10000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
4N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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