TPD2E2U06DCKR

Product Folder Order Now Tools & Software Technical Documents Support & Community TPD2E2U06 ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 TPD2E2U06 双通道高速 ESD 保护器件 1 特性 • 1 • • • • • • • 3 说明 TPD2E2U06 是一款双通道低电容瞬态电压抑制器 (TVS) 二极管静电放电 (ESD) 保护器件。该器件可提 供符合 IEC 61000-4-2 标准的 ±25kV 接触 ESD 保护 和 ±30kV 气隙 ESD 保护。TPD2E2U06 的 1.5pF 线 路电容使得此器件适合于广泛的 应用中的数字输入 D 类音频放大器。典型应用接口为 USB 2.0，低压差分 信令 (LVDS) 接口和I2C™。 IEC 61000-4-2 4 级 – ±25kV（接触放电） – ±30kV（气隙放电） IEC 61000-4-5 浪涌保护 – 5.5A 峰值脉冲电流（8/20µs 脉冲） IO 电容值 1.5pF（典型值） 直流击穿电压 6.5V（最小值） 超低泄漏电流 10nA（最大值） 低 ESD 钳位电压 工业温度范围：-40℃ 至 +125°C 易于布线的小型 DRL 和 DCK 封装 器件信息(1) 器件型号 • 封装尺寸（标称值） SOT (5) 1.60mm × 1.20mm TPD2E2U06DCK SC70 (3) 2.0mm × 1.25mm (1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附 录。 2 应用 • 封装 TPD2E2U06DRL 终端设备 – 机顶盒 – 笔记本 – 服务器 – 电子销售点 (EPOS) 接口 – USB 2.0 – 以太网 – MIPI 总线 – LVDS – I2C 简化原理图 Power Supply D+ USB 2.0 Transceiver USB 2.0 Connector Vbus DGND 3 5 TPD2E2U06 4 GND 1 本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确 性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。 English Data Sheet: SLLSEG9 TPD2E2U06 ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com.cn 目录 1 2 3 4 5 6 7 特性 .......................................................................... 应用 .......................................................................... 说明 .......................................................................... 修订历史记录 ........................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 4 4 4 4 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 8 7.4 Device Functional Modes.......................................... 9 8 Application and Implementation ........................ 10 8.1 Application Information............................................ 10 8.2 Typical Application ................................................. 10 9 Power Supply Recommendations...................... 11 10 Layout................................................................... 11 10.1 Layout Guidelines ................................................. 11 10.2 Layout Example .................................................... 12 11 器件和文档支持 ..................................................... 12 11.1 11.2 11.3 11.4 商标 ....................................................................... 接收文档更新通知 ................................................. 支持资源................................................................ Glossary ................................................................ 12 12 12 12 12 机械、封装和可订购信息 ....................................... 12 4 修订历史记录 Changes from Revision B (May 2015) to Revision C Page • Added DCK Package to the Pin Configuration and Functions section................................................................................... 3 • Added DCK Package to the Electrical Characteristics table ................................................................................................. 4 Changes from Revision A (June 2013) to Revision B Page • 已添加 添加了“ESD 额定值”表、“特性 说明 ”部分、器件功能模式、“应用和实施”部分、“电源相关建议”部分、“布局”部 分、“器件和文档支持”部分以及“机械、封装和可订购信息”部分。 .......................................................................................... 1 2 Copyright © 2013–2019, Texas Instruments Incorporated TPD2E2U06 www.ti.com.cn ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 5 Pin Configuration and Functions DRL Package 5-Pin SOT Top View NC NC IO1 5 1 IO2 2 3 4 GND DCK Package 3-Pin SC70 Top View IO1 1 3 IO2 GND 2 Pin Functions PIN NAME I/O DESCRIPTION DRL DCK IO1 3 1 I/O IO2 5 2 I/O NC 1, 2 — - This pin is not connected and is left floating, grounded, or connected to VCC. 4 3 G The GND (ground) pin is connected to ground. GND The IO1 and IO2 pins are an ESD protected channel. Connect these pins to the data line as close to the connector as possible. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT IPP Peak pulse current (tp = 8/20 μs) 5.5 (1) A PPP Peak pulse power (tp = 8/20 μs) DRL package 85 (1) W PPP Peak pulse power (tp = 8/20 μs) DCK package 75 (1) W (1) Operating temperature –40 125 °C Storage temperature –65 155 °C Measured at 25°C. Copyright © 2013–2019, Texas Instruments Incorporated 3 TPD2E2U06 ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com.cn 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 EC 61000-4-2 contact ±25000 EC 61000-4-2 air-gap ±30000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIO Input Pin Voltage TA Operating Free Air Temperature NOM MAX UNIT 0 5.5 V -40 125 °C 6.4 Thermal Information TPD2E2U06 THERMAL METRIC (1) DRL DCK 5 PINS 3 PINS RθJA Junction-to-ambient thermal resistance 286.8 308.3 RθJC(top) Junction-to-case (top) thermal resistance 130.7 170.7 RθJB Junction-to-board thermal resistance 104.8 89.2 ψJT Junction-to-top characterization parameter 25.6 34.2 ψJB Junction-to-board characterization parameter 104.3 88.6 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VRWM Reverse stand-off voltage IIO < 10 µA VCLAMP IO to GND IPP = 1 A, TLP (1) 9.7 IPP = 5 A, TLP (1) 12.4 IPP = 1 A, TLP (1) 1.9 (1) 4 VCLAMP GND to IO IPP = 5 A, TLP MAX 5.5 UNIT V V V RDYN Dynamic resistance DRL package IO to GND (2) 0.5 Ω RDYN Dynamic resistance DRL package GND to IO (2) 0.25 Ω RDYN Dynamic resistance DCK package IO to GND (2) 0.6 Ω RDYN Dynamic resistance DCK package GND to IO (2) 0.4 Ω CL Line capacitance f = 1 MHz, VBIAS = 2.5 V (3) 1.5 1.9 pF CCROSS Channel-to-channel input capacitance Pin 4 = 0 V, f = 1 MHz, VBIAS = 2.5 V, between channel pins (3) 0.02 0.03 pF (1) (2) (3) 4 Transmission Line Pulse with 10-ns rise time, 100-ns width. Extraction of RDYN Using least squares fit of TLP characteristics between I = 20 A and I = 30 A. Measured at 25°C. Copyright © 2013–2019, Texas Instruments Incorporated TPD2E2U06 www.ti.com.cn ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS ∆CIO-TO-GND Variation of channel input capacitance Pin 4 = 0 V, f = 1 MHz, VBIAS = 2.5 V, channel_x pin to GND – channel_y pin to GND (3) VBR Break-down voltage IIO = 1 mA ILEAK Leakage current VIO = 2.5 V Copyright © 2013–2019, Texas Instruments Incorporated MIN TYP MAX 0.03 0.1 6.5 1 UNIT pF 8.5 V 10 nA 5 TPD2E2U06 ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com.cn 30 30 25 25 20 20 Current (A) Current (A) 6.6 Typical Characteristics 15 15 10 10 5 5 0 0 0 5 10 15 20 25 30 35 40 45 Voltage (V) 50 0 5 10 Figure 1. TLP, Data to GND 30 35 40 45 50 C003 Figure 2. TLP, GND to Data 0 ±15 90 ±30 75 Voltage (V) Voltage (V) 25 15 105 60 45 30 ±45 ±60 ±75 ±90 ±105 15 ±120 0 ±135 ±15 ±150 0 25 50 75 100 125 150 175 200 Time (ns) ±10 15 40 65 90 115 140 165 Time (ns) C004 Figure 3. IEC 61000-4-2 Clamping Voltage, +8 kV Contact 190 C005 Figure 4. IEC 61000-4-2 Clamping Voltage, –8 kV Contact 500 0.001 400 Current (pA) 0.0005 Current (A) 20 Voltage (V) 120 0 -0.0005 300 200 100 0 -0.001 ±2 ±1 0 1 2 3 4 5 6 Voltage (V) 7 8 9 10 0 20 40 60 80 100 Temperature (ƒC) C006 120 C007 VIN 2.5 V TA = 25°C Figure 5. IV Curve 6 15 C002 Figure 6. ILEAK vs Temperature Copyright © 2013–2019, Texas Instruments Incorporated TPD2E2U06 www.ti.com.cn ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 Typical Characteristics (continued) 2.2 6.5 100 Current 90 Power 5.2 80 1.6 3.9 60 50 2.6 40 Power (W) 70 1.8 Current (A) Capacitance (pF) 2 30 1.4 1.3 20 1.2 10 F = 1 MHz 0.0 1 0 0 ±5 0 1 2 3 4 5 10 15 5 IO Voltage (V) 20 25 30 35 40 45 50 Time ( S) C009 C008 f = 1 MHz Gain (dB) Figure 7. Capacitance Across VBIAS 1 0 ±1 ±2 ±3 ±4 ±5 ±6 ±7 ±8 ±9 ±10 ±11 ±12 100k Figure 8. Surge Curve (tp = 8/20 μs) IO to GND 1M 10M 100M Frequency (Hz) 1000M 10000M C010 Figure 9. Insertion Loss Copyright © 2013–2019, Texas Instruments Incorporated 7 TPD2E2U06 ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com.cn 7 Detailed Description 7.1 Overview The TPD2E2U06 is a dual-channel low capacitance TVS diode ESD protection device. The device offers ±25-kV contact and ±30-kV air-gap ESD protection in accordance with the IEC 61000-4-2 standard. The 1.5-pF line capacitance of the TPD2E2U06 makes the device suitable for a wide range of applications. Typical application interfaces are USB 2.0, LVDS, and I2C. 7.2 Functional Block Diagram IO1 IO2 GND 7.3 Feature Description The TPD2E2U06 is a dual-channel low capacitance TVS diode ESD protection device. The device offers ±25-kV contact and ±30-kV air-gap ESD protection in accordance with the IEC 61000-4-2 standard. The 1.5-pF line capacitance of the TPD2E2U06 makes the device suitable for a wide range of applications. Typical application interfaces are USB 2.0, LVDS, and I2C. 7.3.1 IEC 61000-4-2 Level 4 The I/O pins can withstand ESD events up to ±25-kV contact and ±30-kV air. An ESD/surge clamp diverts the current to ground. 7.3.2 IO Capacitance The capacitance between each I/O pin to ground is 1.5 pF. These capacitances support data rates in excess of 1.5 Gbps. 7.3.3 DC Breakdown Voltage The DC breakdown voltage of each I/O pin is a minimum of 6.5 V. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of 5.5 V. 7.3.4 Ultra-Low Leakage Current The I/O pins feature an ultra-low leakage current of 10 nA (Max) with a bias of 2.5 V. 7.3.5 Low ESD Clamping Voltage The I/O pins feature an ESD clamp that is capable of clamping the voltage to 9.7 V (IPP = 1 A). 8 Copyright © 2013–2019, Texas Instruments Incorporated TPD2E2U06 www.ti.com.cn ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 Feature Description (continued) 7.3.6 Industrial Temperature Range This device is designed to operate from –40°C to 125°C. 7.3.7 Small Easy-to-Route Package The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers flow-through routing, requiring minimal modification to an existing layout. 7.4 Device Functional Modes TPD2E2U06 is a passive integrated circuit that triggers when voltages are above VBR or below the lower diodes Vf (–0.6 V). During ESD events, voltages as high as ±30 kV (air) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels of TPD2E2U06 (usually within 10’s of nano-seconds) the device reverts to passive. Copyright © 2013–2019, Texas Instruments Incorporated 9 TPD2E2U06 ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com.cn 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information TPD2E2U06 is a diode type TVS which is typically used to provide a path to ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC. 8.2 Typical Application Power Supply D+ USB 2.0 Transceiver USB 2.0 Connector Vbus D3 GND 5 TPD2E2U06 4 GND Figure 10. Typical USB Application Diagram 8.2.1 Design Requirements For this design example, one TPD2E2U06 device will be used in a USB 2.0 application. This will provide complete port protection. Given the USB 2.0 application, the following parameters are known. DESIGN PARAMETER VALUE Signal range on Pins 3 or 5 0 V to 3.3 V Operating Frequency 240 MHz 8.2.2 Detailed Design Procedure To begin the design process, some parameters must be decided upon; the designer needs to know the following: • Signal range of all the protected lines • Operating frequency 10 Copyright © 2013–2019, Texas Instruments Incorporated TPD2E2U06 www.ti.com.cn ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 8.2.2.1 Signal Range The TPD2E2U06 has 2 identical protection channels for signal lines. The symmetry of the device provides flexibility when selecting which of the 2 I/O channels will protect which signal lines. Any I/O will support a signal range of 0 to 5.5 V. 8.2.2.2 Operating Frequency The TPD2E2U06 has a capacitance of 1.5 pF (Typ), supporting USB 2.0 data rates. 8.2.3 Application Curves 1 Gain (dB) 0 ±1 ±2 ±3 ±4 100k 1M 10M 100M 1000M Frequency (Hz) 10000M C011 Figure 11. Insertion Loss Graph 9 Power Supply Recommendations This device is a passive ESD protection device and there is no need to power it. Care should be taken to make sure that the maximum voltage specifications for each line are not violated. 10 Layout 10.1 Layout Guidelines • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 版权 © 2013–2019, Texas Instruments Incorporated 11 TPD2E2U06 ZHCSB74C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com.cn 10.2 Layout Example IO2 IO1 GND = VIA to GND Figure 12. Routing with DRL Package 11 器件和文档支持 11.1 商标 E2E is a trademark of Texas Instruments. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. 11.2 接收文档更新通知 要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品 信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。 11.3 支持资源 TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 机械、封装和可订购信息 以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且 不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。 12 版权 © 2013–2019, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPD2E2U06DCKR ACTIVE SC70 DCK 3 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1GH TPD2E2U06DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 DT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of