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TPD2S017
SLLS949B – SEPTEMBER 2009 – REVISED DECEMBER 2015
TPD2S017 2-Channel Ultra-Low Clamp Voltage ESD
Solution With Series-Resistor Isolation
1 Features
3 Description
•
The TPD2S017 is a two channel electrostatic
discharge (ESD) protection device. This protection
product offers two-stage ESD transient voltage
suppression (TVS) diodes in each line with a typically
1-Ω series resistor isolation. This architecture allows
the device to clamp at a very low voltage during
system level ESD strikes.
1
•
•
•
•
•
•
Ultra-Low Clamping Voltage Ensures the
Protection of Ultra-Low Voltage Core Chipset
During ESD Events
IEC 61000-4-2 ESD Protection
Matching of Series Resistor (R = 1 Ω) of ±8 mΩ
(Typical)
Differential Channel Input Capacitance Matching
of 0.02 pF (Typical)
High-Speed Data Rate and EMI Filter Action at
High Frequencies (–3 dB Bandwidth, ≉3 GHz)
Available in 6-Pin Small-Outline Transistor [SOT23 (DBV)] Package
Easy Straight-Through Routing Packages
2 Applications
•
•
•
•
•
Hi-Speed USBs
IEEE 1394 Interfaces
Low-Voltage Differential Signaling (LVDS)
Mobile Display Digital Interfaces (MDDI) and
Mobile Industry Processor Interfaces (MIPI)
HS Signals
The TPD2S017 conforms to the IEC61000-4-2 ESD
protection standard. Due to the series resistor
component, the TPD2S017 provides a controlled filter
roll-off for even greater spurious EMI suppression and
signal integrity. The monolithic silicon technology
allows good matching of the component values,
including the clamp capacitances and the series
resistors between the differential signal pairs. The
tight matching of the line capacitance and series
resistors ensures that the differential signal distortion
due to added ESD clamp remains minimal, and it also
allows the part to operate at high-speed differential
data rate (in excess of 1.5 Gbps). The DBV package
offers a flow-through pin mapping for ease of board
layout.
Typical applications of this ESD protection device are
circuit protection for USB data lines, IEEE 1394
Interfaces, LVDS, MDDI/MIPI and HS signals.
Device Information(1)
PART NUMBER
TPD2S017
PACKAGE
SOT-23 (6)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Schematic
Power Supply
Vcc (optional)
TPD2S017
CH1
Ch1_In
Ch1_Out
Connector
(source of ESD)
ESD sensitive
device
CH2
Ch2_In
Ch2_Out
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD2S017
SLLS949B – SEPTEMBER 2009 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
3
3
4
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 6
7.1 Overview ................................................................... 6
7.2 Functional Block Diagram ......................................... 6
7.3 Feature Description................................................... 6
7.4 Device Functional Modes.......................................... 6
8
Application and Implementation .......................... 7
8.1 Application Information.............................................. 7
8.2 Typical Application ................................................... 7
9 Power Supply Recommendations........................ 9
10 Layout..................................................................... 9
10.1 Layout Guidelines ................................................... 9
10.2 Layout Example ...................................................... 9
11 Device and Documentation Support ................. 10
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
10
10
10
10
12 Mechanical, Packaging, and Orderable
Information ........................................................... 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2015) to Revision B
•
Added ƒ = 10 MHz to the test condition of IO capacitance in the Electrical Characteristics table ....................................... 4
Changes from Original (September 2009) to Revision A
•
2
Page
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SLLS949B – SEPTEMBER 2009 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
Ch1_Out
1
6
Ch2_Out
GND
2
5
VCC
Ch1_In
3
4
Ch2_In
Pin Functions
PIN
NAME
NO.
Ch1_In
3
Ch2_In
4
Ch1_Out
1
Ch2_Out
6
GND
VCC
I/O
DESCRIPTION
I
High-speed ESD clamp input
O
High-speed ESD clamp output
2
—
Ground
5
—
Optional power
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
0
5
V
Operating temperature
–40
85
°C
Storage temperature
–85
125
°C
VIO
IO voltage
TA
Tstg
(1)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±15000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
IEC 61000-4-2 Contact Discharge
±11000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Operating free-air temperature, TA
Operating voltage
NOM
MAX
–40
85
VCC
0
5
Ch1_In
0
VCC
Ch2_In
0
VCC
UNIT
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°C
V
3
TPD2S017
SLLS949B – SEPTEMBER 2009 – REVISED DECEMBER 2015
www.ti.com
6.4 Thermal Information
TPD2S017
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
192.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
166.2
°C/W
RθJB
Junction-to-board thermal resistance
39.8
°C/W
ψJT
Junction-to-top characterization parameter
44.7
°C/W
ψJB
Junction-to-board characterization parameter
39.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Ω
R
Series resistor
1
IIO
Current from I/O pins
VIO = 3 V
0.01
0.1
μA
ΔRS
Channel-to-channel resistance
match
VIO = 3 V
±8
±15
mΩ
VD
Diode forward voltage for lower
clamp
ID = 8 mA
–0.8
–0.95
RDYN
Dynamic resistance (for I/O clamp)
I=9A
CIO
IO capacitance
VIO = 2.5 V; ƒ = 10 MHz
VBR
Break-down voltage
IO = 1 mA
–0.6
11
V
0.8
Ω
1
pF
12
V
6.6 Dissipation Ratings
(1)
4
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA ≤ 25°C
TA = 70°C
POWER RATING
DBV
463.18 mW
–4.63 mW/C
254.75 mW
Derating factor is defined as the inverse of the traditional junction-to-ambient thermal resistance (RθJA).
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SLLS949B – SEPTEMBER 2009 – REVISED DECEMBER 2015
6.7 Typical Characteristics
0
8.0
130
-1
7.2
117
6.4
104
-2
I/O to I/O
5.6
91
Current (A)
4.8
IPP (A)
-4
-5
78
4.0
65
Power (W)
3.2
PPP (W)
Insertion Loss (dB)
-3
52
-6
2.4
39
1.6
26
-8
0.8
13
-9
0.0
-7
1.000E+06
1.000E+07
1.000E+08
1.000E+09
0
0
1.000E+10
5
10
15
20
Frequency (Hz)
30
35
40
45
50
Figure 2. Peak Pulse Waveforms
Ch1_Out, PUT with respect to GND, VCC = 5 V
Figure 1. Insertion Loss Data (S21)
8.0
130
50
7.2
117
45
6.4
104
40
5.6
91
35
4.8
78
4.0
65
52
2.4
39
PPP (W)
Current (A)
3.2
30
Amplitude (V)
IPP (A)
25
Time (us)
25
20
15
Power (W)
1.6
26
0.8
13
0.0
0
10
5
0
5
10
15
20
25
30
35
40
45
50
0
Time (us)
-5
0
20
40
60
80
100
120
140
160
180
200
Time (ns)
Figure 3. Peak Pulse Waveforms
Ch2_In, PUT with respect to GND, VCC = 5 V
Figure 4. IEC Clamping Waveforms
8-kV Contact, 1-GHz Bandwidth
5
0
-5
-10
-15
Amplitude (V)
-20
-25
-30
-35
-40
-45
-50
-55
-60
0
20
40
60
80
100
120
140
160
180
200
Time (nS)
Figure 5. IEC Clamping Waveforms
–8-kV Contact, 1-GHz Bandwidth
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SLLS949B – SEPTEMBER 2009 – REVISED DECEMBER 2015
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7 Detailed Description
7.1 Overview
The TPD2S017 is a two-channel ESD protection device. The two-stage ESD diodes and 1-Ω isolation resistor
topology of the device gives the system very robust and good protection during ESD strikes. The TPD2S017
conforms to the IEC61000-4-2 ESD protection standard. The TPD2S017 provides a –3-dB frequency at almost 3
GHz which provides enough bandwidth for a vast majority of applications. Thanks to the monolithic silicon
technology, the tight matching of the line capacitances and series resistances ensures a minimum distorted
differential signal and a high operating differential data rate. The DBV package offers a flow-through pin mapping
for ease of board layout.
7.2 Functional Block Diagram
Vcc (optional)
TPD2S017
Ch1_In
Ch1_Out
Ch2_In
Ch2_Out
7.3 Feature Description
Each channel of the TPD2S017 device has a topology of two-stage clamps with isolation resistor. This topology
optimizes the clamping performance while supporting a high bandwidth. Due to the low clamping voltage, the
down stream circuits that connect to the output of the channels are well-protected. The high IEC 61000-4-2 level
ensures the system's robustness during the ESD events. The good matching of the resistor and capacitance
values will yield minimal distortion of the signals. The low resistance and capacitance values make sure that this
device supports a high differential data rate. The flow-through pinout ensures no additional layout burden on the
printed circuit board (PCB).
7.4 Device Functional Modes
The TPD2S017 device stays passive and has low leakage during normal operation when the voltage at the input
of each channel is from 0 V to VCC and activates when that voltage exceeds one forward diode drop above VCC
or below ground. During IEC ESD events, contact transient voltages as high as ±11 kV can be suppressed.
When the voltages on the protected lines fall below the trigger voltage, the device reverts back to the low
leakage passive state.
6
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
When a system contains a human interface connector, it becomes vulnerable to large system-level ESD strikes
that standard ICs cannot survive. Protection products are typically used to suppress ESD at these connectors.
TPD2S017 is a two-channel ESD protection device. In each channel, it contains two-stage TVS diodes and a
resistor between the two clamping stages as an isolation. This implementation provides good clamping
performance, minimal signal distortion and the support of high data speed.
8.2 Typical Application
VBUS
Power
Regulator
Vcc (optional)
TPD2S017
Ch1_In
D+
Ch1_Out
USB Connector
USB Controller
Ch2_In
D-
Ch2_Out
GND
Figure 6. Typical Application Schematic
8.2.1 Design Requirements
For this design example, a TPD2S017 will be used to protect the USB 2.0 high-speed data lines. The following
system parameters are known.
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
High-speed mode high-level output voltage
400 mV ±10%
High-speed mode low-level output voltage
0 V ± 10 mV
USB 2.0 high-speed data rate
480 Mbps
Required IEC 61000-4-2 ESD Protection
±8-kV Contact
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8.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon; the designer should make sure:
• Voltage range on the protected lines must not go beyond one forward diode drop above the VCC and must no
go below one forward diode drop below the ground.
• Operating frequency is supported by the IO capacitance CIO.
• IEC 61000-4-2 protection requirement is covered by the IEC performance of the TVS diode.
For this application, a high speed USB 2.0 signal that ranges from –10 mV to 440 mV will be applied to each line.
Connect a 5-V power supply to VCC pin; therefore, the signal will not fall outside of the normal operation range
and the TPD2S017 will stay passive and low leakage during normal operation.
Next, consider the data rate of this signal and ensure that the TVS I/O capacitance will not distort this signal by
filtering it. The speed of a USB 2.0 high-speed signal is 480 Mbit/s. With TPD2S017's ultra low IO capacitance,
this device can support 1.5 Gbit/s data rate and thus can pass USB 2.0 high-speed signal with minimal distortion.
Finally, TPD2S017 is rated for the IEC 61000-4-2 (Level 4) so it provides sufficient system-level ESD protection
to the human interface in this application. See Layout Example for instructions on properly laying out TPD2S017.
8.2.3 Application Curves
50
5
0
45
-5
40
-10
35
-15
30
Amplitude (V)
Amplitude (V)
-20
25
20
-25
-30
-35
15
-40
10
-45
5
-50
0
-55
-5
-60
0
20
40
60
80
100
120
140
160
180
200
0
20
Time (ns)
8
40
60
80
100
120
140
160
180
200
Time (nS)
Figure 7. IEC Clamping Waveforms
8-kV Contact, 1-GHz Bandwidth
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Figure 8. IEC Clamping Waveforms
–8-kV Contact, 1-GHz Bandwidth
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9 Power Supply Recommendations
The optional VCC power supply bias is recommended to lower the I/O capacitances. Ensure that the maximum
voltage specifications for each pin are not violated.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
Use thick and short traces for the power and ground paths.
Run differential signal lines in pair with small distance to optimize signal integrity.
10.2 Layout Example
Ch1_Out
Ch2_Out
GND
Vcc
Ch1_In
Ch2_In
Power Ground
LEGEND
VIA to Power Ground Plane
VIA to Power Supply Plane
Figure 9. Layout Recommendation
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TPD2S017
SLLS949B – SEPTEMBER 2009 – REVISED DECEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
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PACKAGE OPTION ADDENDUM
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12-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPD2S017DBVR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOT-23
DBV
6
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
NFT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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12-Oct-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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12-Oct-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPD2S017DBVR
Package Package Pins
Type Drawing
SPQ
SOT-23
3000
DBV
6
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
178.0
9.0
Pack Materials-Page 1
3.23
B0
(mm)
K0
(mm)
P1
(mm)
3.17
1.37
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD2S017DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
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EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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