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TPD4E02B04-Q1
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
适用于 USB Type-C 和 HDMI 2.0 的 TPD4E02B04-Q1 4 通道 ESD 保护
二极管
1 特性
•
•
1
•
•
•
•
•
•
•
•
•
•
符合 AEC-Q101
IEC 61000-4-2 4 级 ESD 保护
– ±12kV 接触放电
– ±15kV 气隙放电
ISO 10605（330pF，330Ω）ESD 保护
– ±10kV 接触放电
– ±10kV 气隙放电
IEC 61000-4-4 瞬态放电 (EFT) 保护
– 80A (5/50ns)
IEC 61000-4-5 浪涌保护
– 2A (8/20µs)
IO 电容：
– 0.25pF（典型值）
直流击穿电压：5.5V（最小值）
超低泄漏电流：10nA（最大值）
低 ESD 钳位电压：8.8V (5A TLP)
支持速率高达 10Gbps 的高速接口
工业温度范围：-40°C 至 +125°C
简易直通布线封装
2 应用
•
•
终端设备
– 音响主机
– 后座娱乐系统
– 远程信息处理
– USB 集线器
– 仪表组
– 车身控制模块
– 媒体接口
接口
– USB Type-C
– USB 3.1 第 2 代
– 高清多媒体接口 (HDMI) 2.0/1.4
– USB 3.0
– DisplayPort 1.3
– 10/100/1000Mbps 以太网
3 说明
TPD4E02B04-Q1 是一种经过汽车认证的双向 TVS
ESD 保护二极管阵列，用于 USB Type-C 和 HDMI
2.0 电路保护。TPD4E02B04-Q1 的额定 ESD 冲击消
散值高达 10kV，符合 ISO
10605（330pF，330Ω）ESD 标准。TPD4E02B04 的
额定 ESD 冲击消散值也达到了 IEC 61000-4-2 国际标
准（4 级）中规定的最高水平。
该器件的每个通道均 具有 一个 0.25pF IO 电容，适用
于保护速率高达 10Gbps 的高速接口（例如第 2 代
USB 3.1）。低动态电阻和低钳位电压确保系统级抗瞬
变事件保护。
TPD4E02B04-Q1 采用符合行业标准的 USON-10
(DQA) 封装。该封装 采用 直通布线，其引脚间距为
0.5mm，能够简化实现并缩短设计时间。
该器件还具有未经过汽车认证的型
号：TPD4E02B04。
器件信息(1)
器件型号
TPD4E02B04-Q1
封装
封装尺寸（标称值）
USON (10)
2.50mm x 1.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
典型应用原理图
USB Type-C
Connector
TPD4E02B04-Q1
SSRX1P
SSRX1N
SSTX1P
SSTX1N
TPD4E05U06-Q1
VBUS
SBU2
CC1
DPT
DMT
TPD4E05U06-Q1
DMB
DPB
SBU1
CC2
VBUS
TPD4E02B04-Q1
SSRX2N
SSRX2P
SSTX2N
SSTX2P
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDZ2
TPD4E02B04-Q1
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings—AEC Specification .............................
ESD Ratings—IEC Specification ..............................
ESD Ratings—ISO Specification ..............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Examples................................................... 15
11 器件和文档支持 ..................................................... 17
11.1
11.2
11.3
11.4
11.5
11.6
文档支持 ...............................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
17
17
17
17
17
17
12 机械、封装和可订购信息 ....................................... 17
4 修订历史记录
Changes from Original (June 2017) to Revision A
Page
•
首次公开发布数据表 ............................................................................................................................................................... 1
•
已更改 将 ISO 气隙额定值更改成了 10kV .............................................................................................................................. 1
•
已更改 将接触额定值更改成了 10kV....................................................................................................................................... 1
•
已更改 将接口以太网更改成了 10/100/1000Mbps .................................................................................................................. 1
2
Copyright © 2017, Texas Instruments Incorporated
TPD4E02B04-Q1
www.ti.com.cn
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
5 Pin Configuration and Functions
DQA Package
10-Pin USON
Top View
IO1
1
10
NC
IO2
2
9
NC
GND
3
8
GND
IO3
4
7
NC
IO4
5
6
NC
Pin Functions
PIN
NAME
NO.
GND
3
GND
8
IO1
1
IO2
2
IO3
4
IO4
5
NC
6
NC
7
NC
9
NC
10
TYPE
Ground
DESCRIPTION
Ground. Connect to ground
I/O
ESD protected channel
NC
Not connected; Used for optional straight-through routing. Can be left floating or
grounded
Copyright © 2017, Texas Instruments Incorporated
3
TPD4E02B04-Q1
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Electrical fast transient
Peak pulse
MAX
UNIT
IEC 61000-4-5 (5/50 ns) at 25°C
80
A
IEC 61000-4-5 power (tp - 8/20 µs) at 25°C
17
W
IEC 61000-4-5 Ccurrent (tp - 8/20 µs) at 25°C
2
A
TA
Operating free-air temperature
–40
125
°C
Tstg
Storage temperature
–65
155
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings—AEC Specification
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
UNIT
±2500
Charged-device model (CDM), per AEC Q100-011
V
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 contact discharge
±12000
IEC 61000-4-2 air-gap discharge
±15000
UNIT
V
6.4 ESD Ratings—ISO Specification
VALUE
V(ESD)
Electrostatic discharge
ISO 10605 330 pF, 330 Ω, IO
Contact discharge
±10000
Air-gap discharge
±10000
UNIT
V
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIO
Input pin voltage
–3.6
3.6
UNIT
V
TA
Operating free-air temperature
–40
125
°C
6.6 Thermal Information
TPD4E02B04-Q1
THERMAL METRIC
(1)
DQA (USON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
348.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
214.1
°C/W
RθJB
Junction-to-board thermal resistance
270.7
°C/W
ψJT
Junction-to-top characterization parameter
81.7
°C/W
ψJB
Junction-to-board characterization parameter
270.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017, Texas Instruments Incorporated
TPD4E02B04-Q1
www.ti.com.cn
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VRWM
Reverse stand-off voltage
IIO < 10 nA
VBRF
Breakdown voltage, any IO pin to
GND (1)
IIO = 1 mA, TA = 25°C
5.5
VBRR
Breakdown voltage, GND to any IO
pin (1)
IIO = 1 mA, TA = 25°C
–5.5
VHOLD
Holding voltage (2)
IIO = 1 mA
5.8
IPP = 1 A, TLP, from IO to GND
6.6
IPP = 5 A, TLP, from IO to GND
8.8
IPP = 1 A, TLP, from GND to IO
6.6
IPP = 5 A, TLP, from GND to IO
8.8
VCLAMP
Clamping voltage
ILEAK
Leakage current, any IO to GND
RDYN
Dynamic resistance
CL
(1)
(2)
UNIT
3.6
V
6.4
7.5
V
–6.4
–7.5
V
VIO = ±2.5 V
V
V
10
nA
IO to GND
0.47
GND to IO
0.47
Line capacitance
VIO = 0 V, f = 1 MHz, IO to GND, TA =
25°C
0.25
0.33
pF
Variation of line capacitance
Delta of capacitance between any two IO
pins, VIO = 0 V, f = 1 MHz, TA = 25°C,
GND = 0 V
0.01
0.07
pF
Channel to channel capacitance
Capacitance from one IO to another, VIO
= 0 V, f = 1 MHz, GND = 0 V
0.13
0.16
pF
ΔCL
CCROSS
–3.6
MAX
Ω
VBRF and VBRR are defined as the voltage when 1 mA is applied in the positive-going direction, before the device latches into the
snapback state.
VHOLD is defined as the voltage when 1 mA is applied in the negative-going direction, after the device has successfully latched into the
snapback state.
版权 © 2017, Texas Instruments Incorporated
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TPD4E02B04-Q1
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
www.ti.com.cn
30
30
25
25
20
20
Current (A)
Current (A)
6.8 Typical Characteristics
15
15
10
10
5
5
0
0
0
3
6
9
12
15
18
21
24
Voltage (V)
0
3
6
9
12
15
18
21
Voltage (V)
C001
图 1. Positive TLP Curve
24
C002
图 2. Negative TLP Curve
3
160
24
Current
Power
2.5
140
20
16
1.5
12
1
8
0.5
4
100
Voltage (V)
2
Power (W)
Current (A)
120
80
60
40
20
0
0
-5
0
5
10
15
20
25
Time (Ps)
30
35
40
0
45
-20
-25
D001
图 3. Surge Curve (tp = 8/20 µs), any IO pin to GND
0.5
0
0.45
Capacitance (pF)
-40
Voltage (V)
50
75
100 125
Time (ns)
150
175
200
225
D001
0.4
-20
-60
-80
-100
0.35
0.3
0.25
0.2
0.15
-120
0.1
-140
0.05
0
25
50
75
100 125
Time (ns)
150
图 5. –8-kV IEC Waveform
6
25
图 4. 8-kV IEC Waveform
20
-160
-25
0
175
200
225
D001
0
-3.6 -3 -2.4 -1.8 -1.2 -0.6 0 0.6 1.2 1.8 2.4
Bias Voltage (V)
3
3.6
D001
图 6. Capacitance vs Bias Voltage
版权 © 2017, Texas Instruments Incorporated
TPD4E02B04-Q1
www.ti.com.cn
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
Typical Characteristics (接
接下页)
0.6
0.5
Bias = -2.5V
Bias = 2.5V
0.45
0.5
0.35
Leakage (nA)
Capacitance (pF)
0.4
0.3
0.25
0.2
0.15
0.1
0.4
0.3
0.2
0.1
0.05
0
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (qC)
95
0
-40
110 125
-25
-10
5
D001
图 7. Capacitance vs Ambient Temperature
20 35 50 65
Temperature (qC)
80
95
110 125
D001
图 8. Leakage Current vs Temperature
1
0.5
0.75
0.4
Capacitance (pF)
Current (mA)
0.5
0.25
0
-0.25
0.3
0.2
-0.5
0.1
-0.75
-1
-7
-6
-5
-4
-3
-2
-1 0 1
Voltage (V)
2
3
4
5
6
0
6E+8
7
1E+9
2E+9
3E+9
Frequency (Hz)
D001
图 9. DC Voltage Sweep I-V Curve
5E+9 7E+9 1E+10
D001
图 10. Capacitance vs Frequency
40
5
0
35
-5
30
-10
Voltage (V)
Voltage (V)
25
20
15
10
-15
-20
-25
-30
-35
5
-40
0
-45
-5
-10
0
10
20
30
40 50 60
Time (ns)
70
80
90 100 110
D001
图 11. 8-kV IEC Waveform through 2-m HDMI Cable
版权 © 2017, Texas Instruments Incorporated
-50
-10
0
10
20
30
40 50 60
Time (ns)
70
80
90 100 110
D001
图 12. –8-kV IEC Waveform through 2-m HDMI Cable
7
TPD4E02B04-Q1
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
www.ti.com.cn
Typical Characteristics (接
接下页)
8
图 13. USB3.0 Eye Diagram (Bare Board)
图 14. USB3.0 Eye Diagram (With TPD4E02B04-Q1)
图 15. USB3.1 Gen 2 Eye Diagram (Bare Board)
图 16. USB3.1 Gen 2 Eye Diagram
(With TPD4E02B04-Q1)
图 17. HDMI2.0 6-Gbps TP2 Eye Diagram (Bare Board)
图 18. HDMI2.0 6-Gbps TP2 Eye Diagram (With TPD4E02B04Q1)
版权 © 2017, Texas Instruments Incorporated
TPD4E02B04-Q1
www.ti.com.cn
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
Typical Characteristics (接
接下页)
Insertion Loss (dB)
0
-3
-6
+
2E 10
+1
0
1E
1E
+9
1E
+8
1E
+7
1E
+6
3E
+5
-9
D001
Frequency (Hz)
图 19. Differential Insertion Loss
版权 © 2017, Texas Instruments Incorporated
9
TPD4E02B04-Q1
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPD4E02B04-Q1 is an automotive-qualified bidirectional ESD Protection Diode with ultra-low capacitance.
This device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 (Level 4)
International Standard. The ultra-low capacitance makes this device ideal for protecting any super high-speed
signal pins.
7.2 Functional Block Diagram
IO1
IO2
IO3
IO4
GND
7.3 Feature Description
7.3.1 AEC-Q101 Qualified
This device is qualified to AEC-Q101 standards and is qualified to operate from –40°C to +125°C.
7.3.2 ISO 10605 ESD Protection
The I/O pins can withstand ESD events of at least ±10-kV contact and ±10-kV air gap according to the ISO
10605 (330 pF, 330 Ω) standard. The device diverts the current to ground.
7.3.3 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air gap. An ESD-surge clamp diverts
the current to ground.
7.3.4 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground.
7.3.5 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2 A and 17 W (8/20 µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.6 IO Capacitance
The capacitance between each I/O pin to ground is 0.25 pF (typical). This device supports data rates up to 10
Gbps.
7.3.7 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of ±5.5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of ±3.6 V.
7.3.8 Ultra Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of ±2.5 V.
10
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TPD4E02B04-Q1
www.ti.com.cn
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
Feature Description (接
接下页)
7.3.9 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 8.8 V (IPP = 5 A).
7.3.10 Supports High Speed Interfaces
This device is capable of supporting high speed interfaces up to 10 Gbps, because of the extremely low IO
capacitance.
7.3.11 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
7.3.12 Easy Flow-Through Routing Package
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The TPD4E02B04-Q1 is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR.
During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network.
When the voltages on the protected line fall below the trigger levels of the TPD4E02B04-Q1 (usually within 10s
of nano-seconds) the device reverts to passive.
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TPD4E02B04-Q1
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD4E02B04-Q1 is a diode type TVS which is used to provide a path to ground for dissipating ESD events
on high-speed signal lines between a human interface connector and a system. As the current from ESD passes
through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the
protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
USB Type-C
Connector
TPD4E02B04-Q1
SSRX1P
SSRX1N
SSTX1P
SSTX1N
TPD4E05U06-Q1
VBUS
SBU2
CC1
DPT
DMT
TPD4E05U06-Q1
DMB
DPB
SBU1
CC2
VBUS
TPD4E02B04-Q1
SSRX2N
SSRX2P
SSTX2N
SSTX2P
Copyright © 2017, Texas Instruments Incorporated
图 20. USB 3.1 Gen 2 Type-C ESD Schematic
12
版权 © 2017, Texas Instruments Incorporated
TPD4E02B04-Q1
www.ti.com.cn
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
Typical Application (接
接下页)
图 21. USB 3.1 Gen 2 SuperSpeed Layout
8.2.1 Design Requirements
For this design example two TPD4E02B04-Q1 devices and two TPD4E05U06 devices are being used in a USB
3.1 Gen 2 Type-C application. This provides a complete ESD protection scheme.
Given the USB 3.1 Gen 2 Type-C application, the parameters listed in 表 1 are known.
表 1. Design Parameters
DESIGN PARAMETER
VALUE
Signal Range on SuperSpeed+ Lines
0 V to 3.6 V
Operating Frequency on SuperSpeed+ Lines
5 GHz
Signal Range on CC, SBU, and DP/DM Lines
0 V to 5 V
Operating Frequency on CC, SBU, and DP/DM Lines
up to 480 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The TPD4E02B04-Q1 supports signal ranges between –3.6 V and 3.6 V, which supports the SuperSpeed+ pairs
on the USB Type-C application. The TPD4E05U06 supports signal ranges between 0 V and 5.5 V, which
supports the CC, SBU, and DP/DM lines.
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8.2.2.2 Operating Frequency
The TPD4E02B04-Q1 has a 0.25 pF (typical) capacitance, which supports the USB3.1 Gen 2 data rates of 10
Gbps. The TPD4E05U06 has a 0.5 pF (typical) capacitance, which easily supports the CC, SBU, and DP/DM
data rates.
8.2.3 Application Curves
图 22. USB 3.1 Gen 2 10-Gbps Eye Diagram (Bare Board)
14
图 23. USB 3.1 Gen 2 10-Gbps Eye Diagram (With
TPD4E02B04-Q1)
版权 © 2017, Texas Instruments Incorporated
TPD4E02B04-Q1
www.ti.com.cn
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
9 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (–3.6 V to 3.6 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
SSTX2P
SSTX2N
SSRX2P
SSRX2N
TPD4E02B04-Q1
CC2
SBU1
DP_bot
DM_bot
TPD4E05U06-Q1
DP_top
DM_top
CC1
SBU2
TPD4E05U06-Q1
SSTX1P
SSTX1N
SSRX1P
TPD4E02B04-Q1
SSRX1N
10.2 Layout Examples
Legend
Top Layer
Bottom Layer
Pin to GND
VIA to VBUS Plane
VIA to Other Layer
VIA to GND Plane
图 24. USB Type-C Mid-Mount, Hybrid Connector with One-Sided ESD Layout
版权 © 2017, Texas Instruments Incorporated
15
TPD4E02B04-Q1
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
www.ti.com.cn
Layout Examples (接
接下页)
TPD4E02B04-Q1
TMDS_D2+
GND
TMDS_D2TMDS_D1+
GND
TMDS_D1TMDS_D0+
GND
TMDS_D0TMDS_CK+
GND
TMDS_CKCEC
UTILITY
DDC_CLK
DDC_DAT
GND
5V_OUT
HOTPLUG_DET
TMDS_D2+
TMDS_D2-
Legend
GND
Top Layer
Bottom Layer
Pin to GND
VIA to Other Layer
VIA to GND Plane
TMDS_D1+
TMDS_D1TPD4E02B04-Q1
TMDS_D0+
TMDS_D0GND
TMDS_CK+
TMDS_CKTPD4E05U06-Q1
CEC
UTILITY
GND
DDC_CLK
DDC_DAT
HOTPLUG_DET
To GPIO
GND
5V_SUPPLY
TPD3S014-Q1
图 25. HDMI2.0 Type-A Transmitter Port Layout
16
版权 © 2017, Texas Instruments Incorporated
TPD4E02B04-Q1
www.ti.com.cn
ZHCSGS8A – JUNE 2017 – REVISED SEPTEMBER 2017
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
• 《阅读并理解 ESD 保护数据表》，SLLA305
• 《ESD 布局布线指南》，SLVA680
• 《为超高速数据线选择 ESD 二极管》，SLVA785
• 《TPD4E02B04EVM 用户指南》，SLVUAH6
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD4E02B04QDQARQ1
ACTIVE
USON
DQA
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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