TPD4E02B04DQAR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPD4E02B04 SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 TPD4E02B04 4-Channel ESD Protection Diode for USB Type-C and HDMI 2.0 1 Features • 1 • • • • • • • • • • IEC 61000-4-2 Level 4 ESD Protection – ±12-kV Contact Discharge – ±15-kV Air Gap Discharge IEC 61000-4-4 EFT Protection – 80 A (5/50 ns) IEC 61000-4-5 Surge Protection – 2 A (8/20 µs) IO Capacitance: – 0.25 pF (Typical) – 0.33 pF (Maximum) DC Breakdown Voltage: 5.5 V (Minimum) Ultra Low Leakage Current: 10 nA (Maximum) Low ESD Clamping Voltage: 8.8 V at 5-A TLP Supports High Speed Interfaces up to 10 Gbps Industrial Temperature Range: –40°C to +125°C Easy Flow-Through Routing Package 2 Applications • Interfaces – USB Type-C – USB 3.1 Gen 2 – HDMI 2.0/1.4 – USB 3.0 – DisplayPort 1.3 – PCI Express 3.0 3 Description The TPD4E02B04 is a bidirectional TVS ESD protection diode array for USB Type-C and HDMI 2.0 circuit protection. The TPD4E02B04 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4). This device features a 0.25-pF IO capacitance per channel making it ideal for protecting high-speed interfaces up to 10 Gbps such as USB 3.1 Gen2. The low dynamic resistance and low clamping voltage ensure system level protection against transient events. The TPD4E02B04 is offered in the industry standard USON-10 (DQA) package. The package features flow-through routing and 0.5-mm pin pitch easing implementation and reducing design time. End Equipment – Laptops and Desktops – Set-Top Boxes – TV and Monitors – Mobile and Tablets – DVR and NVR Device Information(1) PART NUMBER TPD4E02B04 PACKAGE USON (10) BODY SIZE (NOM) 2.50 mm × 1.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Schematic USB Type-C TPD4E02B04 Connector SSRX1P SSRX1N SSTX1P SSTX1N TPD4E05U06 VBUS SBU2 CC1 DPT DMT TPD4E05U06 DMB DPB SBU1 CC2 VBUS TPD4E02B04 SSRX2N SSRX2P SSTX2N SSTX2P 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD4E02B04 SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. ESD Ratings—IEC Specification .............................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Application ................................................. 12 9 Power Supply Recommendations...................... 15 10 Layout................................................................... 15 10.1 Layout Guidelines ................................................. 15 10.2 Layout Examples................................................... 15 11 Device and Documentation Support ................. 17 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 17 17 17 17 17 17 12 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2016) to Revision B Page • Updated Capacitance spec in the Features, Description, , IO Capacitance and Operating Frequency sections.................. 1 • Made changes to Operating Frequency ................................................................................................................................. 1 • Updated Figure 15, Figure 16, Figure 22 and Figure 23 ....................................................................................................... 1 Changes from Original (Novemeber 2015) to Revision A • 2 Page Changed device status from Product Preview to Production Data ........................................................................................ 1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 TPD4E02B04 www.ti.com SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 5 Pin Configuration and Functions DQA Package 10-Pin USON Top View IO1 1 10 NC IO2 2 9 NC GND 3 8 GND IO3 4 7 NC IO4 5 6 NC Pin Functions PIN NAME NO. GND 3 GND 8 IO1 1 IO2 2 IO3 4 IO4 5 NC 6 NC 7 NC 9 NC 10 TYPE Ground DESCRIPTION Ground. Connect to ground I/O ESD protected channel NC Not connected; Used for optional straight-through routing. Can be left floating or grounded Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 3 TPD4E02B04 SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Electrical fast transient Peak pulse MAX UNIT IEC 61000-4-5 (5/50 ns) 80 A IEC 61000-4-5 Power (tp - 8/20 µs) 17 W IEC 61000-4-5 Current (tp - 8/20 µs) 2 A TA Operating free-air temperature –40 125 °C Tstg Storage temperature –65 155 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings—IEC Specification VALUE V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±12000 IEC 61000-4-2 air-gap discharge ±15000 UNIT V 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX VIO Input pin voltage –3.6 3.6 UNIT V TA Operating free-air temperature –40 125 °C 6.5 Thermal Information TPD4E02B04 THERMAL METRIC (1) DQA (USON) UNIT 10 PINS RθJA Junction-to-ambient thermal resistance 348.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 214.1 °C/W RθJB Junction-to-board thermal resistance 270.7 °C/W ψJT Junction-to-top characterization parameter 81.7 °C/W ψJB Junction-to-board characterization parameter 270.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 TPD4E02B04 www.ti.com SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 6.6 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VRWM Reverse stand-off voltage IIO < 10 nA VBRF Breakdown voltage, any IO pin to GND (1) IIO = 1 mA, TA = 25°C 5.5 VBRR Breakdown voltage, GND to any IO pin (1) IIO = 1 mA, TA = 25°C –5.5 VHOLD Holding voltage (2) IIO = 1 mA 5.8 IPP = 1 A, TLP, from IO to GND 6.6 IPP = 5 A, TLP, from IO to GND 8.8 IPP = 1 A, TLP, from GND to IO 6.6 IPP = 5A, TLP, from GND to IO 8.8 VCLAMP Clamping voltage ILEAK Leakage current, any IO to GND RDYN Dynamic resistance CL (1) (2) UNIT 3.6 V 6.4 7.5 V –6.4 –7.5 V VIO = ±2.5 V V V 10 nA IO to GND 0.47 GND to IO 0.47 Line capacitance VIO = 0 V, f = 1 MHz, IO to GND, TA = 25°C 0.25 0.33 pF Variation of line capacitance Delta of capacitance between any two IO pins, VIO = 0 V, f = 1 MHz, TA = 25°C, GND = 0 V 0.01 0.07 pF Channel to channel capacitance Capacitance from one IO to another, VIO = 0 V, f = 1 MHz, GND = 0 V 0.13 ΔCL CCROSS –3.6 MAX Ω pF VBRF and VBRR are defined as the voltage when 1 mA is applied in the positive-going direction, before the device latches into the snapback state. VHOLD is defined as the voltage when 1 mA is applied in the negative-going direction, after the device has successfully latched into the snapback state. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 5 TPD4E02B04 SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 www.ti.com 30 30 25 25 20 20 Current (A) Current (A) 6.7 Typical Characteristics 15 15 10 10 5 5 0 0 0 3 6 9 12 15 18 21 24 Voltage (V) 0 3 6 9 C001 Figure 1. Positive TLP Curve 15 18 21 24 C002 Figure 2. Negative TLP Curve 3 160 24 Current Power 2.5 12 Voltage (V) 140 20 16 1.5 12 1 8 0.5 4 100 Voltage (V) 2 Power (W) Current (A) 120 80 60 40 20 0 0 -5 0 5 10 15 20 25 Time (Ps) 30 35 40 0 45 -20 -25 0 D001 Figure 3. Surge Curve (tp = 8/20 µs), any IO pin to GND 0.5 0 0.45 Capacitance (pF) -40 Voltage (V) 75 100 125 Time (ns) 150 175 200 225 D001 0.4 -20 -60 -80 -100 0.35 0.3 0.25 0.2 0.15 -120 0.1 -140 0.05 0 25 50 75 100 125 Time (ns) 150 175 200 225 D001 0 -3.6 -3 -2.4 -1.8 -1.2 -0.6 0 0.6 1.2 1.8 2.4 Bias Voltage (V) Figure 5. –8-kV IEC Waveform 6 50 Figure 4. 8-kV IEC Waveform 20 -160 -25 25 Submit Documentation Feedback 3 3.6 D001 Figure 6. Capacitance vs Bias Voltage Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 TPD4E02B04 www.ti.com SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 Typical Characteristics (continued) 0.6 0.5 Bias = -2.5V Bias = 2.5V 0.45 0.5 0.35 Leakage (nA) Capacitance (pF) 0.4 0.3 0.25 0.2 0.15 0.1 0.4 0.3 0.2 0.1 0.05 0 -40 -25 -10 5 20 35 50 65 80 Ambient Temperature (qC) 95 0 -40 110 125 -25 -10 5 D001 Figure 7. Capacitance vs Ambient Temperature 20 35 50 65 Temperature (qC) 80 95 110 125 D001 Figure 8. Leakage Current vs Temperature 1 0.5 0.75 0.4 Capacitance (pF) Current (mA) 0.5 0.25 0 -0.25 0.3 0.2 -0.5 0.1 -0.75 -1 -7 -6 -5 -4 -3 -2 -1 0 1 Voltage (V) 2 3 4 5 6 0 6E+8 7 1E+9 2E+9 3E+9 Frequency (Hz) D001 Figure 9. DC Voltage Sweep I-V Curve 5E+9 7E+9 1E+10 D001 Figure 10. Capacitance vs Frequency 40 5 0 35 -5 30 -10 Voltage (V) Voltage (V) 25 20 15 10 -15 -20 -25 -30 -35 5 -40 0 -5 -10 -45 0 10 20 30 40 50 60 Time (ns) 70 80 90 100 110 -50 -10 0 D001 Figure 11. 8-kV IEC Waveform through 2-m HDMI Cable 10 20 30 40 50 60 Time (ns) 70 80 90 100 110 D001 Figure 12. –8-kV IEC Waveform through 2-m HDMI Cable Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 7 TPD4E02B04 SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 www.ti.com Typical Characteristics (continued) 8 Figure 13. USB3.0 Eye Diagram (Bare Board) Figure 14. USB3.0 Eye Diagram (With TPD4E02B04) Figure 15. USB3.1 Gen 2 Eye Diagram (Bare Board) Figure 16. USB3.1 Gen 2 Eye Diagram (With TPD4E02B04) Figure 17. HDMI2.0 6-Gbps TP2 Eye Diagram (Bare Board) Figure 18. HDMI2.0 6-Gbps TP2 Eye Diagram (With TPD4E02B04) Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 TPD4E02B04 www.ti.com SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 Typical Characteristics (continued) Insertion Loss (dB) 0 -3 -6 + 2E 10 +1 0 1E 1E +9 1E +8 1E +7 1E +6 3E +5 -9 D001 Frequency (Hz) Figure 19. Differential Insertion Loss Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 9 TPD4E02B04 SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 www.ti.com 7 Detailed Description 7.1 Overview The TPD4E02B04 is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-low capacitance makes this device ideal for protecting any super high-speed signal pins. 7.2 Functional Block Diagram IO1 IO2 IO3 IO4 GND 7.3 Feature Description 7.3.1 IEC 61000-4-2 ESD Protection The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air gap. An ESD-surge clamp diverts the current to ground. 7.3.2 IEC 61000-4-4 EFT Protection The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω impedance). An ESD-surge clamp diverts the current to ground. 7.3.3 IEC 61000-4-5 Surge Protection The I/O pins can withstand surge events up to 2 A and 17 W (8/20 µs waveform). An ESD-surge clamp diverts this current to ground. 7.3.4 IO Capacitance The capacitance between each I/O pin to ground is 0.25 pF (typical) and 0.33 pF (maximum). This device supports data rates up to 10 Gbps. 7.3.5 DC Breakdown Voltage The DC breakdown voltage of each I/O pin is a minimum of ±5.5 V. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of ±3.6 V. 7.3.6 Ultra Low Leakage Current The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of ±2.5 V. 7.3.7 Low ESD Clamping Voltage The I/O pins feature an ESD clamp that is capable of clamping the voltage to 8.8 V (IPP = 5 A). 7.3.8 Supports High Speed Interfaces This device is capable of supporting high speed interfaces up to 10 Gbps, because of the extremely low IO capacitance. 10 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 TPD4E02B04 www.ti.com SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 Feature Description (continued) 7.3.9 Industrial Temperature Range This device features an industrial operating range of –40°C to +125°C. 7.3.10 Easy Flow-Through Routing Package The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers flow-through routing, requiring minimal modification to an existing layout. 7.4 Device Functional Modes The TPD4E02B04 is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR. During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network. When the voltages on the protected line fall below the trigger levels of TPD4E02B04 (usually within 10s of nanoseconds) the device reverts to passive. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 11 TPD4E02B04 SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPD4E02B04 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on high-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC. 8.2 Typical Application USB Type-C Connector TPD4E02B04 SSRX1P SSRX1N SSTX1P SSTX1N TPD4E05U06 VBUS SBU2 CC1 DPT DMT TPD4E05U06 DMB DPB SBU1 CC2 VBUS TPD4E02B04 SSRX2N SSRX2P SSTX2N SSTX2P Figure 20. USB 3.1 Gen 2 Type-C ESD Schematic 12 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 TPD4E02B04 www.ti.com SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 Typical Application (continued) Figure 21. USB 3.1 Gen 2 SuperSpeed Layout 8.2.1 Design Requirements For this design example two TPD4E02B04 devices and two TPD4E05U06 devices are being used in a USB 3.1 Gen 2 Type-C application. This provides a complete ESD protection scheme. Given the USB 3.1 Gen 2 Type-C application, the parameters listed in Table 1 are known. Table 1. Design Parameters DESIGN PARAMETER VALUE Signal Range on SuperSpeed+ Lines 0 V to 3.6 V Operating Frequency on SuperSpeed+ Lines 5 GHz Signal Range on CC, SBU, and DP/DM Lines 0 V to 5 V Operating Frequency on CC, SBU, and DP/DM Lines up to 480 MHz Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 13 TPD4E02B04 SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 www.ti.com 8.2.2 Detailed Design Procedure 8.2.2.1 Signal Range The TPD4E02B04 supports signal ranges between –3.6 V and 3.6 V, which supports the SuperSpeed+ pairs on the USB Type-C application. The TPD4E05U06 supports signal ranges between 0 V and 5.5 V, which supports the CC, SBU, and DP/DM lines. 8.2.2.2 Operating Frequency The TPD4E02B04 has a 0.25 pF (typical) capacitance, which supports the USB3.1 Gen 2 data rates of 10 Gbps. The TPD4E05U06 has a 0.5 pF (typical) capacitance, which easily supports the CC, SBU, and DP/DM data rates. 8.2.3 Application Curves Figure 22. USB 3.1 Gen 2 10-Gbps Eye Diagram (Bare Board) 14 Figure 23. USB 3.1 Gen 2 10-Gbps Eye Diagram (With TPD4E02B04) Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 TPD4E02B04 www.ti.com SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 9 Power Supply Recommendations This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended I/O specification (–3.6 V to 3.6 V) to ensure the device functions properly. 10 Layout 10.1 Layout Guidelines • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. SSTX2P SSTX2N SSRX2P SSRX2N TPD4E02B04 CC2 SBU1 DP_bot DM_bot TPD4E05U06 DP_top DM_top CC1 SBU2 TPD4E05U06 SSTX1P SSTX1N SSRX1P TPD4E02B04 SSRX1N 10.2 Layout Examples Legend Top Layer Bottom Layer Pin to GND VIA to VBUS Plane VIA to Other Layer VIA to GND Plane Figure 24. USB Type-C Mid-Mount, Hybrid Connector with One-Sided ESD Layout Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 15 TPD4E02B04 SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 www.ti.com Layout Examples (continued) TPD4E02B04 TMDS_D2+ TMDS_D2- Legend GND Top Layer Bottom Layer Pin to GND VIA to Other Layer VIA to GND Plane TMDS_D1+ TMDS_D1TPD4E02B04 TMDS_D0+ TMDS_D0GND TMDS_CK+ TMDS_CKTPD4E05U06 CEC UTILITY GND DDC_CLK DDC_DAT HOTPLUG_DET TMDS_D2+ GND TMDS_D2TMDS_D1+ GND TMDS_D1TMDS_D0+ GND TMDS_D0TMDS_CK+ GND TMDS_CKCEC UTILITY DDC_CLK DDC_DAT GND 5V_OUT HOTPLUG_DET To GPIO GND 5V_SUPPLY TPD3S014 Figure 25. HDMI2.0 Type-A Transmitter Port Layout 16 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 TPD4E02B04 www.ti.com SLVSD85B – NOVEMBER 2015 – REVISED JULY 2016 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • Reading and Understanding an ESD Protection Datasheet, SLLA305 • ESD Layout Guide, SLVA680 • Picking ESD Diodes for Ultra High-Speed Data Lines, SLVA785 • TPD4E02B04EVM Users Guide, SLVUAH6 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPD4E02B04 17 PACKAGE OPTION ADDENDUM www.ti.com 15-Feb-2018 PACKAGING INFORMATION Orderable Device Status (1) TPD4E02B04DQAR ACTIVE Package Type Package Pins Package Drawing Qty USON DQA 10 3000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -40 to 125 1SG 1SY (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of