Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TPD4S014
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
TPD4S014 USB Charger Port Protection Including ESD Protection for All Lines and
Overvoltage Protection on VBUS
1 Features
3 Description
•
•
•
•
The TPD4S014 is a single-chip solution for USB
charger port protection. This device offers low
capacitance transient voltage suppressor (TVS)
electrostatic discharge (ESD) clamps for the D+, D–,
and standard capacitance for the ID pin. On the VBUS
pin, this device provides overvoltage protection (OVP)
up to 28 V DC. The overvoltage lockout feature
ensures that if there is a fault condition at the VBUS
line, the TPD4S014 is able to isolate the VBUS line to
protect the internal circuitry from damage. There is a
17-ms turn-on delay after VBUS rises above the
undervoltage lockout (UVLO) threshold in order to let
the voltage stabilize before turning the nFET on. This
function acts as a de-glitch and prevents unnecessary
switching if there is any ringing on the line during
connection.
1
•
•
•
•
•
•
Input Voltage Protection at VBUS up to 28 V
Low Ron nFET Switch
Supports > 2 A Charging Current
ESD Performance D+/D–/ID/VBUS Pins:
– ±15-kV Contact Discharge (IEC 61000-4-2)
– ±15-kV Air Gap Discharge (IEC 61000-4-2)
Overvoltage and Undervoltage Lockout Features
Low Capacitance TVS ESD Clamp for USB2.0
High Speed Data Rate
Internal 17 ms Startup Delay
Integrated Input Enable and Status Output Signal
Thermal Shutdown Feature
Space Saving SON Package (2 mm × 2 mm)
Device Information(1)
2 Applications
•
•
•
•
PART NUMBER
Cell Phones
eBook
Portable Media Players
Digital Camera
TPD4S014
PACKAGE
WSON (10)
BODY SIZE (NOM)
2.00 mm x 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
VLOGIC
10 KΩ
TPD4S014
VBUS
10 µF
D-
ACK
EN
To Processor
From Processor
VBUSOUT
D+
ID
Battery
Charger
10 µF
USB Port
VBUS
DD+
USB
Transceiver
ID
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD4S014
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics, EN, ACK, D+, D–, ID Pins
................................................................................... 6
Electrical Characteristics OVP Circuits ..................... 7
Supply Current Consumption.................................... 7
Thermal Shutdown Feature ...................................... 7
Typical Characteristics .............................................. 8
Detailed Description ............................................ 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ................................................ 13
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
7.1 Overview ................................................................. 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (September 2015) to Revision G
•
Added a frequency test condition to capacitance in the Electrical Characteristics table. ..................................................... 6
Changes from Revision E (June 2014) to Revision F
•
Page
Page
Corrected VDROP on nFET under load................................................................................................................................... 10
Changes from Revision D (April 2014) to Revision E
Page
•
Updated Recommended Operating Conditions table. ........................................................................................................... 5
•
Changed terminal name to ILEAK from IL ................................................................................................................................. 6
•
Updated Electrical Characteristics OVP Circuits table. .......................................................................................................... 7
•
Changed tON MAX value from 18 ms to 22ms ....................................................................................................................... 7
•
Changed tOFF 8 µs value from MAX to TYP............................................................................................................................ 7
•
Changed td(OVP) 11 µs value from MAX to TYP. ..................................................................................................................... 7
•
Changed tREC MAX value from 9 ms to 10.5 ms. .................................................................................................................. 7
•
Updated Application and Implementation section. .............................................................................................................. 13
Changes from Revision C (December 2011) to Revision D
Page
•
Added ESD Ratings table....................................................................................................................................................... 5
•
Added Recommended Operating Conditions table. ............................................................................................................... 5
•
Added Thermal Information table. ......................................................................................................................................... 6
•
Updated Electrical Characteristics OVP Circuits table. .......................................................................................................... 7
2
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
TPD4S014
www.ti.com
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
Changes from Revision B (October 2011) to Revision C
Page
•
Made changes to the datasheet to tighten the parameters, VOP+ changed from 5.55 V to 5.9 V........................................ 1
•
Updated Description. .............................................................................................................................................................. 1
Changes from Revision A (June 2011) to Revision B
Page
•
Changed name of VCC to VBUSOUT throughout the entire document................................................................................... 10
•
Deleted row from Device Operation table. ........................................................................................................................... 12
•
Added Eye Diagrams to Typical Characteristics section...................................................................................................... 14
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
3
TPD4S014
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
www.ti.com
5 Pin Configuration and Functions
DSQ Package
10-Pin WSON
Top Side/See-Through View
VBUSOUT
1
10 VBUS
VBUSOUT
VBUS
EN
GND
ACK
ID
D+
5
6
D-
Pin Functions
PIN
NAME
NO.
VBUSOUT
TYPE
DESCRIPTION
1, 2
Power Output
EN
3
IO
ACK
4
I
ID
5
IO
ESD-protected line
D–
6
IO
ESD-protected line
D+
7
IO
ESD-protected line
GND
8
Ground
VBUS
9, 10
USB Input Power
Central PAD
Heat Sink
Central PAD
4
Connect to PCB internal PCB plane
Enable Active-Low Input. Drive EN low to enable the switch. Drive EN high to disable the switch.
Open-Drain Adapter-Voltage Indicator Output. ACK is driven low after the VIN voltage is stable
between UVLO and OVLO for 17 ms (typ). Connect a pullup resistor from ACK to the logic I/O
voltage of the host system.
Ground
Connector Side of VBUS
Electrically disconnected. Use as heat sink. Connect to GND plane via large PCB PAD
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
TPD4S014
www.ti.com
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
Maximum junction temperature
–40
150
°C
Max Voltage on VBUS
–0.5
30
V
Continuous current through nFET
2.6
A
50
mA
Max Current through D+, D–, ID, VBUS ESD clamps
50
mA
Max voltage on EN, ACK, D+, D-, ID, VBUSOUT
6
V
150
°C
Continuous current through ACK
–50
Storage temperature, Tstg
(1)
(2)
–65
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
IEC 61000-4-2 Contact Discharge
D+, D–, ID, VBUS pins
±1500
IEC 61000-4-2 Air-gap Discharge
D+, D–, ID, VBUS pins
±1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TA
Operating free-air temperature
VI
Input voltage
NOM
MAX
–40
85
VBUSOUT
–0.1
5.5
VBUS
–0.1
5.5
EN
–0.1
5.5
ACK
–0.1
5.5
D+, D-, ID,
–0.1
5.5
UNIT
°C
V
IVBUS
VBUS continuous current (1)
VBUSOUT
CVBUS
Capacitance on VBUS
VBUS Pin
10
CVBUSOUT
Capacitance on VBUSOUT
VBUSOUT Pin
10
µF
RACK
Pullup resistor on ACK
ACK Pin
10
kΩ
(1)
2.0
A
µF
IVBUS Max value is dependent on ambient temperature. See Thermal Shutdown section.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
5
TPD4S014
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
www.ti.com
6.4 Thermal Information
TPD4S014
THERMAL METRIC (1)
DSQ (WSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
70.3
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
46.3
°C/W
RθJB
Junction-to-board thermal resistance
33.8
°C/W
ψJT
Junction-to-top characterization parameter
2.9
°C/W
ψJB
Junction-to-board characterization parameter
33.5
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
16.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics, EN, ACK, D+, D–, ID Pins
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIH
High-level input voltage EN
Load current = 50 µA
VIL
Low-level input voltage EN
Load current = 50 µA
ILEAK
Input Leakage Current EN, D+, D–, ID
VOL
Low-level output voltage ACK
VD
Diode forward Voltage D+, D–, ID pins; lower clamp diode
ΔCIO
Differential Capacitance between the D+, D– lines
CIO
Capacitance to GND for the D+, D– lines
CIO-ID
Capacitance to GND for the ID line
VR
Reverse stand-off voltage of D+, D- and ID pins
VBR
VBR
VBUS
RDYN
6
MIN
TYP MAX UNIT
1
V
0.5
V
VIO = 3.3 V
1
µA
IOL = 2 mA
0.1
V
IO = 8 mA
0.95
V
ƒ = 1 MHz
Breakdown voltage D+, D–, ID pins
IBR = 1 mA
6
Breakdown voltage on VBUS
IBR = 1 mA
28
Dynamic on resistance D+, D–, ID clamps
II = 1 A
Submit Documentation Feedback
0.03
pF
1.6
pF
19
pF
5
V
V
V
1
Ω
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
TPD4S014
www.ti.com
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
6.6 Electrical Characteristics OVP Circuits
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT UNDERVOLTAGE LOCKOUT
VUVLO+
Under-voltage lock-out, input power
detected threshold rising
VBUS increasing from 0 V to 5 V, No load on OUT
pin
2.65
2.8
3
V
VUVLO–
Under-voltage lock-out, input power
detected threshold falling
VBUS decreasing from 5 V to 0 V, No load on OUT
pin
2.25
2.44
2.7
V
VHYS-UVLO
Hysteresis on UVLO
Δ of VUVLO+ and VUVLO–
150
360
550
mV
151
200
mΩ
17.4
22
ms
INPUT TO OUTPUT CHARACTERISTICS
RDS_VBUSSWITCH
VBUS switch resistance
VBUS = 5 V, IOUT = 500 mA
tON
Turn-ON time
VBUS increasing from 2.8 V to 4.75 V, EN = 0 V,
RL = 36 Ω, CL = 10 uF
tOFF
Turn-OFF time
VBUS decreasing from 2.44 V to 0.5 V, EN = 0V,
RL = 36 Ω, CL = 10 uF
16
8
µs
INPUT OVERVOLTAGE PROTECTION (OVP)
VOVP+
Input over –voltage
protection threshold rising
VBUS
VBUS increasing from 5 V to 7 V, No Load
5.9
6.15
6.45
V
VOVP-
Input over –voltage
protection threshold falling
VBUS
VBUS decreasing from 7 V to 5 V, No Load
5.75
5.98
6.24
V
VHYS-OVP
Hysteresis on OVP
VBUS
Δ of VOVP+ and VOVP–
25
100
275
mV
11
8
td(OVP)
Over voltage delay
VBUS
RL = 36 Ω, CL = 10 µF; VBUS increasing from 5 V
to 7 V
tREC
Recovery time from input
over voltage condition
VBUS
RL = 36 Ω, CL = 10 µF; VBUS decreasing from 7 V
to 5 V
µs
10.5
ms
6.7 Supply Current Consumption
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVBUS
VBUS Operating Current
Consumption
No load on VBUS_OUT pin, VBUS = 5 V,
EN = 0 V
147.6
160
µA
IVBUS_OFF
VBUS Operating Current
Consumption
No load on VBUS_OUT pin, VBUS = 5 V,
EN = 5 V
111.8
120
µA
TYP
MAX
UNIT
6.8 Thermal Shutdown Feature
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TSHDN
Thermal Shutdown
TSHDN-HYS
Thermal-Shutdown Hysteresis
TEST CONDITIONS
MIN
144
°C
23
°C
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
7
TPD4S014
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
www.ti.com
6.9 Typical Characteristics
Figure 1. IEC61000-4-2 -8-kV Contact Waveform
Figure 2. IEC61000-4-2 +8-kV Contact Waveform
Figure 3. Capacitance Variation With Voltage
Figure 4. Variation of On Resistance with Ambient
Temperature
Figure 5. Max Pulse Current Through Switch vs Pulse
Duration
8
Figure 6. UVLO Threshold Variation With Temperature
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
TPD4S014
www.ti.com
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
Typical Characteristics (continued)
Figure 7. OVP Threshold Variation With Temperature
Figure 8. Start Up Inrush Current Characteristics
Figure 9. Device Turn on Characteristics
Figure 10. Device Turn OFF Characteristics (Undervoltage)
.
Figure 11. Device Turn OFF Characteristics (Overvoltage)
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
9
TPD4S014
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
www.ti.com
7 Detailed Description
7.1 Overview
The TPD4S014 provides a single-chip protection solution for USB charger interfaces. The VBUS line is tolerant up
to 28 V DC. A Low RON nFET switch is used to disconnect the downstream circuits in case of a fault condition.
At power-up, when the voltage on VBUS is rising, the switch will close 17 ms after the input crosses the under
voltage threshold, thereby making power available to the downstream circuits. The TPD4S014 also has an ACK
output, which de-asserts to alert the system a fault has occurred. The TPD4S014 offers 4 channel ESD clamps
for D+, D-, ID, and VBUS pins that provide IEC61000-4-2 level 4 ESD protection. This eliminates the need for
external TVS clamp circuits in the application.
7.2 Functional Block Diagram
VBUS
VBUSOUT
Internal
Band Gap
Reference
OVLO
Control Logic
+
Charge Pump
ACK
UVLO
EN
GND
D+
D-
ID
7.3 Feature Description
7.3.1 Input Voltage Protection at VBUS up to 28 V DC
When the input voltage rises above VOVP, or drops below the VUVLO, the internal VBUS switch is turned off,
removing power to the application. The ACK signal is de-asserted when a fault condition is detected. If the fault
was an over voltage event, the VBUS nFET switch turns on 8 ms (tREC) after the input voltage returns below
VOVP – VHYS_OVP and remains above VUVLO. If the fault was an under voltage event, the switch turns on 17 ms
after the voltage returns above VUVLO+ (similar to start up). When the switch turns on, the ACK is asserted once
again.
7.3.2 Low RON nFET Switch
The nFET switch has a total on resistance (RON) of 151 mΩ. This equates to a voltage drop of 302 mV when
charging at the maximum 2.0 A current level. Such low RON helps provide maximum potential to the system as
provided by an external charger.
7.3.3 ESD Performance D+/D–/ID/VBUS Pins
The D+, D–, ID, and VBUS pins can withstand ESD events up to ±15-kV contact and air-gap. An ESD clamp
diverts the current to ground.
10
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
TPD4S014
www.ti.com
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
Feature Description (continued)
7.3.4 Overvoltage and Undervoltage Lockout Features
The over voltage and under voltage lockout feature ensures that if there is a fault condition at the VBUS line, the
TPD4S014 is able to isolate the VBUS line and protect the internal circuitry from damage. Due to the body diode
of the nFET switch, if there is a short to ground on VBUS the system is expected to limit the current to VBUSOUT.
7.3.5 Capacitance TVS ESD Clamp for USB2.0 Hi-Speed Data Rate
The D+/D– ESD protection pins have low capacitance so there is no significant impact to the signal integrity of
the USB 2.0 Hi-Speed data rate.
7.3.6 Start-up Delay
Upon startup, TPD4S014 has a built in startup delay. An internal oscillator controls a charge pump to control the
turn-on delay (tON) of the internal nFET switch. The internal oscillator controls the timers that enable the turn-on
of the charge pump and sets the state of the open-drain ACK output. If VBUS < VUVLO or if VBUS > VOVLO, the
internal oscillator remains off, thus disabling the charge pump. At any time, if VBUS drops below VUVLO or rises
above VOVLO, ACK is released and the nFET switch is disabled.
7.3.7 OVP Glitch Immunity
A 17 ms deglitch time has been introduced into the turn on sequence to ensure that the input supply has
stabilized before turning the nFET switch ON. Noise on the VBUS line could turn ON the nFET switch when the
fault condition is still active. To avoid this, OVP glitch immunity allows noise on the VBUS line to be rejected. Such
a glitch protection circuitry is also introduced in the turn off sequence in order to prevent the switch from turning
off for voltage transients. The glitch protection circuitry integrates the glitch over time, allowing the OVP circuitry
to trigger faster for larger voltage excursions above the OVP threshold and slower for shorter excursions.
7.3.8 Integrated Input Enable and Status Output Signal
External control of the nFET switch is provided by an active low EN pin. An ACK pin provides output logic to
acknowledge VBUS is between UVLO and OVP by asserting low.
7.3.9 Thermal Shutdown
When the device is ON, current flowing through the device will cause the device to heat up. Overheating can
lead to permanent damage to the device. To prevent this, an over temperature protection has been designed into
the device. Whenever the junction temperature exceeds 145ºC, the switch will turn off, thereby limiting the
temperature. The ACK signal will be asserted for an over temperature event. Once the device cools down to
below 120ºC the ACK signal will be de-asserted, and the switch will turn on if the EN is active and the VBUS
voltage is within the UVLO and OVP thresholds. While the over temperature protection in the device will not kickin unless the die temperature reaches 145ºC, it is generally recommended that care is taken to keep the junction
temperature below 125 ºC. Operation of the device above 125 ºC for extended periods of time can affect the
long-term reliability of the part.
The junction temperature of the device can be calculated using below formula:
Tj = Ta + PD qJA
where
•
•
•
•
TJ = Junction temperature
Ta = Ambient temperature
θJA = Thermal resistance
PD = Power dissipated in device
(1)
2
PD = I Ron
where
•
•
I = Current through device
RON = Max on resistance of device
(2)
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
11
TPD4S014
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
www.ti.com
Feature Description (continued)
Example
At 2-A continuous current power dissipation is given by:
PD = 22 ´ 0.2 = 0.8W
If the ambient temperature is about 60°C the junction temperature will be:
Tj = 60 + (0.8 ´ 70.3 ) = 116.24
This implies that, at an ambient temperature of 60ºC, TPD4S014 can pass a continuous 2 A without sustaining
damage. Conversely, the above calculation can also be used to calculate the total continuous current the
TPD4S014 can handle at any given temperature.
7.4 Device Functional Modes
Table 1 is the function table for TPD4S014.
Table 1. Function Table
OTP
UVLO
OVLO
EN
SW
ACK
X
H
X
X
OFF
H
X
X
H
X
OFF
H
L
L
L
H
OFF
L
L
L
L
L
ON
L
H
X
X
X
OFF
H
OTP = Over temperature protection circuit active
UVLO = Under voltage lock-out circuit active
OVLO = Over voltage lock-out circuit active
SW = Load switch
CP = Charge pump
X = Don’t Care
H = True
L = False
12
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
TPD4S014
www.ti.com
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD4S014 is a single-chip solution for USB charger port protection. This device offers low capacitance TVS
type ESD clamps for the D+, D–, and standard capacitance for the ID pin. On the VBUS pin, this device can
handle over voltage protection up to 28 V. The over voltage lockout feature ensures that if there is a fault
condition at the VBUS line TPD4S014 is able to isolate the VBUS line and protect the internal circuitry from
damage. In order to let the voltage stabilize before closing the switch there is a 17 ms turn on delay after VBUS
crosses the UVLO threshold. This function acts as a de-glitch which prevents unnecessary switching if there is
any ringing on the line during connection. Due to the body diode of the nFET switch, if there is a short to ground
on VBUS the system is expected to limit the current to VBUSOUT.
8.2 Typical Applications
8.2.1 For Non-OTG USB Systems
VLOGIC
10 KΩ
TPD4S014
VBUS
10 µF
To Processor
From Processor
ACK
EN
VBUSOUT
D+
D-
ID
Battery
Charger
10 µF
USB Port
VBUS
D-
USB
Transceiver
D+
ID
Figure 12. Non-OTG Schematic
8.2.1.1 Design Requirements
Table 2 shows the design parameters.
Table 2. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Signal range on VBUS
3.3 V – 5.9 V
Signal range on VBUSOUT
3.9 V – 5.9 V
Signal range on D+/D– and ID
0V–5V
Drive EN low (enabled)
0 V – 0.5 V
Drive EN high (disabled)
1V–6V
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
13
TPD4S014
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
www.ti.com
8.2.1.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon. The designer needs to know the
following:
• VBUS voltage range
• Processor logic levels VOH, VOL for EN and VIH, VIL for ACK pins
8.2.1.3 Application Curves
Figure 13. Eye Diagram With No EVM and No IC, Full
USB2.0 Speed at 480 Mbps
Figure 14. Eye Diagram With EVM, No IC, Full USB2.0
Speed at 480 Mbps
Figure 15. Eye Diagram With EVM and IC, Full USB2.0 Speed at 480 Mbps
14
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
TPD4S014
www.ti.com
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
8.2.2 For OTG USB Systems
VLOGIC
To OTG power
supply (5 V)
Current
Limit
Switch
10 KΩ
TPD4S014
VBUS
10 µF
To Processor
From Processor
ACK
EN
VBUSOUT
D+
D-
ID
Battery
Charger
10 µF
USB Port
VBUS
D-
USB
Transceiver
D+
ID
Figure 16. OTG Schematic
8.2.2.1 Design Requirements
Table 3 shows the design parameters.
Table 3. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Signal range on VBUS
3.3 V – 5.9 V
Signal range on VBUSOUT
3.9 V – 5.9 V
Signal range on D+/D– and ID
0V–5V
Drive EN low (enabled)
0 V – 0.5 V
Drive EN high (disabled)
1V–6V
8.2.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon. The designer needs to know the
following:
• VBUS voltage range
• Processor logic levels VOH, VOL for EN and VIH, VIL for ACK pins
• OTG power supply output voltage range
8.2.2.3 Application Curves
Refer to Application Curves in the previous section.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
15
TPD4S014
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
www.ti.com
9 Power Supply Recommendations
TPD4S014 Is designed to receive power from a USB 3.0 (or lower) VBUS source. It can operate normally (nFET
ON) between 3.0 V and 5.9 V. Thus, the power supply (with a ripple of VRIPPLE) requirement for TPD4S014 to be
able to switch the nFET ON is between 3.0 V + VRIPPLE and 5.9 V – VRIPPLE.
10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
– Keep traces between the connector and TPD4S014 on the same layer as TPD4S014.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
When designing layout for TPD4S014, note that VBUSOUT and VBUS pins allow for extra wide traces for good
power delivery. In the example shown, these pins are routed with 25 mil (0.64 mm) wide traces. Place the
VBUSOUT and VBUS capacitors as close to the device pins as possible. Pull ACK up to the Processor logic level
high with a resistor. Use external and internal ground planes and stitch them together with VIAs as close to the
GND pins of TPD4S014 as possible. This allows for a low impedance path to ground so that the device can
properly dissipate any ESD events.
16
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
TPD4S014
www.ti.com
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
10.2 Layout Example
Legend
VIA to Power Ground Plane
Processor
Signal VIA
VLOGIC
ACK
Trace on alternate layer
EN
VLOGIC
Power Ground
10 KΩ
USB SYS
VBUS
USB PORT
VBUS
VBUSOUT
1
VBUS
DD+
DD+
ID
ID
Figure 17. Layout Recommendation
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
17
TPD4S014
SLVSAU0G – MAY 2011 – REVISED DECEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPD4S014
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD4S014DSQR
ACTIVE
WSON
DSQ
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ZTE
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
