TPD3S014-Q1
SLVSDG5C – MARCH 2016 – REVISED AUGUST 2020
TPD3S014-Q1 Current Limit Switch and D+/D– ESD Protection for Automotive USB
Host Ports
1 Features
3 Description
•
The TPD3S014-Q1 is an integrated device that
features a current-limited load switch and a twochannel transient voltage suppressor (TVS) based
electrostatic discharge (ESD) protection diode array
for USB interfaces.
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified (Grade 2)
– Ambient Temperature Range: –40°C to +105°C
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Continuous Current Rating of 0.5 A
Fixed, Constant Current Limits of 0.85 A (typical)
Fast Overcurrent Response – 2 μs
Integrated Output Discharge
Reverse Current Blocking
Short-Circuit Protection
Over Temperature Protection With Auto-Restart
Built-In Soft Start
IEC 61000-4-2 Level 4 ESD Protection (External
Pins)
– ±12-kV Contact Discharge (IEC 61000-4-2)
– ±15-kV Air Gap Discharge (IEC 61000-4-2)
ISO 10605 330-pF, 330-Ω ESD Protection
(External Pins)
– ±8-kV Contact Discharge
– ±15-kV Air Gap Discharge
6-Pin SOT-23 Package (2.90 mm × 1.60 mm)
The TPD3S014-Q1 device is intended for applications
such as USB where heavy capacitive loads and shortcircuits are likely to be encountered; the TPD3S014Q1 provides short-circuit protection and overcurrent
protection. The TPD3S014-Q1 limits the output
current to a safe level by operating in constant current
mode when the output load exceeds the current
limit threshold. The fast overload response eases the
burden on the main 5 V power supply by quickly
regulating the power when the output is shorted. The
rise and fall times for the current limit switch are
controlled to minimize current surges when turning the
device on and off.
The TPD3S014-Q1 allows 0.5 A of continuous
current. The TVS diode array is rated to dissipate
ESD strikes above the maximum level specified in the
IEC 61000-4-2 international standard.
2 Applications
•
•
The high level of integration, combined with its
easy-to-route DBV package, allows this device to
provide great circuit protection for USB interfaces in
applications like head units, USB hubs, and media
interfaces.
End Equipment:
– Head Units
– Rear Seat Entertainment
– Telematics
– USB Hubs
– Navigation Module
Interfaces:
– USB 2.0
– USB 3.0
Device Information(1)
PART NUMBER
TPD3S014-Q1
(1)
PACKAGE
SOT-23 (6)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
From Processor
5 V Source
TPD3S014±Q1
150 F
OUT
EN
IN
USB Port
D1
D2
0.1 F
GND
VBUS
DD+
GND
USB Transceiver
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD3S014-Q1
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SLVSDG5C – MARCH 2016 – REVISED AUGUST 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings—AEC Specification............................... 4
6.3 ESD Ratings—IEC Specification................................ 4
6.4 ESD Ratings—ISO Specification................................ 4
6.5 Recommended Operating Conditions.........................4
6.6 Thermal Information....................................................5
6.7 Electrical Characteristics: TJ = TA = 25°C...................5
6.8 Electrical Characteristics: –40°C ≤ TA ≤ 105°C...........6
6.9 Typical Characteristics................................................ 7
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................12
8.1 Overview................................................................... 12
8.2 Functional Block Diagram......................................... 12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................15
9 Application and Implementation.................................. 16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 16
10 Power Supply Recommendations..............................19
11 Layout........................................................................... 19
11.1 Layout Guidelines................................................... 19
11.2 Layout Example...................................................... 19
11.3 Power Dissipation and Junction Temperature.........20
12 Device and Documentation Support..........................22
12.1 Documentation Support.......................................... 22
12.2 Support Resources................................................. 22
12.3 Trademarks............................................................. 22
12.4 Electrostatic Discharge Caution..............................22
12.5 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2016) to Revision C (August 2020)
Page
• Added functional safety link to the Features section.......................................................................................... 1
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
Changes from Revision A (April 2016) to Revision B (April 2016)
Page
• Made changes to the Electrical Characteristics: –40°C ≤ TA ≤ 105°C table. Changed TA from 125°C to 105°C
............................................................................................................................................................................1
• Changed Temperature from 125°C to 105°C in Power Dissipation and Junction Temperature section............. 1
Changes from Revision * (March 2016) to Revision A (April 2016)
Page
• Changed device status from Product Preview to Production Data .................................................................... 1
2
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5 Pin Configuration and Functions
EN
1
6
D2
GND
2
5
D1
IN
3
4
OUT
Figure 5-1. DBV Package 6-Pin SOT-23 Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
D1
5
D2
6
EN
1
I
GND
2
—
IN
3
I
Input voltage and power-switch drain; Connect a 0.1-µF or greater ceramic capacitor
from IN to GND close to the IC
OUT
4
O
Power-switch output, connect to load
I/O
USB data+ or USB data–
Enable input, logic high turns on power switch
Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Input voltage(3)
MIN
MAX
VIN
–0.3
6
VOUT
–0.3
6
EN
–0.3
6
D1
–0.3
6
D2
–0.3
6
Voltage from VIN to VOUT
–6
Junction temperature
TJ
Storage temperature
Tstg
(1)
(2)
(3)
UNIT
V
6
V
150
°C
Internally limited
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Voltages are with respect to GND unless otherwise noted.
See the Input and Output Capacitance section.
6.2 ESD Ratings—AEC Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC
Q100-002(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
IEC 61000-4-2, VOUT, Dx pins
Contact discharge(1)
±12000
Air-gap discharge(1)
±15000
UNIT
V
VOUT was tested on a PCB with input and output bypassing capacitors of 0.1 µF and 120 µF, respectively.
6.4 ESD Ratings—ISO Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
ISO 10605 330 pF, 330 Ω,
VOUT, Dx pins
discharge(1)
±8000
Air-gap discharge(1)
±15000
Contact
UNIT
V
VOUT was tested on a PCB with input and output bypassing capacitors of 0.1 µF and 120 µF, respectively.
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
4.5
5.5
V
Input voltage, EN
0
5.5
V
VIH
High-level Input voltage, EN
2
VIL
Low-level Input voltage, EN
CIN
Input decoupling capacitance, IN to GND
IOUT (1)
Continuous output current (TPD3S014-Q1)
TJ
Operating junction temperature
VIN
Input voltage
VEN
(1)
4
V
0.7
0.1
–40
UNIT
V
µF
0.5
A
125
°C
Package and current ratings may require an ambient temperature derating of 85°C
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6.6 Thermal Information
TPD3S014-Q1
THERMAL
METRIC(1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
185.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
124.7
°C/W
RθJB
Junction-to-board thermal resistance
32.0
°C/W
ψJT
Junction-to-top characterization parameter
23.7
°C/W
ψJB
Junction-to-board characterization parameter
31.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
RθJA (Custom)
See the Power Dissipation and Junction Temperature section
120.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.7 Electrical Characteristics: TJ = TA = 25°C
VIN = 5 V, VEN = VIN, IOUT = 0 A (unless otherwise noted). Parameters over a wider operational range are shown in Electrical
Characteristics: –40°C ≤ TA ≤ 105°C table.
TEST CONDITIONS(1)
PARAMETER
MIN
TYP
MAX
97
120
97
140
0.85
1.01
0.02
1
UNIT
POWER SWITCH
RDS(on)
Input – Output resistance
–40°C ≤ (TJ, TA) ≤ +85°C
mΩ
CURRENT LIMIT
IOS (2)
Current limit, see Figure 8-3
0.67
A
SUPPLY CURRENT
ISD
Supply current, switch disabled
ISE
Supply current, switch enabled
IREV
Reverse leakage current
IOUT = 0 A
–40°C ≤ (TJ, TA) ≤ +85°C, VIN = 5.5 V, IOUT = 0 A
2
IOUT = 0 A
66
–40°C ≤ (TJ, TA) ≤ +85°C, VIN = 5.5 V, IOUT = 0 A
74
85
VOUT = 5 V, VIN = 0 V, Measure IVOUT
0.2
–40°C ≤ (TJ, TA) ≤ +85°C, VOUT = 5 V, VIN = 0 V,
Measure IVOUT
µA
µA
1
5
µA
OUTPUT DISCHARGE
RPD
Output pull-down resistance(3)
VIN = VOUT = 5 V, disabled
400
456
600
Ω
ESD PROTECTION
ΔCIO
Differential capacitance between
the D1, D2 lines
ƒ = 1 MHz, VIO = 2.5 V
0.02
pF
CIO
(D1, D2 to GND)
ƒ = 1 MHz, VIO = 2.5 V
1.4
pF
RDYN
Dynamic on-resistance D1, D2
IEC clamps(4)
Dx to GND
0.2
Ω
GND to Dx
0.2
Ω
(1)
(2)
(3)
(4)
Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
See the Current Limit for explanation of this parameter.
These Parameters are provided for reference only, and do not constitute a part of TI’s published device specifications for purposes of
TI’s product warranty.
RDYN was extracted using the least squares first of the TLP characteristics between I = 20 A and I = 30 A.
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6.8 Electrical Characteristics: –40°C ≤ TA ≤ 105°C
4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, IOUT = 0 A, typical values are at 5 V and 25°C (unless otherwise noted)
TEST CONDITIONS(1)
PARAMETER
MIN
TYP
MAX
UNIT
97
164
mΩ
1.45
2
V
POWER SWITCH
RDS(on)
Input – output resistance
ENABLE INPUT (EN)
Threshold
Input rising
1
Leakage current
VEN = 0 V
–1
0
1
µA
tON
Turnon time
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↑
See Figure 8-2
1
1.6
2.2
ms
tOFF
Turnoff time
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↓
See Figure 8-2
1.7
2.1
2.7
ms
tR
Rise time, output
CL = 1 µF, RL = 100 Ω, VIN = 5 V, See Figure 8-1
0.4
0.64
0.9
ms
tF
Fall time, output
CL = 1 µF, RL = 100 Ω, VIN = 5 V, See Figure 8-1
0.25
0.4
0.8
ms
0.65
0.85
1.05
A
Hysteresis
0.13
V
CURRENT LIMIT
IOS (2)
Current limit, see Figure 8-3
Short-circuit response time(2)
tIOS
VIN = 5 V (see Figure 8-3)
One Half full load → RSHORT = 50 mΩ Measure
from application to when current falls below
120% of final value
2
µs
SUPPLY CURRENT
ISD
Supply current, switch disabled
IOUT = 0 A
0.02
10
µA
ISE
Supply current, switch enabled
IREV
Reverse leakage current
IOUT = 0 A
66
94
µA
VOUT = 5.5 V, VIN = 0 V, Measure IVOUT
0.2
20
µA
3.77
4
V
UNDERVOLTAGE LOCKOUT
VUVLO
Rising threshold
VIN↑
Hysteresis
VIN↓
3.5
0.14
V
OUTPUT DISCHARGE
RPD
Output pull-down resistance
VIN = 4 V, VOUT = 5 V, Disabled
350
545
1200
VIN = 5 V, VOUT = 5 V, Disabled
300
456
800
In current limit
135
Not in current limit
155
Ω
THERMAL SHUTDOWN
TSHDN
Rising threshold (TJ)
Hysteresis(3)
°C
20
°C
ESD PROTECTION
II
Input leakage current (D1, D2)
VI = 3.3 V
VD
Diode forward voltage (D1, D2);
Lower clamp diode
IO = 8 mA
VBR
Breakdown voltage (D1, D2)
IBR = 1 mA
(1)
(2)
(3)
6
0.02
6
1
µA
0.95
V
V
Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature.
See the Current Limit section for explanation of this parameter.
These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
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-2
0
2
4
6
Time (ms)
8
10
12
14
-4
-5
0
5
10
15
Time (ms)
20
25
Amplitude (V)
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-4
2
4
6
Time (ms)
8
10
12
D001
56
IN
52
OUT
IOUT 48
CIN = 300 PF, COUT = 150 PF
-2
0
2
4
D001
Figure 6-3. Pulsed Output Short
6
8
Time (µs)
10
12
14
16
44
40
36
32
28
24
20
16
12
8
4
0
-4
18
D001
Figure 6-4. Short Applied
7
14
6
12
5
10
IOUT sinking (mA)
IREV (PA)
0
Figure 6-2. Enable into Short
1.2
IN
1.12
OUT
1.04
EN
IOUT 0.96
0.88
0.8
0.72
0.64
0.56
0.48
0.4
0.32
0.24
0.16
0.08
0
30
35
Current (A)
Amplitude (V)
Figure 6-1. Turn ON into 10 Ω
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-10
-2
D001
1.5
IN
1.4
OUT 1.3
EN
1.2
IOUT
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
14 16
Current (A)
-4
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
16
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-6
Current (A)
1.5
IN
1.4
OUT
1.3
EN
IOUT 1.2
Amplitude (V)
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-6
Current (A)
Amplitude (V)
6.9 Typical Characteristics
4
3
2
1
-40°C
25°C
85°C
125°C
VIN = 5 V
8
6
4
2
0
-1
-40
0
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
140
D007
Figure 6-5. Reverse Leakage Current (IREV) vs
Temperature
-2
0
0.5
1
1.5
2
2.5
3
3.5
Output Voltage (V)
4
4.5
5
D001
Figure 6-6. Output Discharge Current vs Output
Voltage
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1.4
0.5
1.3
0.475
1.2
0.45
0.425
1
tF (ms)
IOS (A)
1.1
0.9
0.4
0.8
0.375
0.7
0.35
0.6
0.325
0.5
0.4
-40
-20
0
20
40
60
80
Junction Temprature (qC)
100
120
0.3
-40
140
D026
Figure 6-7. Short Circuit Current (IOS) vs
Temperature
-20
0
20
40
60
80
Junction Temprature (qC)
100
120
140
D027
Figure 6-8. Output Fall Time (tF) vs Temperature
0.8
2.8
All Unit Types
2.4
0.75
2
1.6
ISD (PA)
tR (ms)
0.7
0.65
0.6
1.2
0.8
0.4
0
0.55
-0.4
0.5
-40
-20
0
20
40
60
80
Junction Temprature (°C)
100
120
140
20
40
60
80
Junction Temprature (qC)
100
120
140
D001
Figure 6-10. Disabled Supply Current (ISD) vs
Temperature
All Unit Types
-40 (qC)
25 (qC)
85 (qC)
125 (qC)
3.5
3
All Unit Types, V IN = 0 V
2.5
IREV (PA)
ISD (PA)
0
4
-40 (°C)
25 (°C)
85 (°C)
125 (°C)
2
1.5
1
0.5
0
-0.5
4
4.2
4.4
4.6
4.8
5
Input Voltage (V)
5.2
5.4
5.6
4
4.2
D001
Figure 6-11. Disabled Supply Current (ISD) vs Input
Voltage
8
-20
D028
Figure 6-9. Output Rise Time (tR) vs Temperature
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.8
-40
4.4
4.6
4.8
5
Output Voltage (V)
5.2
5.4
5.6
D001
Figure 6-12. Reverse Leakage Current (IREV) vs
Output Voltage
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72
85
All Unit Types, VIN = 5.5 V
68
75
66
70
64
60
60
55
58
50
45
-20
0
20
40
60
80
Junction Temprature (qC)
100
120
140
35
32.5
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
5
2.5
0
2
4
6
8
10
12
Voltage (V)
14
16
18
4.4
4.6
4.8
5
Input Voltage (V)
5.2
5.4
5.6
D001
35
32.5
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
5
2.5
0
20
0
0.8
1.6
2.4
D001
Figure 6-15. D1/D2 Positive TLP Curve
3.2
4
4.8
Voltage (V)
5.6
6.4
7.2
8
D001
Figure 6-16. D1/D2 Negative TLP Curve
1
100
0.8
90
0.6
80
0.4
70
Amplitude (V)
Current (mA)
4.2
Figure 6-14. Enabled Supply Current (ISE) vs Input
Voltage
Current (A)
Current (A)
4
D001
Figure 6-13. Enabled Supply Current (ISE) vs
Temperature
0
All Unit Types
65
62
56
-40
-40 (°C)
25 (°C)
85 (°C)
125 (°C)
80
ISE (PA)
ISE (PA)
70
0.2
0
-0.2
-0.4
D1/D2 Pins
60
50
40
30
20
-0.6
10
-0.8
0
-1
-2 -1 0
1
2
3
4
5 6 7 8
Voltage (V)
9 10 11 12 13 14
-10
-25
0
D001
Figure 6-17. D1/D2 I-V Curve
25
50
75
100 125
Time (ns)
150
175
200
225
D001
Figure 6-18. D1/D2 IEC 61000-4-2 8-kV Contact
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20
D1/D2 Pins
10
0
Amplitude (V)
-10
-20
-30
-40
-50
-60
-70
-80
-25
0
25
50
75
100
Time (ns)
125
150
175
D001
Figure 6-19. D1/D2 IEC 61000-4-2 –8-kV Contact
10
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7 Parameter Measurement Information
IOUT
VIN
IN
OUT
VOUT
150 µF
0.1 µF1
Enable
Signal
RLOAD
EN
D1
D2
GND
Copyright © 2016, Texas Instruments Incorporated
A.
During the short applied tests, 300 µF is used because of the use of an external supply.
Figure 7-1. Test Circuit for System Operation
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8 Detailed Description
8.1 Overview
The TPD3S014-Q1 is a highly integrated device that features a current limited load switch and a two-channel
TVS based ESD protection diode array for USB interfaces. The TPD3S014-Q1 provides 0.5 A of continuous load
current in 5 V circuits. This part uses N-channel MOSFETs for low resistance, maintaining voltage regulation to
the load. It is designed for applications where short circuits or heavy capacitive loads will be encountered.
Device features include enable, reverse blocking when disabled, output discharge pull-down, over-current
protection, and over-temperature protection. Finally, with two channels of TVS ESD protection diodes integrated,
the TPD3S014-Q1 provides system level ESD protection to all the pins of the USB port.
8.2 Functional Block Diagram
Back
Gate
Control
IN
Current
Limit
OUT
UVLO
D2
GND
EN
Control Logic
+
Charge
Pump
D1
Thermal
Sense
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Undervoltage Lockout (UVLO)
The UVLO circuit disables the power switch until the input voltage reaches the UVLO turnon threshold. Built-in
hysteresis prevents unwanted on and off cycling becuase of input voltage drop from large current surges.
8.3.2 Enable
The logic enable input (EN) controls the power switch, bias for the charge pump, driver, and other circuits. The
supply current is reduced to less than 1 µA when the TPD3S014-Q1 is disabled. The enable input is compatible
with both TTL and CMOS logic levels.
The turnon and turnoff times (tON, tOFF) are composed of a delay and a rise or fall time (tR, tF). The delay
times are internally controlled. The rise time is controlled by both the TPD3S014-Q1 and the external loading
(especially capacitance). The TPD3S014-Q1 fall time is controlled by the loading (R and C), and the output
discharge (RPD). An output load consisting of only a resistor experiences a fall time set by the TPD3S014-Q1. An
output load with parallel R and C elements experiences a fall time determined by the (R × C) time constant if it is
longer than the TPD3S014-Q1 tF. See Figure 8-1 and Figure 8-2 showing tR, tF, tON, and tOFF. The enable must
not be left open; it may be tied to VIN.
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VOUT
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tR
90%
tF
VEN
50%
tON
10%
50%
tOFF
Figure 8-1. Power-On and Power-Off Timing
90%
VOUT
10%
Figure 8-2. Enable Timing, Active-High Enable
8.3.3 Internal Charge Pump
The TPD3S014-Q1 incorporates an internal charge pump and gate drive circuitry necessary to drive the Nchannel MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage
to pull the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall
times of the output voltage to limit large current and voltage surges on the input supply, and provides built-in
soft-start functionality. The MOSFET power switch blocks current from OUT to IN when turned off by the UVLO
or disabled.
8.3.4 Current Limit
The TPD3S014-Q1 responds to overloads by limiting output current to the static current-limit (IOS) levels shown
in the Electrical Characteristics: TJ = TA = 25°C table. When an overload condition is present, the device
maintains a constant output current, with the output voltage determined by (IOS × RLOAD). Two possible overload
conditions can occur.
The first overload condition occurs when either:
1. The input voltage is first applied, enable is true, and a short circuit is present (load which draws IOUT > IOS)
or
2. The input voltage is present and the TPD3S014-Q1 is enabled into a short circuit.
The output voltage is held near zero potential with respect to ground and the TPD3S014-Q1 ramps the output
current to IOS. The TPD3S014-Q1 limits the current to IOS until the overload condition is removed or the device
begins to thermal cycle. The device subsequently cycles current off and on as the thermal protection engages.
The second condition is when an overload occurs while the device is enabled and fully turned on. The device
responds to the overload condition within tIOS when the specified overload (per Electrical Characteristics: TJ = TA
= 25°C, Electrical Characteristics: –40°C ≤ TA ≤ 105°C tables) is applied (See Figure 8-3 and Figure 8-4). The
response speed and shape varies with the overload level, input circuit, and rate of application. The current-limit
response varies between simply settling to IOS, or turnoff and controlled return to IOS. Similar to the previous
case, the TPD3S014-Q1 limits the current to IOS until the overload condition is removed or the device begins to
thermal cycle.
I OUT
120% x I OS
V IN
Slope = -RDS(ON)
VOUT
IOS
Decreasing
Load
Resistance
0A
tIOS
Figure 8-3. Output Short Circuit Parameters
0V
0A
IOUT
IOS
Figure 8-4. Output Characteristic Showing Current
Limit
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The TPD3S014-Q1 thermal cycles if an overload condition is present long enough to activate thermal limiting in
any of the cases shown in Figure 8-3 and Figure 8-4. This is because of the relatively large power dissipation
[(VIN – VOUT) × IOS] driving the junction temperature up. The devices turn off when the junction temperature
exceeds 135°C (minimum) while in current limit. The devices remains off until the junction temperature cools
down to 20°C and then restarts.
There are two kinds of current limit profiles typically available in TI switch products similar to the TPD3S014-Q1.
Many older designs have an output I vs V characteristic similar to the plot labeled "Current Limit with Peaking"
in Figure 8-5. This type of limiting can be characterized by two parameters, the current limit corner (IOC), and the
short circuit current (IOS). IOC is often specified as a maximum value. The TPD3S014-Q1 part does not present
noticeable peaking in the current limit, corresponding to the characteristic labeled "Flat Current Limit" in Figure
8-5. This is why the IOC parameter is not present in the Electrical Characteristics: TJ = TA = 25°C, Electrical
Characteristics: –40°C ≤ TA ≤ 105°C tables.
Current Limit
with Peaking
V IN
Flat Current
Limit
Decreasing
Load
Resistance
Decreasing
Load
Resistance
Slope = -RDS(ON)
VOUT
VOUT
Slope = -RDS(ON)
V IN
0V
0V
0A
IOUT
IOS IOC
0A
IOUT
IOS
Figure 8-5. Current Limit Profiles
8.3.5 Output Discharge
A 470 Ω (typical) output discharge resistance dissipates stored charge and leakage current on OUT when the
TPD3S014-Q1 is in UVLO or disabled. The pull-down circuit loses bias gradually as VIN decreases, causing a
rise in the discharge resistance as VIN falls towards 0 V.
8.3.6 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance must be optimized
for the particular application. For all applications, a 0.1 µF or greater ceramic bypass capacitor between IN and
GND is recommended as close to the device as possible for local noise decoupling.
All protection circuits such as the TPD3S014-Q1 has the potential for input voltage overshoots and output
voltage undershoots.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of
input voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high
impedance (before turnon). Theoretically, the peak voltage is 2 times the applied. The second cause is because
of the abrupt reduction of output short circuit current when the TPD3S014-Q1 turns off and energy stored in the
input inductance drives the input voltage high. Input voltage droops may also occur with large load steps and
as the TPD3S014-Q1 output is shorted. Applications with large input inductance (for example, connecting the
evaluation board to the bench power-supply through long cables) may require large input capacitance reduce
the voltage overshoot from exceeding the absolute maximum voltage of the device. The fast current-limit speed
of the TPD3S014-Q1 to hard output short circuits isolates the input bus from faults. However, ceramic input
capacitance in the range of 1 µF to 22 µF adjacent to the TPD3S014-Q1 input aids in both speeding the
response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are
permitted.
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Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred
and the TPD3S014-Q1 has abruptly reduced OUT current. Energy stored in the inductance drives the OUT
voltage down and potentially negative as it discharges. Applications with large output inductance (such as
from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When
implementing USB standard applications, a 120-µF minimum output capacitance is required. Typically a 150µF electrolytic capacitor is used, which is sufficient to control voltage undershoots. However, if the application
does not require 120 µF of capacitance, and there is potential to drive the output negative, a minimum of 10-µF
ceramic capacitance on the output is recommended. The voltage undershoot must be controlled to less than 1.5
V for 10 µs.
8.4 Device Functional Modes
8.4.1 Operation With VIN < 4 V (Minimum VIN)
These devices operate with input voltages above 4 V. The maximum UVLO voltage on IN is 4 V and the devices
will operate at input voltages above 4 V. Any voltage below 4 V may not work with these devices. The minimum
UVLO is 3.5 V, so some devices may work between 3.5 V and 4 V. At input voltages below the actual UVLO
voltage, these devices will not operate.
8.4.2 Operation With EN Control
The enable rising edge threshold voltage is 1.45 V typical and 2 V maximum. With EN held below that voltage
the device is disabled and the load switch will be open. The IC quiescent current is reduced in this state. When
the EN pin is above its rising edge threshold and the input voltage on the IN pin is above its UVLO threshold, the
device becomes active. The load switch is closed, and the current limit feature is enabled. The output voltage on
OUT ramps up with the soft start value TON in order to prevent large inrush current surges on VBUS because of
a heavy capacitive load. When EN voltage is lowered below is falling edge threshold, the device output voltage
also ramps down with soft turnoff value TOFF to prevent large inductive voltages being presented to the system in
the case a large load current is following through the device.
8.4.3 Operation of Level 4 IEC 61000-4-2 ESD Protection
Regardless of which functional mode the devices are in, the TPD3S014-Q1 provides Level 4 IEC 61000-4-2
ESD Protection on the pins of the USB connector.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPD3S014-Q1 is a device that features a current limited load switch and a two-channel TVS based ESD
protection diode array. It is typically used to provide a complete protection solution for USB host ports. USB
host ports are required by the USB specification to provide a current limit on the VBUS path in order to
protect the system from overcurrent conditions on the port that could lead to system damage and user injury.
Additionally, USB ports typically require system level IEC ESD protection because of direct end-user interaction.
The following design procedure can be used to determine how to properly implement the TPD3S014-Q1 in your
systems to provide a complete, one-chip solution for your USB ports.
9.2 Typical Application
From Processor
5 V Source
TPD3S014±Q1
150 F
OUT
EN
IN
USB Port
D1
D2
0.1 F
GND
VBUS
DD+
GND
USB Transceiver
Copyright © 2016, Texas Instruments Incorporated
Figure 9-1. USB2.0 Application Schematic
9.2.1 Design Requirements
For this design example, design parameters shown in Table 9-1 are used.
Table 9-1. Design Parameters
(1)
16
DESIGN PARAMETER
VALUE
USB port type
Standard downstream port
Signal voltage range on VBUS
0 V to 5.25 V
Current range on VBUS
0 mA to 500 mA
Drive EN low (disabled)
0 V to 0.7 V(1)
Drive EN high (enabled)
2 V to 5.5 V(1)
Maximum voltage droop allowed on adjacent USB port
330 mV
Maximum data rate
480 Mbps
If active low logic is desired, see the Implementing Active Low Logic section.
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9.2.2 Detailed Design Procedure
To properly implement your USB port with the TPD3S014-Q1, the first step is to determine what type of USB
port is implemented in the system, whether it be a Standard Downstream Port (SDP), Charging Downstream
Port (CDP), or Dedicated Charging Port (DCP); this informs us what maximum continuous operating current will
be on VBUS. In our example, we are implementing an SDP port, so the maximum continuous current allowed
to be pulled by a device is 500 mA. Therefore, we must choose a current limit switch that is 5.25 V tolerant,
can handle 500 mA continuous DC current, and has a current limit point is above 500 mA so it will not current
limit during normal operation. The TPD3S014-Q1 is therefore the best choice for this application, as it has these
features, and in fact was specifically designed for this application.
The next decision point is choosing the input and output capacitors for the current limit switch. A minimum of
0.1 µF is always recommended on the IN pin. For the OUT pin on VBUS, USB standard requires a minimum
of 120 µF; typically a 150 µF capacitor is used. The purpose of the capacitance requirement on the VBUS line
in the USB specification is to prevent the adjacent USB port's VBUS voltage from dropping more than 330 mV
during a hot-plug or fault occurrence on the VBUS pin of one USB port. Hot-plugs and fault conditions on one
USB port must not disturb the normal operation of an adjacent USB port; therefore, it is possible to use an output
capacitance lower than 120 µF if the system is able to keep voltage droops on adjacent USB ports less than or
equal to 330 mV. For example, if the DC/DC powering VBUS has a fast transient response, 120 µF may not be
required.
If the USB port is powered from a shared system 5 V rail, a system designer may desire to use an input
capacitor larger than 0.1 µF on the IN pin. This is largely dependent on the PCB layout and parasitics, as well
as your maximum tolerated voltage droop on the shared rail during transients. For more information on choosing
input and output capacitors, see the Input and Output Capacitance section.
The EN pin controls the on and off state of the device, and typically is connected to the system processor for
power sequencing. However, the EN pin can also be shorted to the IN pin to always have the TPD3S014-Q1 on
when 5 V power supply on; this also saves a GPIO pin on your processor.
For a USB port with High-Speed 480 Mbps operation, low capacitance TVS ESD protection diodes are required
to protect the D+ and D– lines in the event of system level ESD event. The TPD3S014-Q1 has 2-channels of low
capacitance TVS ESD protection diodes integrated. When placed near the USB connector, the TPD3S014-Q1
offers little or no signal distortion during normal operation. The TPD3S014-Q1 also ensures that the core
system circuitry is protected in the event of an ESD strike. PCB layout is critical when implementing TVS ESD
protection diodes in your system. See the Layout section for proper guidelines on routing your USB lines with the
TPD3S014-Q1.
9.2.3 Implementing Active Low Logic
For active low logic, a transistor can be used with the TPD3S014-Q1 EN Pin. Figure 9-2 shows how to
implement Active low logic for EN pin.
Using an nFET transistor, when the Processor sends a low signal, the transistor is switched off, and VLOGIC pulls
up EN through R1. When the Processor sends a “high” signal, the nFET is switched on and sinks current from
the EN Pin and R1. For 5 V VLOGIC, with the appropriate on-resistance (RON) value in the nFET and resistance
for R1, the VIL for EN can be met. For example, with a transistor with RON of 3 Ω, a pull-up resistor as low as 11
Ω provides a logic level of 0.7 V. For power-budgeting concerns, a better choice is R1 of 40 kΩ which provides
0.25 V for EN when the Processor asserts high, and 4.96 V when the Processor asserts low.
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VLOGIC
R1
TPD3S014-Q1 40 kΩ
Processor
EN
EN_Out
Copyright © 2016, Texas Instruments Incorporated
Figure 9-2. Implementing Active Low Logic for EN Pin
9.2.4 Application Curves
Figure 9-3. Eye-Diagram Without EVM
Figure 9-4. Eye-Diagram With EVM, Without
TPD3S014-Q1
Figure 9-5. Eye-Diagram of TPD3S014-Q1 on EVM
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10 Power Supply Recommendations
The TPD3S014-Q1 is designed to operate from a 5-V input voltage supply. This input must be well regulated.
If the input supply is located more than a few inches away from the TPD3S014-Q1, additional bulk capacitance
may be required in addition to the recommended minimum 0.1-µF bypass capacitor on the IN pin to keep the
input rail stable during fault events.
11 Layout
11.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
GND
GND
D+
Top Layer GND Plane
EN
D2
GND
D1
IN
OUT
D-
VBUS
Via
Figure 11-1. USB2.0 Type A TPD3S014-Q1 Board Layout
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11.3 Power Dissipation and Junction Temperature
It is good design practice to estimate power dissipation and maximum expected junction temperature of the
TPD3S014-Q1. The system designer can control choices of the devices proximity to other power dissipating
devices and printed circuit board (PCB) design based on these calculations. These have a direct influence on
maximum junction temperature. Other factors, such as airflow and maximum ambient temperature, are often
determined by system considerations. It is important to remember that these calculations do not include the
effects of adjacent heat sources, and enhanced or restricted air flow. Addition of extra PCB copper area around
these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low
as practical. In particular, connect the GND pin to a large ground plane for the best thermal dissipation. The
following PCB layout example in Figure 11-2 was used to determine the RθJA Custom thermal impedances noted
in the Thermal Information table. It is based on the use of the JEDEC high-k circuit board construction with 4, 1
oz. copper weight layers (2 signal and 2 plane).
GND
GND
D+
EN
D2
GND
D1
IN
OUT
D-
V BUS
OUT: W: 10.424 mm, H:4.536 mm, A: 47.28 mm
2
GND: W: 6.57 mm, H: 7.53 mm, A: 49.47 mm
& 6 x 0.879 mm diameter vias
IN: W: 4.26 mm
H: 5.82 mm
2
A: 24.79 mm
& 4 x 0.879 mm
diameter vias
2
GND: W: 4.44 mm, H: 4.00 mm, A: 17.76 mm
& 2 x 0.533 mm diameter vias
2
Figure 11-2. PCB Layout Example
The following procedure requires iteration a power loss is because of the internal MOSFET I2 × RDS(ON), and
RDS(ON) is a function of the junction temperature. See Equation 1. As an initial estimate, use the RDS(ON) at
105°C from the Typical Characteristics, and the preferred package thermal resistance for the preferred board
construction from the Thermal Information table.
TJ = TA + [(IOUT 2 × RDS(ON)) × RθJA]
(1)
where
•
•
•
20
IOUT = Rated OUT pin current (A)
RDS(ON) = Power switch on-resistance at an assumed TJ (Ω)
TA = Maximum ambient temperature (°C)
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•
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TJ = Maximum junction temperature (°C)
RθJA = Thermal resistance (°C/W)
If the calculated TJ is substantially different from the original assumption, estimate a new value of RDS(ON) using
the typical characteristic plot and recalculate.
If the resulting TJ is not less than 125°C, try a PCB construction with a lower RθJA. The junction temperature
derating curve based on the TI standard reliability duration is shown in Figure 11-3.
130
TI Standard
125
120
TJ (qC)
115
110
105
100
95
90
85
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
IOUT (ADC)
1
1.1
1.2
1.3
1.4
1.5
1.6
D001
Figure 11-3. Junction Temperature Derating Curve
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TPD3S014-Q1EVM User's Guide, SLVUAQ0.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD3S014TDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 105
13WW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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