TPD6E004RSER

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPD6E004 SLLS799B – FEBRUARY 2008 – REVISED APRIL 2016 TPD6E004 Low-Capacitance, 6-Channel ±15-kV ESD Protection Array for High-Speed Data Interfaces 1 Features 3 Description • The TPD6E004 device is a low-capacitance, ±15-kV ESD-protection diode array designed to protect sensitive electronics attached to communication lines. Each channel consists of a pair of diodes that steers ESD current pulses to VCC or GND. The TPD6E004 protects against ESD pulses up to ±15-kV humanbody model (HBM), ±8-kV contact ESD, and ±12-kV air-gap ESD as specified in IEC 61000-4-2. This device has a typical 1.6-pF capacitance per channel, making it ideal for use in high-speed data I/O interfaces. 1 • • • • ESD Protection Exceeds JESD – ±15-kV Human-Body Model (HBM) – ±8-kV IEC 61000-4-2 Contact Discharge – ±12-kV IEC 61000-4-2 Air-Gap Discharge Low 1.6-pF I/O Capacitance 0.9-V to 5.5-V Supply-Voltage Range 6-Channel Device Space-Saving UQFN (RSE) Package 2 Applications • • • • • • • The TPD6E004 device is available in the RSE package and is specified for –40°C to +85°C operation. USB Ethernet FireWire Video Cell Phones SVGA Video Connections Glucose Meters The TPD6E004 device is a six-channel ESD structure designed for USB, Ethernet, and FireWire applications. Device Information(1) PART NUMBER TPD6E004 PACKAGE UQFN (8) BODY SIZE (NOM) 1.50 mm × 1.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram VCC IO1 IO2 IO3 IO4 IO5 IO6 GND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD6E004 SLLS799B – FEBRUARY 2008 – REVISED APRIL 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 3 3 4 4 4 4 5 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. ESD Ratings – Surge Protection............................... Recommended Operating Conditions....................... Thermal Information ................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 6 7.1 Overview ................................................................... 6 7.2 Functional Block Diagram ......................................... 6 7.3 Feature Description................................................... 6 7.4 Device Functional Modes.......................................... 6 8 Application and Implementation .......................... 7 8.1 Application Information.............................................. 7 8.2 Typical Application ................................................... 7 9 Power Supply Recommendations........................ 9 10 Layout..................................................................... 9 10.1 Layout Guidelines ................................................... 9 10.2 Layout Example ...................................................... 9 11 Device and Documentation Support ................. 10 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 10 10 10 10 10 12 Mechanical, Packaging, and Orderable Information ........................................................... 10 4 Revision History Changes from Revision A (February 2008) to Revision B • 2 Page Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6E004 TPD6E004 www.ti.com SLLS799B – FEBRUARY 2008 – REVISED APRIL 2016 5 Pin Configuration and Functions IO2 IO3 1 2 3 4 7 6 5 IO5 IO4 8 IO6 VCC IO1 RSE Package 8-Pin UQFN Bottom View GND Pin Functions PIN NO. NAME I/O DESCRIPTION 1 IO1 I/O ESD-protected channel 2 IO2 I/O ESD-protected channel ESD-protected channel 3 IO3 I/O 4 GND GND 5 IO4 I/O ESD-protected channel 6 IO5 I/O ESD-protected channel 7 IO6 I/O ESD-protected channel 8 VCC PWR Ground Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor. 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Operating voltage for pin VCC –0.3 5.5 V VI/O Operating voltage for pins IO1, IO2, IO3, IO4, IO5 and IO6 –0.3 VCC + 0.3 V Bump temperature (soldering) Infrared (15 s) 220 Vapor phase (60 s) 215 Lead temperature (soldering, 10 s) TJ Junction temperature Tstg Storage temperature (1) –65 °C 300 °C 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±15000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6E004 3 TPD6E004 SLLS799B – FEBRUARY 2008 – REVISED APRIL 2016 www.ti.com 6.3 ESD Ratings – Surge Protection VALUE V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±8000 IEC 61000-4-2 air-gap discharge ±12000 UNIT V 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX TA Operating free-air temperature –40 85 UNIT °C VCC Operating voltage for pin VCC 0.9 5.5 V VI/O Operating voltage for pins IO1, IO2, IO3, IO4, IO5 and IO6 0 Minimum of: (5.8, VCC) V 6.5 Thermal Information TPD6E004 THERMAL METRIC (1) RSE (UQFN) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 138.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 74.7 °C/W RθJB Junction-to-board thermal resistance 43.9 °C/W ψJT Junction-to-top characterization parameter 3.6 °C/W ψJB Junction-to-board characterization parameter 43.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.6 Electrical Characteristics VCC = 5 V ± 10%, TA = TMIN to TMAX (unless otherwise noted) PARAMETER TEST CONDITIONS VCC Supply voltage ICC Supply current VF Diode forward voltage II Channel leakage current VBR Break-down voltage II = 10 μA CI/O Channel input capacitance VCC = 5 V, bias of VCC/2, f = 10 MHz (1) 4 MIN TYP (1) 0.9 IF = 1 mA MAX V 500 nA 0.8 V ±1 6 1.6 UNIT 5.5 nA 8 V 2 pF Typical values are at VCC = 5 V and TA = 25°C. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6E004 TPD6E004 www.ti.com SLLS799B – FEBRUARY 2008 – REVISED APRIL 2016 6.7 Typical Characteristics 160 70 140 60 120 Leakage Current (pA) IO Current (mA) 50 100 80 60 40 20 40 30 20 10 0 0 1.05 1.15 1.25 1.35 1.45 1.55 –40 55 25 IO Voltage (V) 85 Temperature (°C) VCC = 0 V, DC Sweep Across the I/O Pin VI/O = 2.5 V Figure 1. Forward Diode Voltage (Upper Clamp Diode) Figure 2. Leakage Current vs Temperature 5.0 16.0 14.0 4.0 IO Capacitance (pF) 12.0 IO Current (µA) 10.0 8.0 6.0 4.0 3.0 2.0 1.0 2.0 0.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 1 7.0 2 3 4 5 IO Voltage (V) IO Voltage (V) VCC = 5 V VCC = Open Figure 3. Reverse Diode Curve Current I/O to GND Figure 4. I/O Capacitance vs Input Voltage Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6E004 5 TPD6E004 SLLS799B – FEBRUARY 2008 – REVISED APRIL 2016 www.ti.com 7 Detailed Description 7.1 Overview The TPD6E004 device is a six-channel TVS protection diode array. The TPD6E004 is rated to dissipate ESD strikes of ±8-kV contact and ±12-kV air-gap, as specified in the IEC 61000-4-2 international standard. This device has 1.6-pF capacitance per I/O channel, making it ideal for use in high-speed data I/O interfaces. 7.2 Functional Block Diagram VCC IO1 IO2 IO3 IO4 IO5 IO6 GND Copyright © 2016, Texas Instruments Incorporated Figure 5. Logic Block Diagram 7.3 Feature Description The TPD6E004 is a TVS that provides ESD protection for up to six channels, withstanding up to ±8-kV contact and ±12-kV air-gap ESD per IEC 61000-4-2. The monolithic technology yields exceptionally small variations in capacitance between any I/O pin of the TPD6E004. The small footprint is ideal for applications where spacesaving designs are important. 7.4 Device Functional Modes The TPD6E004 device is a passive integrated circuit that triggers when voltages are above VBR or below the diodes VF of approximately –0.8 V. During ESD events, voltages as high as ±8-kV contact and ±12-kV air-gap ESD can be directed to ground through the internal diodes. When the voltages on the protected line fall below the trigger levels of TPD6E004 (usually within 10s of nano-seconds) the device reverts back to its highimpedance state. 6 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6E004 TPD6E004 www.ti.com SLLS799B – FEBRUARY 2008 – REVISED APRIL 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPD6E004 device is a TVS diode array typically used to provide a path to ground for dissipating ESD events on high-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected integrated circuit (IC). The triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC. 8.2 Typical Application VBUS DD+ ID GND 0.1 µF USB Controller TPD6E004 IO1 VCC IO2 IO3 Micro-B USB Connector IO6 IO5 IO4 GND Micro-B USB Connector VBUS DD+ ID GND Copyright © 2016, Texas Instruments Incorporated Figure 6. Two-Port Micro-B USB 2.0 Application 8.2.1 Design Requirements For this design example, a single TPD6E004 is used to protect all the pins of two USB 2.0 Micro-B connectors. Table 1 lists the design parameters for the USB application. Table 1. Design Parameters DESIGN PARAMETER VALUE Signal range on IO1, IO2, IO3, IO4, IO5 and IO6 0 V to 3.6 V Signal voltage range on VCC 0 V to 5.5 V Operating Frequency 240 MHz Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6E004 7 TPD6E004 SLLS799B – FEBRUARY 2008 – REVISED APRIL 2016 www.ti.com 8.2.2 Detailed Design Procedure When placed near the USB connectors, the TPD6E004 ESD solution offers little or no signal distortion during normal operation due to low I/O capacitance and ultra-low leakage current specifications. The TPD6E004 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, the Layout and following design guidelines must be followed: 1. Place the TPD6E004 solution close to the connectors. This allows the TPD6E004 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board. 2. Place a 0.1-μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the I/O pin during the ESD strike event. 3. Ensure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD6E004 consumes only μA of leakage current, but during an ESD event, VCC and GND may see 15-A to 30-A of current, depending on the ESD level. A sufficient current path enables the safe discharge of all the energy associated with the ESD strike. 4. Leave any unused I/O pins floating. In this example of protecting two Micro-B USB ports, none of the I/O pins are left unused. 5. The VCC pin can be connected in two different ways: (a) If the VCC pin is connected to the system power supply, the TPD6E004 works as a transient suppressor for any signal swing above VCC + VF. TI recommends a 0.1-μF capacitor on the device VCC pin for ESD bypass. (b) If the VCC pin is not connected to the system power supply, the TPD6E004 can tolerate a higher signal swing in the range of up to 5.8 V. NOTE A 0.1-μF capacitor is still recommended at the VCC pin for ESD bypass. 8.2.3 Application Curve Figure 7 is a capture of the voltage clamping waveform of the TPD6E004 during a +8-kV contact IEC 61000-4-2 ESD strike. 220 200 180 160 Amplitude (V) 140 120 100 80 60 40 20 0 –20 0 25 50 75 100 125 150 Time (ns) 175 200 225 250 Figure 7. IEC 61000-4-2 +8-kV Contact ESD Clamping Waveform 8 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6E004 TPD6E004 www.ti.com SLLS799B – FEBRUARY 2008 – REVISED APRIL 2016 9 Power Supply Recommendations The TPD6E004 device is a passive ESD protection device, so there is no need to power it. Do not violate the maximum voltage specifications for each pin. 10 Layout 10.1 Layout Guidelines • • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any corners less than 135° on the protected traces between the TVS and the connector. Best practice is using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. Connect the ground pin to a same layer ground pour which is connected to an internal ground plane with a VIA. Place the VIA very near the ground pin. 10.2 Layout Example Legend VBUS VIA in SMD Pad Top Layer Routing Signal VIA Secondary Layer Routing Pin to GND VIA to Internal GND Plane D1D1+ ID1 USB Connector TPD6E004 D1D1+ { ID1 To USB Controller D2D2+ USB Connector ID2 VBUS D2D2+ ID2 Copyright © 2016, Texas Instruments Incorporated Figure 8. TPD6E004 Layout Example for Two USB 2.0 Micro-B Connectors Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6E004 9 TPD6E004 SLLS799B – FEBRUARY 2008 – REVISED APRIL 2016 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • • Reading and Understanding an ESD Protection Datasheet, SLLA305 ESD Protection Layout Guide, SLVA680 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6E004 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPD6E004RSER ACTIVE UQFN RSE 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2V (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of