TPD1E05U06, TPD4E05U06, TPD6E05U06
SLVSBO7N – DECEMBER 2012 – REVISED FEBRUARY 2022
TPDxE05U06 1, 4, 6 Channel ESD Protection Device
for Super-Speed (Up to 6 Gbps) Interface
1 Features
3 Description
•
The TPDxE05U06 is a family of unidirectional
Transient
Voltage
Suppressor
(TVS)
based
Electrostatic Discharge (ESD) protection diodes with
ultra-low capacitance. Each device can dissipate ESD
strikes above the maximum level specified by the IEC
61000-4-2 international standard. The TPDxE05U06s
ultra-low loading capacitance makes it ideal for
protecting any high-speed signal pins.
•
•
•
•
•
•
•
•
•
IEC 61000-4-2 level 4 ESD protection
– ±12-kV contact discharge
– ±15-kV air gap discharge
IEC 61000-4-4 EFT protection
– 80 A (5/50 ns)
IEC 61000-4-5 surge protection
– 2.5 A (8/20 µs)
IO capacitance 0.42 pF to 0.5 pF (typical)
DC breakdown voltage 6.5 V (minimum)
Ultra low leakage current 10 nA (maximum)
Low ESD clamping voltage
Industrial temperature range: –40°C to +125°C
Easy straight-through routing packages
Industry standard SOD-523 package
(1.60 mm × 0.80 mm × 0.65 mm)
Typical applications for TPDxE05U06 includes high
speed signal lines in HDMI 1.4b, HDMI 2.0, USB 3.0,
MHL, LVDS, DisplayPort, PCI-Express®, eSata, and
V-by-One® HS.
Device Information(1)
PART NUMBER
0.60 mm × 1.00 mm
SOD-523 (2)
0.80 mm × 1.20 mm
TPD4E05U06
USON (10)
2.50 mm × 1.00 mm
TPD6E05U06
USON (14)
3.50 mm × 1.35 mm
TPD1E05U06
•
•
•
•
•
•
•
•
•
(1)
TPD4E05U06
For all available packages, see the orderable addendum at
the end of the data sheet.
1
2
4
5
GND
GND
3
BODY SIZE (NOM)
X1SON (2)
2 Applications
HDMI 1.4b
HDMI 2.0
USB 3.0
MHL
LVDS interfaces
DisplayPort
PCI-express®
eSata interfaces
V-by-One® HS
PACKAGE
8
D0+
D1+
D1-
D2+
D2-
Connector
D1+
D1D2+
D2-
GND
TPD4E05U06 Functional Block Diagram
CLK+
CLKTPD4E05U06
GND
GND
HDMI Controller
D0-
3
1
2
4
5
8
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD1E05U06, TPD4E05U06, TPD6E05U06
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SLVSBO7N – DECEMBER 2012 – REVISED FEBRUARY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
Absolute Maximum Ratings.............................................. 6
6.1 ESD Ratings—JEDEC Specification...........................6
6.2 ESD Ratings—IEC Specification................................ 6
Recommended Operating Conditions...............................6
6.3 Thermal Information....................................................7
6.4 Electrical Characteristics.............................................7
6.5 Typical Characteristics................................................ 9
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................12
8 Application and Implementation.................................. 13
8.1 Application Information............................................. 13
8.2 Typical Applications.................................................. 13
9 Power Supply Recommendations................................16
10 Layout...........................................................................17
10.1 Layout Guidelines................................................... 17
10.2 Layout Example...................................................... 17
11 Device and Documentation Support..........................19
11.1 Documentation Support.......................................... 19
11.2 Receiving Notification of Documentation Updates.. 19
11.3 Support Resources................................................. 19
11.4 Trademarks............................................................. 19
11.5 Electrostatic Discharge Caution.............................. 19
11.6 Glossary.................................................................. 19
12 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (January 2017) to Revision N (February 2022)
Page
• Updated the SOD-523 package information from the body size dimensions (0.8 mm × 1.2 mm) to the lead-tolead dimensions (1.60 mm × 0.80 mm × 0.65 mm) ........................................................................................... 1
Changes from Revision L (January 2017) to Revision M (December 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the Features section to include SOD-523 package information...........................................................1
• Added the DYA package to the Device Information table...................................................................................1
• Added the DYA package to the Pin Configuration and Functions section.......................................................... 4
• Changed the minimum DC breakdown voltage from 6 V to 6.5 V in the Detailed Description section.............12
• Changed the minimum reverse standoff voltage from 5 V to 5.5 V in the Detailed Description section...........12
• Updated the Related Documentation section................................................................................................... 19
Changes from Revision K (November 2016) to Revision L (January 2017)
Page
• Updated DPY pinout image................................................................................................................................ 4
• Updated title from TPD4E05U06 to TPD6E05U06 in Figure 7-3 ..................................................................... 11
Changes from Revision J (March 2016) to Revision K (November 2016)
Page
• Changed min value of VBR from 6 V to 6.5 V in the Electrical Characteristics table...........................................6
Changes from Revision I (June 2015) to Revision J (March 2016)
Page
• Replaced all instances of X2SON with X1SON ................................................................................................. 1
• Update the Pin Functions table ..........................................................................................................................4
• Added the Power Supply Recommendations section.......................................................................................16
Changes from Revision H (May 2015) to Revision I (June 2015)
Page
• Added trademarks ............................................................................................................................................. 1
• Corrected TPD6E05U06 Pin 13 name................................................................................................................4
• Corrected TLP definition..................................................................................................................................... 6
2
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SLVSBO7N – DECEMBER 2012 – REVISED FEBRUARY 2022
Changes from Revision G (July 2014) to Revision H (May 2015)
Page
• Added additional application...............................................................................................................................1
• Updated with HDMI 2.0 Eye Diagrams............................................................................................................. 14
Changes from Revision F (November 2013) to Revision G (July 2014)
Page
• Added 61000-4-4 EFT compliance..................................................................................................................... 1
• Added Thermal Information table....................................................................................................................... 6
• Added Handling Ratings table............................................................................................................................ 6
• Added the Detailed Description section............................................................................................................ 11
• Added the Application and Implementation section..........................................................................................13
• Added Layout section. ..................................................................................................................................... 17
Changes from Revision * (December 2012) to Revision A (December 2012)
Page
• Added TPS2EUSB30A part to document........................................................................................................... 1
Changes from Revision A (December 2012) to Revision B (January 2013)
Page
• Added Insertion Loss Graphic............................................................................................................................ 9
• Added Eye Diagrams........................................................................................................................................14
Changes from Revision B (January 2013) to Revision C (March 2013)
Page
• Changed IO Capacitance range......................................................................................................................... 1
• Changed test conditions and typ values for Vclamp ............................................................................................ 6
• Added typ RDYN values for DQA and RVZ packages......................................................................................... 6
• Added CL values for DQA and RVZ packages................................................................................................... 6
• Changed CURRENT vs VOLTAGE graphic........................................................................................................9
• Changed Insertion Loss graphic......................................................................................................................... 9
• Changed HDMI Eye Diagrams......................................................................................................................... 14
Changes from Revision C (March 2013) to Revision D ()
Page
• Updated Title.......................................................................................................................................................1
• Removed Ordering Information table..................................................................................................................4
Changes from Revision D (August 2013) to Revision E (November 2013)
Page
• Updated document formatting............................................................................................................................ 1
• Added additional application...............................................................................................................................1
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SLVSBO7N – DECEMBER 2012 – REVISED FEBRUARY 2022
5 Pin Configuration and Functions
ID Area
I/O
1
1
2
2
GND
Figure 5-1. DPY Package 2-Pin X1SON Top View
Figure 5-2. DYA Package 2-Pin SOD-523 Top View
Table 5-1. Pin Functions TPD1E05U06 DPY and DYA
PIN
NAME
NO.
TYPE
GND
2
Ground
I/O
1
I/O
(1)
DESCRIPTION
Ground; Connect to ground
ESD protected channel(1)
Place as close to the connector as possible.
D1+
1
10
NC
D1–
2
9
NC
GND
3
8
GND
D2+
4
7
NC
D2–
5
6
NC
Figure 5-3. DQA Package 10-Pin USON Top View
Table 5-2. Pin Functions TPD4E05U06 DQA
PIN
NAME
TYPE
DESCRIPTION
D1+
1
I/O
ESD protected channel(1)
D1–
2
I/O
ESD protected channel(1)
D2+
4
I/O
ESD protected channel(1)
D2–
5
I/O
ESD protected channel(1)
GND
3
GND
8
NC
6
NC
7
NC
9
NC
10
(1)
4
NO.
Ground
—
Ground; Connect to ground
Not connected; Used for optional straight-through routing. Can be left floating or grounded
Place as close to the connector as possible.
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SLVSBO7N – DECEMBER 2012 – REVISED FEBRUARY 2022
NC
1
14
D1+
NC
2
13
D1–
NC
3
12
D2+
NC
4
11
D2–
GND
5
10
GND
NC
6
9
D3+
NC
7
8
D3–
Figure 5-4. RVZ Package 14-Pin USON Top View
Table 5-3. Pin Functions TPD6E05U06 RVZ
PIN
NAME
NO.
TYPE
DESCRIPTION
D1+
14
I/O
ESD protected channel(1)
D1–
13
I/O
ESD protected channel(1)
D2+
12
I/O
ESD protected channel(1)
D2–
11
I/O
ESD protected channel(1)
D3+
9
I/O
ESD protected channel(1)
D3–
8
I/O
ESD protected channel(1)
GND
5
GND
10
NC
1
NC
2
NC
3
NC
4
NC
6
NC
7
(1)
Ground
—
Ground; Connect to ground
Not connected; Used for optional straight-through routing. Can be left floating or grounded
Place as close to the connector as possible.
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SLVSBO7N – DECEMBER 2012 – REVISED FEBRUARY 2022
6 Specifications
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Electrical Fast Transient
(2) (3)
Peak Pulse
(2) (3)
MAX
UNIT
IEC 61000-4-4 (5/50ns)
80
A
IEC 61000-4-5 Current
(8/20us)
2.5
A
IEC 61000-4-5 Power
(8/20us)
40
W
TA
Ambient Operating
Temperature
-40
125
°C
Tstg
Storage Temperature
-65
155
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Voltages are with respect to GND unless otherwise noted.
Measured at 25℃
6.1 ESD Ratings—JEDEC Specification
V(ESD)
V(ESD)
(1)
(2)
Electrostatic discharge – DPY, DQA, and RVZ
Electrostatic discharge – DYA
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001 (1)
±4000
V
Charged device model (CDM), per JEDEC
specification JESD22-C101 (2)
±1500
V
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001
±2500
V
Charged device model (CDM), per JEDEC
specification JS-002
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±4000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1500 V may actually have higher performance.
6.2 ESD Ratings—IEC Specification
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 contact discharge
±12000
IEC 61000-4-2 air-gap discharge
±15000
UNIT
V
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
6
VIO
Input pin voltage
TA
Operating free-air
temperature
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NOM
MAX
UNIT
0
5.5
V
-40
125
°C
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SLVSBO7N – DECEMBER 2012 – REVISED FEBRUARY 2022
6.3 Thermal Information
TPD1E05U06
THERMAL METRIC
(1)
TPD4E05U06
TPD6E05U06
UNIT
DPY (X1SON)
DYA (SOD523)
DQA (USON)
RVZ (USON)
2 PINS
2 PINS
10 PINS
14 PINS
697.3
772.1
327
197.9
°C/W
471
444.6
189.5
119.1
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal
resistance
RθJB
Junction-to-board thermal resistance
575.9
540.4
257.7
92.6
°C/W
ΨJT
Junction-to-top characterization
parameter
175.7
159.9
60.9
22
°C/W
ΨJB
Junction-to-board characterization
parameter
575.1
533.9
257
91.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
INPUT - OUTPUT RESISTANCE
VRWM
Reverse stand-off voltage
IIO < 10 µA
VBR
Break-down voltage
IIO = 1 mA
VClamp Clamp voltage
6.5
IPP = 1 A, TLP, from I/O to GND (1)
10
IPP = 5 A, TLP, from I/O to GND (1)
14
IPP = 1 A, TLP, from GND to I/O (1)
3
IPP = 5 A, TLP, from GND to I/O (1)
ILEAK
Leakage current
VIO = 2.5 V
DPY package
DYA package
RDYN
Dynamic
resistance
DQA package
RVZ package
0.8
GND to I/O (2)
0.8
(2)
0.8
GND to I/O (2)
0.7
(2)
0.8
GND to I/O (2)
0.8
(2)
0.8
GND to I/O (2)
0.8
I/O to GND
I/O to GND
I/O to GND
V
8.5
V
V
7
0.01
(2)
I/O to GND
5.5
10
nA
Ω
CAPACITANCE
CL
Δ CIOTO-GND
Line capacitance
VIO = 2.5 V; ƒ = 1 MHz , I/O to
GND
(3)
Variation of input capacitance
TPD1E05U06
DPY
package
0.42
TPD1E05U06
DYA
package
0.42
TPD4E05U06
DQA
package
0.5
TPD6E05U06
RVZ
package
0.47
GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V,
Channel x pin to GND – channel y pin to GND
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pF
0.05
0.07
pF
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SLVSBO7N – DECEMBER 2012 – REVISED FEBRUARY 2022
6.4 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CCROS
S
(1)
(2)
(3)
8
TEST CONDITION
Channel to channel input capacitance
MIN
GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V,
between channel pins
TYP
MAX UNIT
0.01
0.06
pF
Transition line pulse with 100 ns width, 200 ps rise time.
Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A.
Capacitance data is taken at 25°C.
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SLVSBO7N – DECEMBER 2012 – REVISED FEBRUARY 2022
6.5 Typical Characteristics
3.5
1.0
0.8
50
Current
Power
3.0
45
40
0.6
2.5
0.2
0.0
±0.2
±0.4
35
30
2.0
25
1.5
20
Power (W)
Current (A)
Current (mA)
0.4
15
1.0
10
±0.6
0.5
±0.8
5
0
0.0
±1.0
±2
0
±1
1
2
3
4
5
6
7
8
9
Voltage (V)
10
0
±5
5
10
15
20
25
30
35
40
45
50
Time ( s)
C001
C002
.
.
Figure 6-1. DC Voltage Sweep I-V Curve
Figure 6-2. Surge Curve (tp = 8/20 μs), Pin IO to GND
25
35
30
20
20
Current (A)
Current (A)
25
15
10
5
15
10
5
0
0
±5
0
5
10
15
20
25
30
35
Voltage (V)
0
40
5
10
15
20
25
Voltage (V)
C003
.
C008
.
Figure 6-3. Positive TLP Plot IO to GND
Figure 6-4. Negative TLP Plot IO to GND
300
80
70
250
200
Voltage (V)
Current (pA)
60
150
100
50
40
30
20
10
50
0
0
±10
±40
±20
0
20
40
60
80
Temperature (ƒC)
100
120
0
25
50
75
.
Figure 6-5. Leakage vs Temperature
100
125
150
Time (ns)
C004
175
200
C005
.
Figure 6-6. 8-kV IEC Waveform
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6.5 Typical Characteristics (continued)
10
0
0
±1
±2
±10
±3
Insertion Loss (dB)
Voltage (V)
±20
±30
±40
±50
±60
±4
±5
±6
±7
±8
±9
±70
±10
±80
±11
±90
0
25
50
75
100
125
150
Time (ns)
175
200
±12
100k
1M
10M
C007
Figure 6-8. TPD1E05U06 Insertion Loss
Figure 6-7. –8-kV IEC Waveform
0
0
±1
±1
Insertion Loss (dB)
Insertion Loss (dB)
10G
10000M
.
.
±2
±3
±4
±5
±2
±3
±4
±5
±6
100k
1M
10M
1G
1000M
100M
Frequency (Hz)
10G
10000M
C009
±6
100k
1M
10M
Figure 6-9. TPD4E05U06 Insertion Loss
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1G
1000M
100M
Frequency (Hz)
.
10
1G
1000M
100M
Frequency (Hz)
C006
10G
10000M
C010
.
Figure 6-10. TPD6E05U06 Insertion Loss
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7 Detailed Description
7.1 Overview
The TPDxE05U06 is a family of unidirectional Transient Voltage Suppressor (TVS) based Electrostatic
Discharge (ESD) protection diodes with ultra-low capacitance. Each device can dissipate ESD strikes above
the maximum level specified by the IEC 61000-4-2 international standard. The TPDxE05U06s ultra-low loading
capacitance makes it ideal for protecting any high-speed signal pins.
7.2 Functional Block Diagram
I/O
GND
Figure 7-1. TPD1E05U06 Block Diagram
D1+
D1-
D2+
D2-
GND
Figure 7-2. TPD4E05U06 Block Diagram
D1+
D1-
D2+
D2-
D3+
D3-
GND
Figure 7-3. TPD6E05U06 Block Diagram
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7.3 Feature Description
The TPDxE05U06 is a family of unidirectional Transient Voltage Suppressor (TVS) Electrostatic Discharge
(ESD) protection diodes with ultra-low capacitance. Each device can dissipate ESD strikes above the maximum
level specified by the IEC 61000-4-2 international standard. The TPDxE05U06s ultra-low loading capacitance
makes it ideal for protecting any high-speed signal pins.
7.3.1 ±15-kV IEC61000-4-2 Level 4 ESD Protection
The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air. An ESD-surge clamp diverts the
current to ground.
7.3.2 IEC61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground. This has been validated on the TPD4E05U06
only.
7.3.3 IEC61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2.5 A and 40 W (8/20 µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.4 I/O Capacitance
The capacitance between each I/O pin to ground is 0.42 pF (TPD1E05U06), 0.5 pF (TPD4E05U06) or 0.47 pF
(TPD6E05U06). These devices support data rates up to 6 Gbps.
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of 6.5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of 5.5 V.
7.3.6 Ultra-Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of 2.5 V.
7.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 10 V (IPP = 1 A).
7.3.8 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
7.3.9 Easy Flow-Through Routing
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The TPDxE05U06 is a passive integrated circuit that triggers when voltages are above VBR or below the lower
diodes Vf (–0.6 V). During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the
internal diode network. When the voltages on the protected line fall below the trigger levels of TPDxE05U06
(usually within 10s of nano-seconds) the device reverts to passive.
12
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPDxE05U06 is a diode type TVS which is typically used to provide a path to ground for dissipating ESD
events on hi-speed signal lines between a human interface connector and a system. As the current from ESD
passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to
the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected
IC.
8.2 Typical Applications
8.2.1 HDMI 2.0 Application
TPD4E05U06DQA
HOT PLUG 1
UTILITY 2
D2+
1
10
D2-
2
9
3
8
4
7
5
6
UTI_CON
TMDS D2+ 3
D2-
5V Source
D1+
D1+
TMDS_GND 4
D2+
D1-
D1-
TMDS D2- 5
HDMI Connector
TMDS D1+ 6
TPD4E05U06DQA
TMDS_GND 7
TMDS D1- 8
D0+
1
10
D0-
2
9
3
8
4
7
5
6
D0+
D0-
TMDS D0+ 9
TMDS_GND 10
CLK+
TMDS D0- 11
CLK-
CLK+
CLK-
TMDS CLK+ 12
TMDS_GND 13
TPD5S116YFF
TMDS CLK- 14
CEC 15
CEC_CON
DDC/CEC GND 16
SCL_CON
SCL 17
SDA_CON
SDA 18
EN
GND 20
SDA_SYS
5V_SYS
HPD_CON
0.1 µF
SCL_SYS
VCCA
5V_CON
P 5V0 19
HDMI Controller
CEC_SYS
UTI_CON
HPD_SYS
GND
0.1 µF
UTI_CON
Figure 8-1. HDMI 2.0 Schematic
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8.2.1.1 Design Requirements
For this design example, the two TPD4E05U06 devices, and a TPD5S116 are being used in an HDMI 2.0
application. This provides a complete port protection scheme.
Given the HDMI 2.0 application, the parameters listed in Table 8-1 are known.
Table 8-1. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on pins 1, 2, 4, or 5
0 V to 5 V
Operating frequency
3 GHz
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Signal Range on Pin 1, 2, 4, or 5
The TPD4E05U06 has 4 identical protection channels for signal lines. The symmetry of the device provides
flexibility when selecting which of the 4 I/O channels is going to protect which signal lines. Any I/O supports a
signal range of 0 to 5.5 V.
8.2.1.3 Application Curves
14
Figure 8-2. 3.4-Gbps HDMI 1.4 TP1 Eye Diagram
Unpopulated EVM
Figure 8-3. 3.4-Gbps HDMI 1.4 TP1 Eye Diagram
TPD1E05U06
Figure 8-4. 3.4-Gbps HDMI 1.4 TP1 Eye Diagram
TPD4E05U06
Figure 8-5. 3.4-Gbps HDMI 1.4 TP1 Eye Diagram
TPD6E05U06
Figure 8-6. 6-Gbps HDMI 2.0 (TP1) Eye Diagram
Unpopulated EVM
Figure 8-7. 6-Gbps HDMI 2.0 (TP1) Eye Diagram
TPD1E05U06
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Figure 8-8. 6-Gbps HDMI 2.0 (TP1) Eye Diagram
TPD4E05U06
Figure 8-9. 6-Gbps HDMI 2.0 (TP1) Eye Diagram
TPD6E05U06
8.2.2 HDMI 2.0 Application
1
TPD1E05U06
1
TPD1E05U06
1
TPD1E05U06
2
1
GND
2
GND
GND
GND
TPD1E05U06
2
2
D0D1+
Connector
HDMI 2.0 Controller
D0+
D1D2+
D2CLK+
CLK1
TPD1E05U06
1
2
GND
2
1
TPD1E05U06
GND
2
1
TPD1E05U06
GND
GND
TPD1E05U06
2
Figure 8-10. HDMI 2.0 Schematic
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8.2.2.1 Design Requirements
For this design example, the TPD1E05U06 and the TPD5S116 are used to protect the data pairs and control
lines of the HDMI 2.0 connection. This provides full HDMI 2.0 port protection.
Given the HDMI 2.0 application, the following parameters in Table 8-2 are known.
Table 8-2. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on data lines
0 V to 5 V
Operating frequency
3 GHz
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Signal Range
The TPD1E05U06 has 1 protection channel for signal lines, supporting a signal range of 0 V to 5.5 V.
8.2.2.2.2 Operating Frequency
The TPD1E05U06 has 0.42 pF of capacitance, which supports HDMI 2.0 data rates.
8.2.2.3 Application Curves
Refer to the Section 8.2.1.3 section.
9 Power Supply Recommendations
This device is a passive ESD protection device and there is no need to power it. Care must be taken to make
sure that the maximum voltage specifications for each line are not violated.
16
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10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
10.2.1 TPD4E05U06 Layout Example
This application is typical of an HDMI 1.4 layout.
Clk+
Clk-
D0+
D0-
D1+
D1-
D2+
D2-
VIA to GND Plane
D0+
D1-
D1+
GND
NC
NC
NC
NC
GND
NC
D0-
GND
D0+
GND
NC
NC
D1+
NC
D0-
D1-
Figure 10-1. TPD4E05U06 Layout
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10.2.2 TPD1E05U06 Layout Example
This application is typical of an HDMI 2.0 layout.
Clk+
Clk-
GND
GND
I/O
I/O
D0+
D0GND
GND
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
D2+
D2-
D1+
D1-
VIA to GND Plane
Figure 10-2. TPD1E05U06 Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Reading and Understanding an ESD Protection data sheet
• Texas Instruments, ESD Layout Guide application reports
• Texas Instruments, TPD6E05U06RVZ EVM user's guide
• Texas Instruments, Picking ESD Diodes for Ultra High-Speed Data Lines application reports
• Texas Instruments, ESD PROTECTION DIODES EVM user's guide
• Texas Instruments, TPD1E05U06DPY EVM user's guide
• Texas Instruments, TPD4E05U06DQA EVM user's guide
• Texas Instruments, Generic ESD Evaluation Module user's guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
PCI-express® and PCI-Express® are registered trademarks of PCI-SIG .
V-by-One® is a registered trademark of Thine Electronics, Inc.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD1E05U06DPYR
ACTIVE
X1SON
DPY
2
10000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(BK, C1, C6)
C2
TPD1E05U06DPYT
ACTIVE
X1SON
DPY
2
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(BK, C1, C6)
C2
TPD1E05U06DYAR
ACTIVE
SOT-5X3
DYA
2
3000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
1KS
TPD4E05U06DQAR
ACTIVE
USON
DQA
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(BLG, BRG)
BRY
TPD6E05U06RVZR
ACTIVE
USON
RVZ
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(BV, BVY)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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