TPD8E003DQDR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPD8E003 SLLSE38B – JUNE 2010 – REVISED MARCH 2016 TPD8E003 8-Channel ESD Protection Diode for Keypad and GPIO 1 Features 3 Description • The TPD8E003 device is a unidirectional Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode array. The TPD8E003 is rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard (Level 4). This device provides 8 channels of ESD protection in a space-saving WSON package. Typical applications for the TPD8E003 include Keypad, GPIO, resistive touchscreen, and low-speed memory interfaces. Also, see the TPD2E2U06 and TPD4E05U06 for 2- and 4-channel ESD protection solutions, respectively. 1 • • • • • • IEC 61000-4-2 Level 4 ESD Protection – ±12-kV Contact Discharge – ±15-kV Air-Gap Discharge IEC 61000-4-5 Surge Protection – 3.5-A (8/20 µs) IO Capacitance: 9 pF (Typical) DC Breakdown Voltage: 6 V (Minimum) Low Leakage Current: 100 nA (Maximum) Industrial Temperature Range: –40ºC to 85ºC Space-Saving, Ultra-Thin, WSON Package Device Information(1) 2 Applications • • End Equipment – Laptops and Desktops – IP Phones Interfaces – Keypads – GPIO Headers – Touchscreens – Low-Speed Memory Interfaces PART NUMBER TPD8E003 PACKAGE WSON (8) BODY SIZE (NOM) 1.70 mm × 1.35 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Circuit Schematic 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD8E003 SLLSE38B – JUNE 2010 – REVISED MARCH 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 4 5 5 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. ESD Ratings – Surge Protection............................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 6 7.1 Overview ................................................................... 6 7.2 Functional Block Diagram ......................................... 6 7.3 Feature Description................................................... 6 7.4 Device Functional Modes.......................................... 6 8 Application and Implementation .......................... 7 8.1 Application Information.............................................. 7 8.2 Typical Application ................................................... 7 9 Power Supply Recommendations........................ 9 10 Layout..................................................................... 9 10.1 Layout Guidelines ................................................... 9 10.2 Layout Example ...................................................... 9 11 Device and Documentation Support ................. 11 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 11 11 11 11 12 Mechanical, Packaging, and Orderable Information ........................................................... 11 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September 2010) to Revision B Page • Added ESD Ratings tables, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1 2 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPD8E003 TPD8E003 www.ti.com SLLSE38B – JUNE 2010 – REVISED MARCH 2016 5 Pin Configuration and Functions DQD Package 8-Pin WSON Top View IO1 1 IO2 2 8 IO8 7 IO7 GND IO3 3 6 IO6 IO4 4 5 IO5 Pin Functions PIN NO. NAME TYPE (1) DESCRIPTION 1 IO1 I/O ESD protected channel 2 IO2 I/O ESD protected channel 3 IO3 I/O ESD protected channel 4 IO4 I/O ESD protected channel 5 IO5 I/O ESD protected channel 6 IO6 I/O ESD protected channel 7 IO7 I/O ESD protected channel 8 IO8 I/O ESD protected channel GND GND G Connect to ground (1) G = Ground, I = Input, O = Output Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPD8E003 3 TPD8E003 SLLSE38B – JUNE 2010 – REVISED MARCH 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT 6 V Peak pulse power (tp = 8/20 µs) 55 W Peak pulse current (tp = 8/20 µs) 3.5 A IO voltage tolerance (IO pins) TA Operating free-air temperature –40 85 ºC Tstg Storage temperature –55 155 ºC (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings – Surge Protection VALUE V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±12000 IEC 61000-4-2 air-gap discharge ±15000 UNIT V 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIO Input pin voltage TA Operating free-air temperature NOM MAX UNIT 0 5.5 V –40 85 °C 6.5 Thermal Information TPD8E003 THERMAL METRIC (1) DQD (WSON) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 98.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 110.3 °C/W RθJB Junction-to-board thermal resistance 42.5 °C/W ψJT Junction-to-top characterization parameter 9.2 °C/W ψJB Junction-to-board characterization parameter 42.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 22.0 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPD8E003 TPD8E003 www.ti.com SLLSE38B – JUNE 2010 – REVISED MARCH 2016 6.6 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT Vclamp Clamp voltage IIO = 2 A, IO pin-to-ground 10 V II Leakage current IO pin-to-ground 0.1 μA CIO IO capacitance VIO = 2.5 V, IO pins 12 pF ΔCIO Differential line capacitance VIO = 2.5 V, between IO pins VBR Break-down voltage IIO = 1 mA Rdyn Dynamic resistance IIO = 1 A, between IO pin and ground 7 9 0.1 pF 1 Ω 6 V 6.7 Typical Characteristics Figure 1. IO Capacitance vs IO Voltage Figure 2. DC Characteristics Figure 3. Peak Pulse Waveforms Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPD8E003 5 TPD8E003 SLLSE38B – JUNE 2010 – REVISED MARCH 2016 www.ti.com 7 Detailed Description 7.1 Overview The TPD8E003 is a unidirectional TVS-based, ESD protection diode array. The TPD8E003 is rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard (Level 4). This device provides 8 channels of ESD protection in a space-saving WSON package. 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 IEC 61000-4-2 ESD Protection The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air gap. An ESD/surge clamp diverts the current to ground. 7.3.2 IEC 61000-4-5 Surge Protection The I/O pins can withstand surge events up to 3.5 A and 55 W (8/20 µs waveform). An ESD/surge clamp diverts this current to ground. 7.3.3 IO Capacitance The capacitance between each I/O pin-to-ground is 9 pF (typical) and 12 pF (maximum). 7.3.4 DC Breakdown Voltage The DC breakdown voltage of each I/O pin is a minimum of 6 V. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of 5.5 V. 7.3.5 Low Leakage Current The I/O pins feature an low leakage current of 100 nA (maximum) with a bias of 2.5 V. 7.3.6 Industrial Temperature Range This device features an industrial operating range of –40°C to 85°C. 7.3.7 Space-Saving Package This device features a space-saving WSON package that puts many channels of ESD in a small form factor. 7.4 Device Functional Modes TPD8E003 is a passive integrated circuit that triggers when voltages are above VBR or below the lower diodes Vf (–0.6 V). During ESD events, voltages as high as ±15 kV (air) can be directed to ground through the internal diode network. When the voltages on the protected line fall below the trigger levels of TPD8E003 (usually within 10s of nano-seconds) the device reverts to passive. 6 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPD8E003 TPD8E003 www.ti.com SLLSE38B – JUNE 2010 – REVISED MARCH 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPD8E003 offers eight ESD clamp circuits in a space-saving DQD package. When placed near the connector, the TPD8E003 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD8E003 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. 8.2 Typical Application IO1 IO3 Microcontroller GPIO Header IO2 IO4 IO5 IO6 IO7 IO8 1 8 2 7 TPD8E003 3 6 4 5 GND GND Figure 4. GPIO Header Application 8.2.1 Design Requirements For this design example, one TPD8E003 is used to protect an 8-pin GPIO header. Given the example application, the parameters listed in Table 1 are known. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPD8E003 7 TPD8E003 SLLSE38B – JUNE 2010 – REVISED MARCH 2016 www.ti.com Table 1. Design Parameters PARAMETER VALUE Signal Range on Protected Lines 0 V to 5 V Required Level of IEC ESD Protection ±8kV Contact, ±15kV Air Gap 8.2.2 Detailed Design Procedure To begin the design process, some parameters must be decided upon; the designer must know the following: • Voltage range of the signal on all protected lines • Required ESD protection needed 8.2.2.1 Signal Range The TPD8E003 supports signal ranges between 0 V and 5.5 V, which supports the GPIO application. 8.2.2.2 Required ESD Protection The TPD8E003 is rated to withstand up to ±12-kV contact and ±15-kV air gap IEC ESD. This meets the IEC ESD design target with room to spare. 8.2.3 Application Curves Figure 5. IEC ESD Clamping Waveforms 8-kV Contact 8 Submit Documentation Feedback Figure 6. IEC ESD Clamping Waveforms –8-kV Contact Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPD8E003 TPD8E003 www.ti.com SLLSE38B – JUNE 2010 – REVISED MARCH 2016 9 Power Supply Recommendations This device is a passive ESD protection device and there is no need to power it. Take care making sure that the maximum voltage specifications for each line are not violated. 10 Layout 10.1 Layout Guidelines For proper operation of the ESD clamps, both during normal function and ESD events, the following layout and design guidelines must be followed: • Place the TPD8E003 solution close to the connector. This allows the TPD8E003 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board. • TI recommends employing two signal layers in the printed-circuit board (PCB) to route through the eight ESD clamp terminals of the TPD8E003. • Ensure that there is proper metallization for the GND vertical interconnect access (VIA). During an ESD event, the in-rush current flows to the system GND plane through the GND VIA. Having a low-impedance path allows the current to flow quickly to GND, effectively building a robust, system-level ESD immunity. • Place the VIA under the DQD pad in locations that offer maximum flexibility in board routing. • One common set of guidelines (not restricted to all cases): – Trace width: 4 mm – VIA diameter: 6 mm – DQD package pad dimensions: 8 mm × 12 mm 10.2 Layout Example Figure 7. Board Layout With the TPD8E003DQDR Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPD8E003 9 TPD8E003 SLLSE38B – JUNE 2010 – REVISED MARCH 2016 www.ti.com Layout Example (continued) Figure 8. Top and Bottom Layer Board Layout With the TPD8E003DQDR 10 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPD8E003 TPD8E003 www.ti.com SLLSE38B – JUNE 2010 – REVISED MARCH 2016 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPD8E003 11 PACKAGE OPTION ADDENDUM www.ti.com 13-May-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPD8E003DQDR ACTIVE WSON DQD 8 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 (65S, 65U) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of