TPL5100DGST

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPL5100 SNAS629C – JULY 2013 – REVISED DECEMBER 2014 TPL5100 Nano-Power Programmable Timer With MOS Driver 1 Features 3 Description • • • The TPL5100 is a long-term timer IC optimized for low-power applications. The TPL5100 can replace a microcontroller's internal timer, allowing the microcontroller to stay completely off instead of running a timer, providing a total power consumption reduction of 60 to 80%.The TPL5100 is designed for use in power cycled applications and provides selectable timing from 16 seconds to 1024 seconds. The TPL5100 can also monitor a battery management IC via a power-good digital input and power on the microcontroller only when a good supply voltage is present. The device is packaged in a 10-pin VSSOP package. 1 Supply Voltage from 1.8 V to 5.0 V Selectable Timer Intervals, 16 to 1024 seconds Current Consumption 30 nA (typical, at 2.5 V) 2 Applications • • • • • • • • Battery-Powered Systems Energy Harvesting Systems Remote Data-Logger Sensor Node Power-Gating Applications Building Automation Low-Power Wireless Consumer Electronics Device Information(1) PART NUMBER TPL5100 PACKAGE BODY SIZE (NOM) VSSOP (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Application Schematic TPL5100 VOUT VBAT_OK VIN D0 µC PGOOD VDD D1 POWER MANAGEMENT GND D2 MOS_DRV VDD TCAL GPIO GND DONE GPIO GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPL5100 SNAS629C – JULY 2013 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Ratings ........................... Thermal Information ................................................. Electrical Characteristics........................................... Timing Requirements TCAL, MOS_DRV, DONE, PGOOD...................................................................... 6.7 Typical Characteristics .............................................. 7 6 7 Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 8 7.4 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application ................................................. 11 9 Power Supply Recommendations...................... 13 10 Layout................................................................... 13 10.1 Layout Guidelines ................................................. 13 10.2 Layout Example .................................................... 13 11 Device and Documentation Support ................. 14 11.1 Trademarks ........................................................... 14 11.2 Electrostatic Discharge Caution ............................ 14 11.3 Glossary ................................................................ 14 12 Mechanical, Packaging, and Orderable Information ........................................................... 14 4 Revision History Changes from Revision B (August 2013) to Revision C Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 3 • Removed TA value. ................................................................................................................................................................ 4 2 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPL5100 TPL5100 www.ti.com SNAS629C – JULY 2013 – REVISED DECEMBER 2014 5 Pin Configuration and Functions VSSOP 10 Pins Top View TPL5100 D0 PGOOD D1 DNC D2 MOS_DRV VDD TCAL GND DONE Pin Functions PIN NAME NO. I/O DESCRIPTION APPLICATION INFORMATION D0 1 I Logic Input to set period delay (tDP) Connect to GND (low logic value) or to VDD (high logic value) D1 2 I Logic Input to set period delay (tDP) Connect to GND (low logic value) or to VDD (high logic value) D2 3 I Logic Input to set period delay (tDP) Connect to GND (low logic value) or to VDD (high logic value) VDD 4 P Supply voltage GND 5 G Ground DONE 6 I Logic input for Watchdog functionality TCAL 7 O Short duration pulse output for estimation of TPL5100 timer delay. MOS_DRV 8 O Drives external MOSFET to power cycle the remaining system. DNC 9 – Do Not Connect PGOOD 10 I Digital power good input Leave this pin floating Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPL5100 3 TPL5100 SNAS629C – JULY 2013 – REVISED DECEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) MIN MAX UNIT Supply Voltage (VDD-GND) -0.3 6 V Input voltage -0.3 VDD+0.3 V Voltage between any two pins (3) -0.3 VDD+0.3 V Input Current on any pin -5 Junction Temperature, TJ (4) Storage temperature, Tstg (1) (2) (3) (4) -65 5 mA 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to ground unless otherwise noted. When the input voltage (VIN) at any pin exceeds the power supply (VDD), the current on that pin must not exceed 5 mA and the voltage must also not exceed 6.0 V. The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Ratings MIN MAX Supply Voltage (VDD-GND) 1.8 5.0 UNIT V Temperature Range -40 105 °C 6.4 Thermal Information TPL5100 THERMAL METRIC (1) VSSOP UNIT 10 PINS RθJA (1) 4 Junction-to-ambient thermal resistance 196.8 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPL5100 TPL5100 www.ti.com SNAS629C – JULY 2013 – REVISED DECEMBER 2014 6.5 Electrical Characteristics (1) Specifications are for TA =TJ = 25°C, VDD-GND=2.5 V, unless otherwise stated. PARAMETER TYP (3) MAX (2) PGOOD=VDD 30 50 PGOOD=GND 12 TEST CONDITIONS MIN (2) UNIT POWER SUPPLY IVDD Supply current (4) nA nA TIMER tDP Timer Delay Period 16, 32, 64, 100, 128, 256, 512, 1024 Timer Delay Period drift over life time (5) 0.06 % Timer Delay Period drift over temperature tCAL 400 Calibration pulse width tDP to tCAL matching error tDONE DONE Pulse width (6) tMOS_DRV MOS_DRV Pulse width 14.063 (6) s 15.625 VDD