TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
Dual 12 V Protection and Blocking Controller
Check for Samples: TPS2456
FEATURES
DESCRIPTION
•
•
•
•
•
•
The TPS2456 is a dual, 12 V, channel protection
(hotswap) and blocking (ORing) controller that
provides inrush control, current limiting, overload
protection, and reverse current blocking. The current
sense topology provides both accurate current limits
and independent setting of current limit and fast trip
thresholds.
1
•
Dual 12 V Protection and Blocking Control
Independent Current Limit and Fast Trip
Blocking Permits ORing of Multiple Inputs
Power Good and Fault Outputs
Analog Current Monitor Outputs
-40°C to 125°C Operating Junction
Temperature
QFN36 Package
The ORing control uses an external MOSFET to
block reverse current when an input is shorted.
Systems with closely matched supply voltages and
feed networks can supply current from both supplies
simultaneously.
APPLICATIONS
•
•
•
•
•
ATCA Carrier Boards
AdvancedMC™ Slots
Blade Servers
Base Stations
Configurable for
– 1 Source, 2 Loads
– 2 Sources, 1 Load
– 2 Sources, 2 Loads
The MONx output provides an accurate analog
indication of load current.
The protection circuits may be used without blocking,
and the blocking may be used without protection.
Internal connections prevent implementation of these
as four fully-independent functions.
INA
RSENSEA
M2A
RG1A
RG2A
GAT1A
GAT2A
M1A
SENMA
SETA
INA
SENPA
RSETA
ENA
ORENA
CTA
OUTA
CINA
0.1mF
TPS2456
PGA
FLTA
36 PIN QFN
MONA
CTA
33nF
GND
VINT
GND
CINT
0.1mF
COMMON
CIRCUITRY
GND
GND
GND
GND
GND
GND
ENB
ORENB
MONB
RMON
CINB
0.1mF
RSETB
RG1B
M1B
INB
OUTB
GAT1B
GAT2B
SENMB
PGB
FLTB
SETB
CTB
33nF
INB
SENPB
CTB
RG2B
M2B
RSENSEB
Figure 1. Two Sources, One Load Application Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCT INFORMATION (1)
(1)
DEVICE
TEMPERATURE
PACKAGE
MARKING
TPS2456RHH
–40°C to 85°C
QFN36 (6mm × 6mm)
TPS2456
For package and ordering information see the Package Option Addendum at the end of this document or see the TI Web site at
www.ti.com.
THERMAL INFORMATION
TPS2456
THERMAL METRIC
(1)
RHH
UNITS
36 PINS
Junction-to-ambient thermal resistance (2)
θJA
32
(3)
θJC(top)
Junction-to-case(top) thermal resistance
θJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
θJC(bottom)
23
(4)
11
(5)
Junction-to-case(bottom) thermal resistance
0.5
(6)
°C/W
10
(7)
2.1
SPACER
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
Spacer
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
ABSOLUTE MAXIMUM RATINGS (1)
Over recommended junction temperature range and all voltages referenced to GND, unless otherwise noted.
PINS OR PIN GROUPS
VALUE
UNITS
GAT1x, GAT2x
–0.3 to 30
V
INx, OUTx, SENPx, SENMx, SETx, ENx, FLTx, PGx, ORENx
–0.3 to 20
V
CTx, MONx
–0.3 to 5
V
5
mA
FLTx, PGx current sinking
MONx current sourcing
VINT current
ESD
Human Body Model
Charged Device Model
Junction Temperature
(1)
2
5
mA
–1 to 1
mA
2
kV
0.5
kV
Internally Limited
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device under any conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
RECOMMENDED OPERATING CONDITIONS
Over recommended junction temperature range and all voltages referenced to GND, unless otherwise noted.
MIN
VINx
TYP
8.5
IMONx
GAT1x, GAT2x board leakage current (1)
1
Operating junction temperature range, TJ
UNIT
12
15
V
100
1000
µA
1
µA
100
250
nF
125
°C
–1
VINT bypass capacitance
(1)
MAX
–40
This condition applies to the PCB and is not a limit on the TPS2456.
ELECTRICAL CHARACTERISTICS
Common conditions (unless otherwise noted) are: INA = INB = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB =
12 V, ENA = ENB = ORENA = ORENB = 3 V, CTA = CTB = GND, RMONA = RMONB = 6.81kΩ, all other pins open,
–40°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.25
1.35
1.45
20
50
80
mV
5
8
15
µA
6
15
µA
20
µs
0.14
0.25
V
1
µA
10.5
10.8
Enable Input – ENx, ORENx
Threshold voltage
VINx ↑
Hysteresis
Pullup current
ENx = ORENx = 0 V, current sourcing
Input bias current
ENx = ORENx = 17 V, current sinking
Turn off time (1)
ENx deasserts to VOUTx < 1 V, COUT = 0 µF, QGAT1x = 33 nF
(2)
V
Power Good Output – PGx
Output low voltage
IPGx = 2 mA sinking
Leakage current
PGx = 17 V (sinking)
Threshold voltage
PGx, VOUTx ↓
Hysteresis
PGx, VOUTx ↑
Deglitch time
PGx falling
10.2
130 (2)
50
V
mV
100
150
µs
0.14
0.25
V
1
µA
2.8
V
µA
Fault Output – FLTx
Output low voltage
IFLTx = 2 mA sinking
Leakage current
VFLTx = 17 V (sinking)
Bias Supply – VINT
Output voltage
0 < IVINT < 50 µA
2
2.3
Fault Timer – CTx
Sourcing current
VCTx = 0 V, during fault
Upper threshold voltage
7
10
13
1.30
1.35
1.40
Discharge pulldown (2)
Timer start threshold
V
Ω
200
(VGAT1x – VINx) when timer starts, with VGAT1x falling due to over
current
5
6
7
V
Channel Current Monitor – MONx
Input referred offset
10.8 V ≤ VSENMx ≤ 13.2 V, VSENPx = VSENMx + 50 mV,
measure VSETx – VSENMx
–1.5
MONx threshold
VGAT1x = 15 V
0.66
Leakage current
VSETx = (VSENMx – 10 mV)
(1)
(2)
1.5
0.675
mV
0.69
V
1
µA
Tested with HAT2156 MOSFET.
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
3
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Common conditions (unless otherwise noted) are: INA = INB = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB =
12 V, ENA = ENB = ORENA = ORENB = 3 V, CTA = CTB = GND, RMONA = RMONB = 6.81kΩ, all other pins open,
–40°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current limit threshold
RSETx = 500 Ω, RMONx = 6800 Ω, measure VSENPx – VSENMx when
VGAT1x = 15 V
47.5
50
52.5
mV
Sink current in current
limit
VMONx = 1 V, VGAT1x = 12 V, measure IGAT1x
20
40
µA
Fast trip threshold
Measure VSENPx – VSENMx
80
100
120
mV
200
300
ns
Current limit
(VSENP – VSENM): 0 V → 120 mV, tP50-50
Fast turn-off delay
(3)
Channel UVLO
UVLO
SENPx rising
8.1
8.5
8.9
V
UVLO hysteresis
SENPx falling
0.44
0.5
0.59
V
10
20
mV
Blocking Comparator
Turn-on threshold
Measure (VSENPx – VOUTx)
5
Turn-off threshold
Measure (VSENPx – VOUTx)
–6
Turn-off delay
20 mV overdrive, tp50-50
–3
0
mV
200
300
ns
21.5
23
24.5
V
40
µA
Gate Drivers – GAT1x, GAT2x
Output voltage
VINx = VOUTx = 10 V
Sourcing current
VINx = VOUTx = 10 V, VGAT1x = VGAT2x = 17 V
20
30
Fast turnoff, VGAT1x = VGAT2x = 14 V, pulsed measurement
0.5
1
6
14
20
mA
14
20
26
kΩ
5
10
15
µs
1
µs
0.25
ms
Sinking current
Sustained, 4 V ≤ (VGAT1x = VGAT2x) ≤ 25 V
Pulldown resistance
In thermal shutdown
Fast turn-off duration
A
(4)
Disable delay
ENx pin to VGATx1 and VGAT2x, tP50-90
Startup Time
INx rising to GAT1x or GAT2x sourcing current (ENx and ORENx
high)
Supply Current (IINx+ ISENPx+ ISENMx+ ISETx+ IOUTx)
Both channels enabled
3.1
4
mA
Both channels disabled
2
2.8
mA
Thermal Shutdown
Shutdown temperature
TJ rising
140
Hysteresis
(3)
(4)
(5)
150
°C
(5)
°C
10
See Figure 3 for timing definition.
See Figure 2 for timing definition.
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
VGAT1x,
VGAT2x
VENx
VGAT1x,
VGAT2x
90%
VSENPx VSENMx
VT
50%
50%
time
time
tP50-90
tP50-50
Figure 2. tP50-90Definition
4
Figure 3. tP50-50 Definition
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
FUNCTIONAL BLOCK DIAGRAM
M1
RSENSEx
12 V Channel
Input Supply
RSETx
SENPx
SETx
RG1x
SENMx
VCP
~25 V
GAT1x
Fast
Trip enx
100 mV
Charge
Pump
M2
RG2x
OUTx
GAT2x
VCP
prgx
blx
INx
A1
CTx
Control
& Fault
FLTx
VINT
CTx
8.5 V
/8V
200 kW
ENx
UVLO
6V
por
675 mV
RMONx
A2
INx
Current
Limit
Blocking prgx
Control
R Q
MONx
10 mV
OUTx
3 mV
FLT Tmr.
Gate Mon.
60 mA
blx
PGx
OUTx
100 ms
10.50 V /
10.63 V
S Q
Output
PG
ORENx
VINT
200 kW
Figure 4. TPS2456 Channel (2 channels per device)
VINT
VINT
INA
en
por
CVINT
2.2V
INB
+
OUTA
PREREG
Pwr On
Reset
Control
Logic
OUTB
GND
Figure 5. Common Control Circuits
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
5
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
PIN FUNCTIONS
PIN
TYPE
A/B (1)
1
I
A
Input voltage sense – connect to input supply. Connect to the source side of RSENSEA.
SETA
2
I
A
Connect RSETA from the input supply to SETA to program the current limit in conjunction with RSENSEA
and RMONA (see the DETAILED PIN DESCRIPTIONS).
SENMA
3
I
A
Connect this pin to the load side of the RSENSEA. The fast-trip threshold equals 100 mV / RSENSEA.
VINT
4
I/O
–
Connect a bypass capacitor (e.g., 0.01µF) to GND for this internal supply.
MONA
5
I/O
A
Connect RMONA from MONA to GND to set the current limit in conjunction with RSENSEA and RSETA
(see the DETAILED PIN DESCRIPTIONS).
ORENA
6
I
A
Blocking transistor enable, active high.
GND
7
GND
–
Connect pin to ground.
GND
8
GND
–
Connect pin to ground
MONB
9
I/O
B
Connect RMONB from MONB to GND to set the current limit in conjunction with RSENSEB and RSETB
(see the DETAILED PIN DESCRIPTIONS).
CTB
10
I/O
B
Connect CTB from CTB to GND to set the fault timer period (see text).
GAT2B
11
O
B
Blocking transistor gate drive.
OUTB
12
I/O
B
Output voltage monitor and bias input.
GND
13
GND
B
Connect pin to ground.
ORENB
14
I
B
Blocking transistor enable, active high.
GAT1B
15
O
B
Protection transistor gate drive.
SENMB
16
I
B
Connect this pin to the load side of the RSENSEB. The fast-trip threshold equals 100 mV / RSENSEB.
SETB
17
I
B
Connect RSETB from input supply to SETB to program the current limit program the current limit in
conjunction with RSENSEB and RMONB (see the DETAILED PIN DESCRIPTIONS).
SENPB
18
I
B
Input voltage sense – connect to input supply. Connect to the source side of RSENSEB.
INB
19
PWR
B
Control power input – connect to input supply.
–
20
–
–
No connection.
FLTB
21
O
B
Fault output, active low, asserted when B fault timer runs out.
PGB
22
O
B
Power good output, active low, asserts when VOUTB > 10.63 V.
GND
23
GND
–
Connect pin to ground.
GND
24
GND
–
Connect pin to ground.
GND
25
GND
–
Connect pin to ground.
PGA
26
O
A
Power good output, active low, asserts when VOUTA > 10.63 V.
FLTA
27
O
A
Fault output, active low, asserted when A fault timer runs out.
GND
28
GND
–
Connect pin to ground.
ENB
29
I
B
Enable, (active high).
GAT1A
30
O
A
Protection transistor gate drive.
ENA
31
I
A
Enable, (active high).
GND
32
GND
A
Connect pin to ground.
OUTA
33
I/O
A
Output voltage monitor and bias input.
GAT2A
34
O
A
Blocking transistor gate drive.
CTA
35
I/O
A
Connect CTA from CTA to GND to set the fault timer period (see the DETAILED PIN DESCRIPTIONS).
INA
36
PWR
A
Control power input – connect to input supply.
PAD
–
–
–
Solder pad to GND.
NAME
NO.
SENPA
(1)
6
DESCRIPTION
Specifies whether this pin is part of A channel, B channel, or is common to both (-).
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
INA
CTA
GAT2A
OUTA
GND
ENA
GAT1A
ENB
GND
DEVICE PINOUT
(TOP VIEW)
36
35
34
33
32
31
30
29
28
SENPA 1
27
FLTA
SETA 2
26
PGA
SENMA 3
25
GND
VINT 4
24
GND
23
GND
ORENA 6
22
PGB
GND 7
21
FLTB
20
NC
19
INB
TPS2456
MONA 5
GND 8
PAD - Backside
10
11
12
13
14
15
16
17
18
CTB
GAT2B
OUTB
GND
ORENB
GAT1B
SENMB
SETB
SENPB
MONB 9
DETAILED PIN DESCRIPTIONS
The TPS2456 supports two 12-V protection (hotswap) and blocking (ORing) channels designated A and B.
Where there are separate pins for both A and B channels, the pin name is shown with an x in place of A or B to
describe the function. For example, references to CTx would be the same as CTA or CTB. Programming
components are referred to in the text by reference designators used in Figure 1.
CTx – A capacitor from CTx to GND sets the period VGAT1x can be low ( VGAT1x < VINx + 6 V) before it shuts the
channel down and declares a fault. VGAT1x will be low during startup and current limit. Low VGAT1x causes this pin
to source 10 µA into the external capacitor (CTx). When VCTx reaches 1.35 V, the TPS2456 shuts the channel off
by pulling the GAT1x and GAT2x pins low, declares a fault by pulling the FLTx pin low, and latching off. A 200 Ω
internal pull down keeps this pin low during normal operation when not in current limit. It is normal to see a
sawtooth on this pin when the channel is latched off by a fault.
ENx – Active high enable input. A low on ENx turns off the channel by pulling GAT1x and GAT2x low. An internal
200 kΩ resistor pulls this pin up to VINT. ENx may be left floating when the channel is to be permanently
enabled.
FLTx – Active low open-drain output indicating that VGAT1x has been low ( VGAT1x < VINx + 6 V) long enough trip
the fault timer and shut the channel down. FLTx may be left open if not used.
GAT1x – Gate drive output for the protection MOSFET. This pin sources 30 µA to turn the MOSFET on. An
internal clamp prevents this pin from rising more than 14.5 V above INx.
Up to 30µA may be sunk while current limit is active. A fast trip (overcurrent), disable (from ENx), or fault timeout
enables a 10 µs, 1 A, discharge current and 14 mA pulldown. The pulldown will be released after 10 µs if only a
fast trip had occurred.
Setting ENx low holds GAT1x low. GAT1x may be left open if not used.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
7
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
GAT2x – Gate drive output for the blocking MOSFET. The blocking MOSFET prevents reverse channel current
when OUTx is higher than INx. This is often used when two input sources are ORed together. GAT2x sources 30
µA to turn the MOSFET on. GAT2x is low when ENx is low, ORENx is low, FLTx is low, a fast trip is active, or a
voltage reversal has occurred. A 10 µs, 1 A, discharge and 14 mA pulldown are applied when this occurs.
An internal clamp prevents this pin from rising more than 14.5 V above OUTx. Setting the ORENx or ENx pins
low holds the GAT2x pin low.
GAT2x may be left open if not used.
INx - Supply pin for the internal circuitry. A small bypass capacitor (e.g. 0.1 µF) is recommended for this pin.
MONx – A resistor connected from this pin to ground forms part of the current limit programming. As the current
delivered to the load increases, so does the voltage on this pin. The current-limit circuit controls GAT1x to limit
channel current at a VMONx of 675 mV. The current limit circuit is inactive for lower values of VMONx.
Equation 1 through Equation 4 define current limit and fast trip values using RMONx, RSENSEx, and RSETx. VMONx
can by sampled with an external A/D converter to measure the channel current.
ORENx – Active high input. Pulling this pin low disables the blocking function by pulling the GAT2x pin low.
Pulling this pin high (or allowing it to float high) allows the blocking function to operate normally. The M2x internal
diode may carry the load current when GAT2x is low and VINX > VOUTX.
An internal 200 kΩ resistor pulls this pin to VINT. ORENx may be left open when blocking is not used, or does
not require active control.
OUTx – Senses the output voltage of the channel. This voltage is used by the biasing, blocking, and power good
circuits.
PGx – Active low open-drain output. A low on PGx indicates that VOUTx has exceeded 10.63 V, and has not
fallen below 10.50 V. These thresholds are internally set, and modifying the OUTx connection may effect
blocking operation.
SENMx – Senses the voltage on the load side of RSENSEx for use by the fast trip and current limiting circuits.
SENPx – Senses the voltage on the source side of RSENSEx for use by the fast trip, UVLO and blocking circuits.
The fast trip overcurrent shutdown is activated at a VSENP-SENM of 0.1 V. UVLO trips when SENPx goes below 8.5
V for more than 440 ns (nominal), 295 ns (worst case).
SETx – A resistor connected from this pin to SENPx sets the current limit level in conjunction with RSENSEx and
RMONx as described in Equation 1 through Equation 4.
VINT – This pin connects to the internal 2.35 V rail. A 0.1 µF capacitor must be connected from this pin to
ground. VINT is not designed to be a general-purpose bias rail.
8
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs TEMPERATURE
SUPPLY CURRENT vs INPUT VOLTAGE
2.45
2.4
TJ = 25°C
2.4
Supply Current - mA
Supply Current - mA
2.3
2.2
2.35
2.3
2.25
2.2
2.1
2.15
2
-40
-20
0
20
40
60
80
100
TJ - Junction Temperature - °C
2.1
10
120
10.5
Figure 6.
11 11.5
12 12.5
13
VINx - Input Voltage - V
13.5
14
Figure 7.
CURRENT LIMIT THRESHOLD vs TEMPERATURE
50.8
BLOCKING TURNOFF THRESHOLD vs TEMPERATURE
-2.80
RSETx = 500W
-2.85
(VINx - VOUTx) - mV
(VSENPx - VSENMx) - mV
RMONx = 6800W
50.6
50.4
-2.90
-2.95
-3.00
-3.05
-3.10
50.2
-40
-20
0
20
40
60
80
100
TJ - Junction Temperature - °C
120
-3.15
-40
Figure 8.
-20
0
20
40
60
80
100
TJ - Junction Temperature - °C
120
Figure 9.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
9
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
BLOCKING TURN ON THRESHOLD vs TEMPERATURE
12
(VINx -VOUTx) - mV
11.5
11
10.5
10
9.5
9
-40
-20
0
20
40
60
80
100
TJ - Junction Temperature - °C
120
Figure 10.
GAT1x,
10 V/div
GAT1x,
10 V/div
OUTx starting up into 1.8 W (6.7 A, 80 W)
Output capacitance is 830 mF
OUTx starting up into 500 W (24 mA)
Output capacitance is 830 mF
675 mV
675 mV
580 mV
MONx,
0.5 V/div
MONx,
0.5 V/div
40 mV
OUTx,
10 V/div
OUTx,
10 V/div
Time - 1 ms/div
Time - 1 ms/div
Figure 11. Startup into 500 Ω, 830 µF Load
10
Figure 12. Startup into 80 Watt, 830 µF Load
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
TYPICAL CHARACTERISTICS (continued)
GAT1x,
10 V/div
GAT1x,
10 V/div
OUTx shorted while driving 6.7 A load
Output capacitance is 47 mF
675 mV
620 mV
MONx,
1 V/div
OUTx shorted while driving 6.7 A load
Output capacitance is 47 mF
MONx,
1 V/div
620 mV
OUTx,
10 V/div
OUTx,
10 V/div
Time - 2 ms/div
Time - 1 ms/div
Figure 13. Short Circuit Under Full Load (6.7 A) Wide
Figure 14. Short Circuit Under Full Load (6.7 A) Zoom View
OUTx overloaded while supplying 6.7 A
GAT1x,
10 V/div
2.9 V
GAT1x,
2 V/div
970 mV
675 mV
675 mV
OUTx starting into short circuit
MONx,
0.5 V/div
MONx,
0.5 V/div
OUTx,
10 V/div
OUTx,
20 mV/div
Time - 1 ms/div
Time - 1 ms/div
Figure 15. Startup into Short Circuit
Figure 16. Overloaded while Supplying 6.7 A
SYSTEM OPERATION
INTRODUCTION
The TPS2456 controls two 12-V channels, or power paths. The channels can draw from a single common
supply, or from two independent supplies. The following sections describe the TPS2456 operation and provide
guidance for designing systems around this device.
CONTROL LOGIC AND POWER-ON RESET
The TPS2456 circuitry draws bias power from any of the INx or OUTx pins through an internal preregulator that
generates VINT. A bypass capacitor from VINT to ground provides decoupling and output filtering for the internal
circuits. Bias supply ORing allows the internal circuitry to function regardless of which channels receive power or
are in a faulted state. The four external MOSFET drive pins (GAT1A, GAT1B, GAT2A, and GAT2B) are held low
during startup to ensure that the channels remain off. When the voltage on the internal VINT rail exceeds
approximately 1 V, the power-on reset (POR) circuit initializes the TPS2456 and allows normal operation.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
11
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
ENABLE FUNCTIONS
The TPS2456 has two external enable pins for each of the channels.
The GAT1x and GAT2x pins are held low when the ENx pin is low. A high on ENx enables GAT1x for normal
control by the startup and protection features. Toggling ENx low, then high, clears a latch-off condition after a
fault has occurred on the channel.
The GAT2x pin is held low when the ORENx or ENx pins are low. The reverse blocking comparator-driven state
machine controls GAT2x when ORENx and ENx pins are high.
ENx
ORENx
PROTECTION
(M1x, GAT1x)
BLOCKING
(M2x, GAT2x)
0
0
Disabled (low)
Disabled (low)
0
1
Disabled (low)
Disabled (low)
1
0
Enabled
Disabled (low)
1
1
Enabled
Enabled
Each of the four enable pins has an internal 200 kΩ pullup resistor to VINT.
POWER GOOD (PGx) OUTPUTS
The TPS2456 provides an active-low open-drain Power Good (PGx) output for each channel. PGx goes low
(output good indication) for rising VOUTx exceeding 10.63 V and PGx goes high for falling VOUTx below 10.5 V. A
100 µs deglitch filter aids in avoiding false indications due to noise.
FAULT (FLTx) OUTPUTS
The TPS2456 provides an active-low open-drain fault output for each channel. The FLTx output pulls low when
the channel has remained in current limit long enough for the fault timer to expire (VCTx > 1.35 V). A channel
experiencing a fault timeout shuts down and latches off. Toggle the faulted channel’s ENx low and high to clear
the fault and re-enable the channel.
CURRENT LIMIT AND FAST TRIP THRESHOLDS
Load current is monitored by sensing the voltage across RSENSEx, whose values typically lie in the range of 4 mΩ
to 10 mΩ. Each channel features two distinct thresholds, a current-limit threshold and a fast-trip threshold.
The current limit threshold sets the regulation point of a feedback loop. If the current flowing through the channel
exceeds the current limit threshold, VGAT1x is reduced, forcing the MOSFET into linear operation. This causes the
current flowing through the channel to settle to the value determined by the current limit threshold. For example,
when a module first powers up, it draws an inrush current to charge its load capacitance. The current-limit loop
ensures that this inrush current does not exceed the current limit threshold. M1 will dissipate much more power
in current limit than during normal operation. The fault timer circuit limits the interval M1 operates in this
condition.
There is a delay before channel current is regulated following the onset of an overload during normal operation.
The current limit circuit is able to sink 30 µA from the protection MOSFET gate. The delay is the result of the
MOSFET’s CISS discharge from (VINx + 13 V) to ( VINx + VT_M1x) where VT_M1x is the protection MOSFET's
threshold voltage. Overloads between the current limit and the fast trip threshold will be permitted for this period.
This is demonstrated by Figure 16. Currents above the fast trip threshold are handled by rapidly turning the
protection MOSFET off with a strong gate pulldown that is driven by a 10 µs oneshot. The fault timer starts and
the gate is allowed to rise after the oneshot completes in what resembles a normal startup.
The fast trip threshold protects the MOSFET and channel components against a severe short that creates a high
current faster than the current-limit loop can control. If (VSENPx – VSENMx) exceeds the 100 mV fast trip threshold,
GAT1x and GAT2x are immediately pulled to GND for a minimum of 10µs. The channel turns back on slowly,
allowing the current limit feedback loop time to take over. The fault timer period limits the duration the MOSFET
will see this stress. This is demonstrated by Figure 13 and Figure 14.
12
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
When the TPS2456 protects a supply output in configurations that allow the loads to hotplug, pay special
attention to coordinating load surges (due to input capacitance) and the fast trip threshold. The fast trip threshold
may need to be set 2–5 times higher than the current limit to accommodate this. Care must also be taken if the
INx voltages can have fast rising transients. The resulting charge current to capacitors on OUTx can potentially
exceed the fast trip threshold.
FAST TRIP AND CURRENT LIMITING
Figure 17 shows a simplified block diagram of the fast trip and current limit circuitry. Each channel requires an
external N-channel protection MOSFET and three external resistors. These resistors allow the user to
independently set the fast trip threshold and the current limit threshold, as described below.
The fast trip function is designed to protect the channel against short-circuit events. If the voltage across RSENSEx
exceeds 100 mV, the TPS2456 immediately turns off the protection MOSFET, M1x. The nominal fast trip limit IFTx
is defined in Equation 1.
100 mV
IFTx =
RSENSEx
(1)
The current limit circuit regulates VGAT1x to control the channel current from exceeding ILIMITx. The current limit
circuitry includes two amplifiers, A1 and A2, as shown in Figure 17 and Figure 4. Amplifier A1 forces the voltage
across external resistor RSETx to equal the voltage across external resistor RSENSEx. The current that flows
through RSETx also flows through external resistor RMONx, generating a voltage on the MONx pin per Equation 2.
æR
´ ISENSEx ö
VMONx = ç SENSEx
÷ ´ RMONx
R SETx
è
ø
(2)
Amplifier A2 implements a slow-reacting current limit. As long as VMONx is less than 0.675 V, GAT1x operates
normally. When VMONx exceeds 0.675 V, amplifier A2 causes a small current to be drawn from GAT1x. The gateto-source voltage of M1x drops until load current is reduced and the two inputs of amplifier A2 balance. The
current flowing through the channel then equals ILIMITx per Equation 3.
æ
ö
R SETx
ILIMITx = ç
÷ ´ 0.675 V
è RMONx ´ RSENSEx ø
(3)
I
´ RMONx ´ R SENSEx
RSETx = LIMITx
0.675 V
(4)
The recommended value of RMONx is 6.81 kΩ. This resistor should be greater than 675 Ω to prevent excessive
currents from flowing through the internal circuitry.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
13
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
IFT,LIMIT
100
RSENSEx
RSETx
SENPx
SETx
SENMx
GAT1x
675mV
+
A2
30mA
+
Fast Trip
Comparator
Current
A1
Limit Amp
60mA
+
100mV
VCP
MONx
RMONx
Figure 17. Over-Current Protection Circuitry
TURN ON AND INRUSH SLEW RATE CONTROL
One of the main functions of a protection device is to provide a method of hot-plugging and starting up a unit in a
low-stress and controlled manner. Starting includes the ability to charge the output capacitance (on OUTx)
without overburdening the input power bus while minimizing the stress on the protection MOSFET. Two possible
charge-rate control methods are possible with the TPS2456, current limited and gate dv/dt controlled.
As normally configured, the gate dv/dt turn-on slew rate is described by Equation 5.
IGAT1x(sourcing)
dVGAT1x
@
dt
C Gate-M1x
(5)
where IGAT1x(sourcing) equals the current sourced by the GAT1x pin (nominally 30 µA) and CGate-M1x is the reverse
transfer capacitance, CRSS. Average CRSS may be approximated using the MOSFET VGATE vs. Qg graph as CRSS
= ΔQg / VT where ΔQg is the width of the plateau region and VT is the gate plateau voltage. To simplify the
calculation, the MOSFET gate capacitances are assumed to be fixed, while in reality, there is a voltage
dependency. The output voltage tracks VGATE_M1x once it has exceeded the MOSFET threshold voltage if current
limit is not active. The inrush current is defined by the following equation for a purely capacitive load. Startup of a
switching converter load during inrush should be avoided by use of PGx to control the converter.
dVOUTx
dVGAT1x
IINx_INRUSH =
´ COUTx =
´ COUTx
dt
dt
(6)
The actual inrush current is the lesser of the current limit (Equation 3) or dv/dt-limited inrush current.
To reduce the slew rate, increase CGate-M1x by connecting additional capacitance from GAT1x to ground. Place a
resistor of at least 1000 Ω in series with the additional capacitance to prevent it from interfering with the fast turn
off of the MOSFET.
14
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
FAULT TIMER PROGRAMMING
Each channel requires an external capacitor CTx connected between the CTx pin and ground. The TPS2456
sources 10 µA into CTx when the gate voltage is low ((VGAT1x– VINx) < 6 V). The timer circuit interprets a low
VGAT1x as an indication that current limit is active. The TPS2456 pulls GAT1x and GAT2x to ground and latches
the channel off if current limit persists long enough for VCTx to reach 1.35 V. CTx is discharged through a nominal
200 Ω pull-down resistor when (VGAT1x– VINx) > 6 V) and FLTx is not active. The nominal fault time tfx is defined
by Equation 7.
1.35 V
´ CTx
tfx =
10 μA
OR
CTx =
t fx ´ 10 μA
1.35 V
= tf x ´ 7.4 ´ 10-6
(7)
Converter startup typically sets the minimum tfx. There are three important intervals to consider when calculating
the time to set tfx, initial charge of the MOSFET gate to the threshold voltage, the interval as VOUTx rises to VINx,
and the interval for VGAT1x to exceed VINx by 6 V. Assume that a constant CISS is charged in the first and third
periods since the MOSFET drain and source voltages do not change. The middle period may be controlled by
either current limit or gate dv/dt limit as previously discussed. Let VTM1x be the MOSFET gate voltage to sustain
the inrush current.
Gate dv/dt Limited Inrush
t INRUSH =
CISS_M1x ´ VTM1x
IGAT1x
+
CRSS_M1x ´ VIN1x
IGAT1x
+
(
CISS_M1x ´ 6 V - VT_M1x
)
IGAT1x
Current Limited Inrush
t INRUSH =
CISS_M1x ´ VTM1x
IGAT1x
+
(
COUTx ´ VIN1x CISS_M1x ´ 6 V - VT_M1x
+
ILIMITx
IGAT1x
)
(8)
Many of these parameters have wide tolerance, thus, the above approximation provides an initial estimate.
Provide sufficient margin in the CTx selection to assure the channel starts reliably while not becoming overly long.
Shorter fault times reduce the stresses imposed on the protection MOSFET under fault conditions, permitting the
use of smaller, less expensive protection MOSFETs.
ENx RESET PERIOD
The TPS2456 will latch off after a current limit that persists long enough to trip the fault timer. The TPS2456 may
be re-enabled by cycling the ENx false (low), then high. There is a minimum low period required to fully reset
CCTx that is determined by the R x C period where R is the internal discharge resistance. Calculate the minimum
period as tENx_LOW_MIN = CCTx_MAX x 400 Ω x 3. Assuming CCTx_MAX is 22 nF at 20% tolerance, tENx_LOW_MIN = (22
nF x 1.2) x 400 x 3 = 31.7 µs. tENx_LOW_MIN should always be greater than 100 ns.
BLOCKING OPERATION
Each channel may use an external MOSFET (M2x) to provide reverse blocking. This feature is often used where
two inputs are ORed together to a common output for redundancy. Blocking protects the common output from
being drawn down if an input is shorted, and maintains the independence of both inputs. Blocking may not be
required in all system topologies. The TPS2456 pulls the GAT2x pin high when V(INx–OUTx) exceeds 10 mV, and it
pulls the pin low when this differential falls below –3 mV (VOUTx is greater than VINx). These thresholds provide 13
mV of hysteresis to help prevent false triggering as shown in Figure 18. This technique will allow some reverse
current to flow, but provides positive detection in the event of a real fault.
The blocking MOSFET is oriented so its body diode conducts forward current and blocks reverse current. The
body diode does not normally conduct current because the MOSFET turns on when the voltage differential
across it exceeds 10 mV.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
15
TPS2456
www.ti.com
VGAT2x
SLVSA78C – MARCH 2010 – REVISED JULY 2012
VINx + 13V
10mV
- 3mV
GND
(VINx-VOUTx)
Figure 18. Blocking Thresholds
APPLICATION INFORMATION
SYSTEM DESIGN CONSIDERATIONS
The TPS2456 has two independent 12 V sections which provide protection and blocking (ORing). These sections
may be used in multiple configurations.
• TPS2456 on the power input of a system
– Two redundant input power rails to a single output (see Figure 1)
– Blocking protects output when one of the inputs is shorted
– Two independent loads powered by two separate or one common input rail
– Blocking not required
– Two redundant input rails ORed (no protection) to one common output
• TPS2456 on the power output of a system
– Up to two output rails with protection
– Protection isolates faulted output bus
– Enable can be used to turn output on and off
– Up to two output power rails with protection and blocking
– Used where multiple outputs are tied together
The system power architecture drives the topology that best suits a particular design.
DESIGN EXAMPLE: CURRENT LIMITED START-UP
The following example is for a single channel protection circuit using current-limited inrush control. The design of
the second channel would follow the same procedure and is not shown since it is redundant.
For this design example, a system board with 1000 µF of capacitance and a dc load of 1.6 Ω (or 7.5 A) must be
able to be hot plugged into a 12 V main bus supply. The main bus supply has a peak fault current capability of
20 A. Operating above 20 A of current draw runs the risk of opening a circuit breaker and shutting the system
down. The average current budgeted for the system board is 7.5 A under normal conditions. The main bus can
supply up to 10.1 A peak for up to 10 ms during start-up or transient conditions. This procedure assumes that the
inrush current is not limited by the gate charge rate. The basic system block diagram is shown in Figure 19.
16
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
Multiple Outputs
Possible
PROTECTION
LOAD
RSENSEx
CLOADx
1000mF
OUTx
GATE1x
Part of TPS2456
CTx
RLOADx
1.6W
0.1mF
RGATEx
SENMx
GND
RMONx
MONx
SENSPx
INx
Specifications (per output):
Peak Fault Current = 20A
Peak Current Limit = 10.1A
Average Current = 7.5A
M1x
RSETx
0.1mF
SETx
12V Main Bus Supply
CTx
Figure 19. 12 V Main Bus
Select RSENSEx
The first step is to calculate RSENSEx which sets the fast current trip point, IFTx. This is the maximum current that
can pass through M1x and is meant to protect against short circuits. Calculate RSENSEx using Equation 9 for a
peak fault current (IFTx) of 20 A.
100mV 100mV
RSENSEx =
=
= 5mΩ
IFTx
20A
(9)
The RSENSEx resistor is in series with the main power path and should have a power rating sufficient to support
the full load current. The 12 V main bus has budgeted 10.1 A for this board, so this is the value of limit used for
further calculations including the power dissipated in RSENSEx. The power dissipated by RSENSE is calculated using
Equation 10. A higher wattage rating should be used based on local derating practice (for example 50%).
PRSENSEx = ILIMITx 2 × RSENSEx = 10.12 ×5mW = 0.51Watts
(10)
Select RSETx
Next, RSETx is calculated to set the channel current limit (ILIMITx) to 10.1 A. RMONx is also a variable in the
calculation of RSETx. Use the recommended 6.81kΩ for RMONx (although other values can be used) and 10.1 A for
ILIMITx to calculate RSETx.
I
×RMONx ×RSENSEx 10.1A × 6.81kW ×0.005W
RSETx = LIMITx
=
= 509W
0.675V
0.675V
(11)
Choose RSETx as the closest standard value, 511 Ω.
Estimate Output Charge Time
The system can provide 10.1 A of peak current for 10 ms. This current can be used for start-up of the system
board as long as the output capacitance can be charged up to 12 V in less than 10 ms while also supplying
current to the load resistance connected in parallel to the output capacitor. The charge time is estimated using
Equation 12. For this equation, VOUTx is the final nominal voltage for the board (12 V), RLOAD is the dc load of the
board (1.6 Ω), and there is a small amount of time for the pass transistor’s gate capacitance to charge to the
threshold voltage. This time, typically around 100 µs, is added to the end of the equation to provide a better
estimate of the total start-up time.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
17
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
æI
×RLOADx - VOUTx ÷ö
÷÷ +100ms
t CHG » -RLOADx ×CLOADx ×ln ççç LIMITx
÷ø
çè
ILIMITx ×RLOADx
t CHG
æ10.1A ×1.6W -12V ö÷
» -1.6W ×1000mF×ln ççç
÷ +100ms
è 10.1A ×1.6W ø÷
t CHG » 2.27ms
(12)
(13)
(14)
The estimated time to charge the output is 2.27 ms. It is safe to allow the board to power up using the peak
current limit because tCHG is below the 10ms target.
Equation 12 assumes there is a resistive load on the output during the ramp up so the output voltage has an
“RC” shape. The output capacitance charges linearly if the load is purely capacitive, simplifying the charge time
equation to the following.
C
× VOUTx
t CHG = LOADx
+100ms
ILIMIT_M1x
(15)
Select M1x
The next design step is to select M1x. The TPS2456 is designed to use N channel MOSFETs as protection
devices. The maximum MOSFET gate to source voltage rating, VGS-MAX, must be high enough to support the
highest of the gate drive (14.5 V) or input voltage.
The next factor to consider is the drain to source voltage rating, VDS-MAX, of the MOSFET. From a dc perspective,
the MOSFET needs to withstand the input power supply voltage of 12 V for this example. However; the MOSFET
can be exposed to high voltage spikes during fault conditions. For this reason, a MOSFET with a substantially
higher VDS-MAX rating improves the system reliability and provides voltage headroom for transient protection
(snubber, TVS, diodes, etc.). Look for a VDS-MAX rating with a minimum of twice of the input power supply voltage.
Next, the dc power loss of the MOSFET must be considered. The power dissipation of the MOSFET is directly
related to the RDS(on) of the MOSFET. The dc power dissipation for the MOSFET can be calculated using
Equation 16.
PDx = RDS(on)_M1x ×ILIMITx 2
(16)
Taking these factors into consideration, the TI CSD16403Q5A was selected for this example. The
CSD16403Q5A has a VGS-MAX rating of 16 V, VDS-MAX rating of 25 V, an RDS(on) of 2.2 mΩ, and an RθJA-MAX of 51
°C/W.
During normal circuit operation, the MOSFET can have up to 10.1 A flowing through, which equates to 0.22 W
(I2xR) and an 11°C rise in junction temperature (P x RθJA-MAX). This is well within the data sheets limits for the
MOSFET. The power dissipated during a fault (e.g. output short) is substantially larger than the steady-state
power. The power handling capability of the MOSFET needs to be checked during fault conditions.
Most MOSFET data sheets provide a Safe Operating Area (SOA) plot. This plot can be used to check if the
MOSFET can survive the power form a transient fault condition. Figure 20 shows the SOA curve for the
QSD16403Q5A. The maximum fault current is set to 20 A for the 12 V input bus. This point can be located on
Figure 20. The diagonal lines tell the length of time this transient can be safely applied to the QSD16403Q5A.
The transistor can survive a 12 V, 20 A transient for approximately 9 ms.
18
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
1k
ID − Drain Current − A
100
1ms
10
10ms
100ms
1
Area Limited
by RDS(on)
1s
0.1
Single Pulse
o
RqJA = 94 C/W (min Cu)
0.01
0.01
0.1
DC
1
10
100
12
VDS − Drain To Source Voltage − V
Figure 20. Drain To Source Voltage
The turn off time of the TPS2456 and MOSFET should be taken into account. The TPS2456 detects the fault
condition as soon as the current through the sense resistor reaches 20 A. There is a 300 ns maximum
propagation delay for the TPS2456 to start discharging the MOSFET gate. The MOSFET has an additional turnoff delay due to gate discharge (see the Electrical Characteristics table, Sinking current - Fast turnoff). The total
delay for the TPS2456 and the CSD16403Q5A is approximately 310 ns. The fault current continues to rise above
20 A for this period. The rise of the fault current is determined by any inductance and resistance in the power
path as well as the impedance of the input voltage source. Continuing to follow the 12 V line up on the SOA
curve, it can be seen that the CSD16403Q5A could handle peak currents up to 180 A for 1 ms, giving substantial
margin in this design. This makes this transistor a good choice for this application.
Output Charge Time Refinement
A more accurate charge time can be calculated using Equation 17, now that the MOSFET has been chosen. This
is the same as Equation 15, but the 100 µs term is replaced with the variables that determine the time it takes to
charge the gate of the MOSFET up to the threshold voltage. The threshold voltage used in this equation should
be the voltage where the Mosfet starts to conduct higher currents. This can be found in the MOSFET data sheet
from graphs showing ID vs. VGS. For the CSD16403Q5A, the VT_M1x is 1.6 V, and CISS is 2040 pF. The term IG in
Equation 17 is the GAT1x sourcing current, typically 30 µA. Using these values, Equation 17 gives a charge time
of 2.28 ms
æI
×RLOADx - VOUTx ÷ö VT_M1x ×CISS_M1x
÷÷ +
t CHG = -RLOADx ×CLOADx ×ln ççç LIMITx
÷ø
çè
ILIMITx ×RLOADx
IG
(17)
Select CTx
The next step is to determine the minimum fault timer period. In the previous section, the change time calculation
yielded 2.28 ms. This is the amount of time it takes to charge the output capacitor up to the final output voltage.
However, the fault timer uses the difference between the input voltage and the gate voltage to determine if the
TPS2456 is in current limit. The fault timer continues to run until VGATE_M1x is 6 V above the input voltage. Some
additional time must be added to the charge time to account for this additional gate voltage rise. The minimum
fault timer time can be calculated using Equation 18.
æI
×RLOADx - VOUTx ÷ö (6 V + VTM1x ) × CISS_M1x
t TMR_MIN = -RLOADx ×CLOADx ×ln ççç LIMITx
÷÷÷ +
çè
ILIMITx ×RLOAD
IG
ø
(18)
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
19
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
Using the example numbers in the above equation leads to a minimum fault timer time of 2.688 ms. The fault
timer must be set to a value higher than 2.688 ms to avoid turning off during start-up but lower than any
maximum time limit. There is a maximum time limit set by the SOA curve of the MOSFET. Referring back to
Figure 20, the CSD16403Q5A SOA curve, the MOSFET can tolerate 10.1 A with 12 V across it for approximately
20 ms. However; the input power supply can only supply the 10.1 A for 10 ms. Therefore, the fault timer should
be set to between 2.688 ms and 10 ms. For this example, select 8 ms to allow for variation of system parameters
such as temperature, load, component tolerance, and input voltage. The timing capacitor is calculated in
Equation 19 as 59 nF. Select a the next highest standard value, 62 nF, yielding an 8.37 ms fault time.
t
×10m A 0.008s×10m A
CTx = FAULT
=
= 59nF
1.35V
1.35V
(19)
Blocking Device, M2x
Since this example uses a single channel, there is no need for the blocking MOSFET, and it can be left out of the
circuit. No connection needs to be made to the GAT2x or ORENx pins.
DESIGN EXAMPLE: GATE RAMP LIMITED STARTUP
In the first example, the output capacitance is charged in current limit. In some applications, the current limit is
the absolute maximum that the circuit should see, so charging the output up in current limit is not an option. In
this case, it is necessary to slow down the output voltage ramp so that the current limit is not reached. This can
be done by adding additional capacitance to M1x's gate.
The gate of the pass transistor is driven by a 30 µA (typical) current source. The current charges the gate to
source and gate to drain (Crss) capacitance, producing a voltage ramp at the gate. The time of the ramp can be
lengthened by adding a capacitor, CADD, between the gate and ground. A 1 kΩ resistor should be placed in
series with the additional capacitance as shown in Figure 21.
From
Source
To
Load
M1x
Part of
TPS2456
GATE1x
CADD
IG
30mA
GND
1kW
Figure 21.
With CADD, the output voltage ramp is equal to:
dVOUTx dVGATE_M1x
IG
=
=
dt
dt
CRSS_M1x + CADD
(20)
The peak current, IINX-PEAK, that is reached with the new ramp rate is:
V
COUTx ×IG
IINx_PEAK = OUTx +
RLOADx (CRSS + CADD )
(21)
20
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
CADD can be adjusted so that IINx_PEAK is less than ILIMITx avoiding current limit start-up. Using a controlled gate
ramp requires lower peak current, but takes longer to charge the output capacitance. The length of the fault time
needs to be selected to accommodate this longer ramp up time. The minimum time the fault timer should be set
to is described by Equation 22.
VT_M1x (CISS + CADD ) VOUTx × (CRSS + CADD ) 6× (CISS + CADD )
t TMR_MIN =
+
+
IG
IG
IG
(22)
BYPASS CAPACITORS
It is a good practice to provide low-impedance ceramic capacitor bypassing of INx and OUTx. Values in the
range of 10 nF to 1 µF are recommended. Some system topologies are insensitive to the values of these
capacitors; however, some are not and prefer to minimize the value of the bypass capacitor.
Input capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the low
impedance power bus when inserted. This stresses the connector contacts and causes a short voltage sag on
the input bus. Small amounts of capacitance (e.g., 10 nF to 0.1 µF) are often tolerable in these systems. In
systems with little or no bus hold up capacitance on the backplane, it is common to have no capacitance at the
board input. This helps minimize transients at plug in.
Filter capacitors at the output of a redundant plug-in board are useful for controlling voltage transients, but they
may can cause problems when the board is inserted into an active bus. If the output capacitor charge from an
active bus is not limited, the inrush surge might engage the active supply's fast-trip shutdown. One possible
solution is to put a few Ohms of resistance in series with the capacitor to limit inrush below the fast trip level.
TRANSIENT PROTECTION
If the TPS2456 is used in applications which have large input and output capacitors, voltage transients during
load steps or short circuits are controlled and pose no problems.
TPS2456 devices are sometimes deployed systems that may have long, inductive feed or load interconnections.
The effect of the inductance, with little local capacitance, gives rise to potential voltage transient issues. A
simplified model of this is shown in Figure 22. Channel current transients may be caused by events such as hotplug, output shorts with fast turnoff, or abrupt load changes. The combination of input inductance and an abrupt
load decrease causes a positive voltage spike on the TPS2354 INPUT pins. The combination of output
inductance and an abrupt load decrease will cause a negative voltage spike on the TPS2354 OUTPUT. These
transients have the potential to exceed the Absolute Maximum Ratings, either damaging the TPS23754 or
causing undesired operation.
Blocking MOSFET
Protection MOSFET
LP
RP
INPUT
E=LI2/2
+
CGD
CIN
RP
LP
OUTPUT
CDS
CDS
INx
SENMx
SENPx
100
GAT1x
GAT2x
E=LI2/2
ESD
Diode
OUTx
ESD
Diode
TPS2456
INTERCONNECT
RLOAD
1kW
100
ESD ESD
Diode Diode
E=LI2/2
CGD
CGS
CGS
LP
RP
LP+
LEMI_FILTER
POWER SUPPLY
COUT
RP
LP
LP
E=LI2/2
INTERCONNECT
LOAD
NOTE: LP = Parasitic Inductance (not all instances equal)
RP = Parasitic Resistance (not all instances equal)
Figure 22. System Transient Model
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
21
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
An analysis must be performed to determine the need for transient protection. Equation 23 allows the designer to
estimate the voltage spike due to current interruptions.
VSPIKE = VINIT + ILOAD L
C
(23)
Where:
VINIT = initial voltage at terminal being analyzed before the current is interrupted
L = combined inductance of feed and RTN lines in series with interrupted current
C = capacitance at point of computation
ILOAD = current immediately before circuit is opened
An approximation for the inductance of a straight wire is:
L ≈ [0.2 × length_in_meters × (In(4 × length/diameter) – 0.75)] nH
The capacitance in Equation 23, at INPUT, consists of parasitic capacitance and any intentional bypass
capacitance. This implies that the transients can be controlled by the addition of sufficient capacitance.
Equation 24 can be used to calculate the capacitance required to limit the voltage spike to a desired level above
the nominal voltage.
C=
L ´ ILO AD 2
(VSPIKE
2
- VNOM )
(24)
TRANSIENT PROTECTION SOLUTIONS
Typical protection solutions involve capacitors, TVSs ( Transient Voltage Suppressors ) and/or a Schottky diode.
A TVS and small bypass capacitor at INPUT (see Figure 22) are the most likely solutions to solve input voltage
overshoot. The TVS must be selected so that its clamping is below the Absolute Maximum Rating (17 V) at the
anticipated fault current. For example, the SMCJ13A data sheet specifies a maximum clamping voltage of 21.5 V
(which exceeds the Absolute Maximum voltage) at 69.7 A. The actual clamping voltage at the fault current (IFT)
may be within the Absolute Maximum; however, the clamp voltage at lower currents must be estimated to verify.
By modeling the TVS as a perfect voltage clamp in series with a resistor, the clamping voltage may be estimated
at different currents per Equation 25.
VCL_MAX - VBR_MIN
21.5 V - 14.4 V
RSERIES =
=
= 0.102 W
IPEAK_PULSE - ITEST
69.7 A - 1 mA
(25)
The maximum permitted clamping current for this device is found in Equation 26. This is a worst case (low)
number.
VABS_MAX - VBR_MAX
17 V - 15.9 V
ICL_MAX =
=
= 10.8 A
RSERIES
0.102
(26)
A Schottky diode and capacitor across the OUTPUT (Figure 22) are the most likely solutions to clamp the
transient energy and limit the negative voltage excursion. Although the Schottky diode absorbs most of the
energy, the extremely fast di/dt at shutoff allows some of the leading edge energy to couple through the parasitic
capacitances of the protection and blocking MOSFET (CDS, CGS, CGD) to the GAT1x and GAT2x pins. Protection
for these pins is provided by 100 Ω resistors which have little effect on normal operation but provide good
isolation during transient events.
Equation 24 gives insight into selection of transient protection capacitors for both INPUT and OUTPUT; however,
there are concerns with adding a lot of capacitance in some situations. See the BYPASS CAPACITORS section
regarding considerations and limitations
PCB layout of the protection is critical to its performance. The layout should minimize the impedance between
the TPS2456 and the protection in order to provide the best clamping.
22
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
OUTPUT BLEED RESISTANCE
The OUTx pin sources a small amount of current when the channel input is powered, but disabled in nonredundant configurations (output is unpowered). The leakage can be modeled as a 6 V source in series with a
280 kΩ resistor, allowing approximately 21.4 µA into a short. This leakage can charge a high-impedance load to
approximately 6 V. If this is unacceptable, control the output voltage in this state by adding a load resistor from
OUTx to GND. Select the resistor, RBLEED, per Equation 27, where VBLEED is the desired maximum output
voltage. Since the model is nominal, use a 25% smaller resistor value.
VBLEED
RBLEED =
´ 280 kW
(6 V - VBLEED )
(27)
CONTROLLING FAULT CURRENT in REDUNDANT POWER TOPOLOGIES
System topologies such as Figure 1 are often used to provide power source redundancy. This permits the load to
run from either source, or potentially both in parallel. Blocking permits the load to operate uninterrupted in the
event of either source failing open or shorting to GND. However, this topology permits the load to draw twice the
channel fault current (ILIMITx) for two closely matched sources.
The simple configuration of Figure 23 programs the total load fault current to a fixed value independent of the
number of channel feeds to the load. The current limit thresholds now apply to the sum of the currents delivered
by the redundant channels. When implementing this redundant mode, it is recommended that all of the channels
use the same RSENSEx and RSETx values. This configuration does not foster sharing or smooth transitions
between sources, it simply permits the power to flow from the higher source, but limits the maximum load current
to a fixed value.
Part of
TPS2456
MONA
RSENSEA = RSENSEB
RSETA = RSETB
MONB
RMON
Figure 23. Fixed Fault Current Application
CURRENT FEEDBACK TO A SHELF CONTROLLER
A shelf controller can monitor channel currents by observing VMONx, which is proportional to the current through
RSENSEx. The voltage on MONx can be directly sampled with an analog circuit (e.g. a comparator) or sampled
with an Analog to Digital Converter (ADC) to provide a digital representation of the current. Figure 24 shows a
typical system configuration using a multiplexer and ADC (analog to digital converter) to monitor the current in
both channels of the TPS2456. It has been assumed that the normal 0 V to 0.675 V range of VMONx is suitable for
the ADC input. If this is not the case, operational amplifier circuits should be used to buffer and scale these
signals. It is not advisable to add capacitance to the MONx pins as this effects the current-limit loop.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
23
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
μP
TPS2456
MONa
a0
2:1 Mux
MONb
ADC
a1 s0
6810
6810
Figure 24.
The output of the MONx pin is a current proportional to the current passing through the pass transistor as defined
in Equation 2. The current flowing out of the MONx pin is converted to a voltage by RMONx which is typically 6.81
kΩ. Any circuitry connected to the MONx pin should either have an input impedance much higher that RMONx to
reduce measurement and limiting error, or the value of the parallel combination must be adjusted. The output of
the MONx pin can also be buffered using a unity gain, non-inverting operational amplifier if necessary.
LAYOUT CONSIDERATIONS
TPS2456 applications require layout attention to ensure proper performance and minimize susceptibility to
transients and noise. In general, all runs should be as short as possible, but the following list deserves first
consideration.
1. When used, decoupling capacitors on INA and INB should have minimal length to the pin and to GND
2. SENMx and SENPx runs must be short and run side-by-side to maximize common mode rejection. Kelvin
connections should be used at the points of contact with RSENSEx. (See Figure 25)
LOAD CURRENT
PATH
RSET
LOAD CURRENT
PATH
SENP
SET
SENM
SENP
SET
SENM
RSET
RSENSEx
TPS2456
TPS2456
Method 1
Method 2
Figure 25. Recommended RSENSE Layout
3. SETx runs need to be short on both sides of RSETx.
4. Power path connections should be as short as possible and sized to carry at least twice the full load current,
more if possible.
5. Connections to GND and MONx pins should be minimized after the connections above have been placed.
6. The device dissipates low power so soldering the powerpad to the board is not a requirement. However,
doing so improves thermal performance and reduces susceptibility to noise.
24
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
TPS2456
www.ti.com
SLVSA78C – MARCH 2010 – REVISED JULY 2012
7. The board should use a single point ground scheme. The current return path for both channels should be
isolated from each other as much as possible and tie together at a single point. This helps to reduce ground
bounce and false turn offs in one channel when there is a fault in the other channel. Also, sensitive analog
grounds (such as the ground connections of RMONx and CTx) should be run separate from the power path
grounds. This analog ground must also tie to the two power path grounds at a single point. Figure 26 shows
the top layer routing of the TPS2456 EVM which uses a single point ground scheme. Each major power path,
the analog ground, and the single point tying them together is highlighted in the figure.
Figure 26.
8. Protection devices such as snubbers, TVS, capacitors or diodes should be placed physically close to the
device they are intended to protect, and routed with short trances to reduce inductance. For example, the
protection Schottky diode shown in Figure 1 should be physically close to the source of the pass transistor
(or the drain of the blocking MOSFET if used).
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
25
TPS2456
SLVSA78C – MARCH 2010 – REVISED JULY 2012
www.ti.com
REVISION HISTORY
Changes from Original (March 2010) to Revision A
Page
•
Changed data sheet status from Preview to Production ...................................................................................................... 1
•
Changed the second paragraph of the DESCRIPTION From: The ORing control uses an external MOSFET to
prevent reverse current flow To: The ORing control uses an external MOSFET to block reverse current when an
input is shorted. .................................................................................................................................................................... 1
•
Deleted the Dissipation Rating table and added the Thermal Information table .................................................................. 2
•
Added test to the SENPA pin of the PIN FUNCTIONS table - Connect to the source side of RSENSEA. .............................. 6
•
Changed PIN 32 From: GNDA To: GND and PIN 23 From: AGND To: GND in the DEVICE PINOUT illustration ............. 7
•
Changed the DETAILED PIN DESCRIPTIONS .................................................................................................................... 7
•
Changed Figure 8 Title From: FAST CURRENT LIMIT THRESHOLD vs TEMPERATURE To: CURRENT LIMIT
THRESHOLD vs TEMPERATURE, and added RSETx and RMONx values ............................................................................. 9
Changes from Revision A (November 2010) to Revision B
Page
•
Changed the max value of the second row in the ABS MAX RATINGS table From: 17 To: 20 .......................................... 2
•
Changed the Test Condition for UVLO From: VINX To: SENPx rising .................................................................................. 4
•
Changed the Test Condition for UVLO hysteresis From: VINX To: SENPx falling ................................................................ 4
•
Updated the SENPx pin description ..................................................................................................................................... 8
•
Updated second paragraph of the BYPASS CAPACITORS section .................................................................................. 21
•
Changed item 1 of the LAYOUT CONSIDERATIONS section, From: Decoupling capacitors... To: When used,
decoupling capacitors... ...................................................................................................................................................... 24
Changes from Revision B (December 2010) to Revision C
•
26
Page
Changed the Sinking current, (VGAT1x = VGAT2x) ≤ 25 V MIN value of From: 10 To 6 mA .................................................... 4
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2456
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS2456RHHR
ACTIVE
VQFN
RHH
36
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS2456
TPS2456RHHT
ACTIVE
VQFN
RHH
36
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS2456
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
