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TPS24720
SLVSAL1E – MARCH 2011 – REVISED APRIL 2016
TPS24720 2.5-V to 18-V High-Efficiency Adjustable Power-Limiting Hot-Swap Controller
With Current Monitor and Overvoltage Protection
1 Features
3 Description
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The TPS24720 is an easy-to-use, full-featured
protection device for 2.5-V to 18-V power rails. This
hot-swap controller drives an external N-channel
MOSFET, while protecting source, load and external
MOSFET against multiple potentially damaging
events. During startup, load current and MOSFET
power dissipation are limited to user-selected values.
After startup, currents above the user-selected limit
will be allowed to flow until programmed timeout –
except in extreme overload events when load is
immediately disconnected from source.
1
2.5-V to 18-V Operation
Accurate Current Limiting for Startup
Programmable FET SOA Protection
Adjustable Current Sense Threshold
Programmable Fault Timer
Power-Good Output
Fast Breaker for Short-Circuit Protection
Analog Load-Current Monitor Output
Programmable UV and OV
Low-current Standby Mode
FET Fault Detection Flag
3-mm × 3-mm, 16-Pin QFN package
Programmable power limiting ensures the external
MOSFET operates inside its safe operating area
(SOA) at all times. This allows use of smaller FETs
while improving system reliability. Power good, Fault,
FET Fault, and current monitor outputs are provided
for system status monitoring and downstream load
control.
2 Applications
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•
•
•
•
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Server Backplanes
Storage Area Networks (SAN)
Telecommunications Mezzanine Cards
Medical Systems
Plug-In Modules
Base Stations
Device Information(1)
PART NUMBER
TPS24720
PACKAGE
VQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application (12 V at 10 A)
RSENSE
2 mΩ
VIN
VOUT
COUT
470 μF
C1
0.1 μF
RSET
51.1 Ω
R7
R1
90.9 kΩ
M1
CSD16403Q5
SET
3V
RGATE
10 Ω
SENSE
GATE
R4
3.01 kΩ
OUT
R5
3.01 kΩ
R6
3.01 kΩ
FLTb
VCC
EN
PGb
R2
2.94 kΩ
TPS24720
FFLTb
OV
ENSD
IMON
PROG
R3
10 kΩ
LATCH
RPROG
53.6 kΩ
GND
TIMER
CT
56 nF
RIMON
1.43 kΩ
VUVLO = 10.83 V
VOV = 14.02 V
ILMT = 12 A
tFAULT = 7.56 ms
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS24720
SLVSAL1E – MARCH 2011 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
8
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
THERMAL INFORMATION.......................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 17
8
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application .................................................. 24
9 Power Supply Recommendations...................... 30
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 31
11 Device and Documentation Support ................. 32
11.1
11.2
11.3
11.4
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2015) to Revision E
•
Page
Changed the Part Number From TPS247120 To: TPS24720 in the Device Information table.............................................. 1
Changes from Revision C (September 2013) to Revision D
Page
•
Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Changed the Input voltage range, PROG - MAX value in the Absolute Maximum Ratings table From: 0.3 To: 3.6 ............ 5
•
Deleted External capacitance - GATE from the Recommended Operating Conditions ......................................................... 5
•
Deleted text from the last paragraph in the GATE section "If used, any capacitor connecting GATE and GND should
not exceed 1 μF and it should be connected in series with a resistor of no less than 1 kΩ.".............................................. 15
•
Deleted section: Alternative Design Example: GATE Capacitor (dV/dt) Control in Inrush Mode......................................... 29
•
Deleted text from the High-Gate-Capacitance Applications section "When gate capacitor dV/dt control is used, ...
then a Zener diode is not necessary." .................................................................................................................................. 29
Changes from Revision B (May 2011) to Revision C
Page
•
Added Note to Supply Current Disabled ................................................................................................................................ 6
•
Added Note to Fast-turnoff delay............................................................................................................................................ 8
•
Changed Gate Comparator 6 V to 5.9 V in Functional Block Diagram ................................................................................ 13
•
Changed text From :(6 V for VVCC = 12 V) To: (5.9 V for VVCC = 12 V) in the GATE pin description .................................. 14
•
Changed Equation 1............................................................................................................................................................. 16
•
Changed text in the INRUSH OPERATION section............................................................................................................. 18
•
Changed Equation 8............................................................................................................................................................. 27
•
Added text and new Equation 9 ........................................................................................................................................... 27
•
Changed Equation 11........................................................................................................................................................... 28
•
Changed text From: VGS rises 6 V To: VGS rises 5.9 V ........................................................................................................ 28
•
Changed text following Equation 11, From: 1.23 ms To 1.22 ms ........................................................................................ 28
2
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SLVSAL1E – MARCH 2011 – REVISED APRIL 2016
•
Changed Equation 15 ........................................................................................................................................................... 29
•
Changed text describing Equation 15 and Equation 16 in the Alternative Design Example section. (Equation 15 and
Equation 16 deleted by revision F.)...................................................................................................................................... 29
Changes from Revision A (April 2011) to Revision B
Page
•
Changed voltages in PGb pin description from 140 mV and 340 mV to 170 mV and 240 mV............................................ 15
•
Changed RIMON equation ...................................................................................................................................................... 26
Changes from Original (March 2011) to Revision A
•
Page
Corrected voltages shown Functional Block Diagram.......................................................................................................... 13
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SLVSAL1E – MARCH 2011 – REVISED APRIL 2016
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5 Pin Configuration and Functions
ENSD
PGb
LATCH
FLTb
15
14
13
8
4
OUT
GND
7
3
SET
TIMER
Thermal
Pad
6
2
IMON
PROG
5
1
OV
EN
16
RGT Package
16 Pins
Top View
12
VCC
11
SENSE
10
GATE
9
FFLTb
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
1
I
Active-high enable input. Logic input. Connects to resistor divider.
ENSD
16
I
Pull low to put device into low-current standby mode. Logic input.
FFLTb
9
O
Active-low, open-drain FET fault indicator. Indicates shorted MOSFET when output is off.
FLTb
13
O
Active-low, open-drain output indicates overload fault timer has turned MOSFET off.
GATE
10
O
Gate driver output for external MOSFET
GND
4
–
Ground
IMON
6
O
Analog load current limit program point. Connect RIMON to ground.
LATCH
14
I
Latch or retry mode select input. Latch when floating or connected to a logic-level voltage; retry when
connected to GND.
OUT
8
I
Output voltage sensor for monitoring MOSFET power.
OV
5
I
Overvoltage comparator input. Connects to resistor divider. GATE is pulled low when OV exceeds the
threshold.
PGb
15
O
Active-low, open-drain power-good indicator. Status is determined by the voltage across the MOSFET.
PROG
2
I
Power-limiting programming pin. A resistor from this pin to GND sets the maximum power dissipation for the
FET.
SENSE
11
I
Current-sensing input for resistor shunt from VCC to SENSE.
SET
7
I
Current-limit programming set pin. A resistor is connected from this pin to VCC.
TIMER
3
I/O
VCC
12
I
Thermal
pad
—
—
4
A capacitor connected from this pin to GND provides a fault timing function.
Input-voltage sense and power supply
Tied to GND
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SLVSAL1E – MARCH 2011 – REVISED APRIL 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, all voltages referred to GND (unless otherwise noted)
Input voltage range
Sink current
MAX
–0.3
30
ENSD, OV
–0.3
20
PROG (1)
–0.3
3.6
[SET, SENSE] to VCC
–0.3
0.3
IMON, LATCH, TIMER
–0.3
5
FFLTb, FLTb, PGb
V
mA
Internally limited
IMON
Temperature
UNIT
5
PROG
Source current
(1)
MIN
EN, FFLTb (1), FLTb (1), GATE, OUT, PGb (1), SENSE, SET (1), VCC
Maximum junction, TJ
5
mA
Internally limited
°C
Do not apply voltage directly to these pins.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic
discharge
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS- All pins except PGb
001 (1)
PIN PGb
±2000
V
±500
V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 THERMAL INFORMATION
THERMAL METRIC (1)
TPS24720
QFN (16) PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
47.3
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
63.8
°C/W
RθJB
Junction-to-board thermal resistance
20.9
°C/W
ψJT
Junction-to-top characterization parameter
1.6
°C/W
ψJB
Junction-to-board characterization parameter
21
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
5.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
ENSD, OV
Input voltage range
SENSE, SET (1), VCC
NOM
MAX
0
16
UNIT
2.5
18
EN, FFLTb, FLTb, PGb, OUT
0
18
Sink current
FFLTb, FLTb, PGb
0
2
mA
Source current
IMON
0
1
mA
Resistance
PROG
4.99
500
kΩ
External capacitance
TIMER
1
Operating junction temperature range, TJ
(1)
–40
V
nF
125
°C
Do not apply voltage directly to these pins.
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6.5 Electrical Characteristics
–40°C ≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, VENSD = 3 V, RSET = 190 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND.
All voltages referenced to GND, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
UVLO threshold, rising
2.2
2.32
2.45
V
UVLO threshold, falling
2.1
2.22
2.35
V
VCC
UVLO hysteresis (1)
0.1
Enabled ― IOUT + IVCC + ISENSE
Supply current
Disabled
(1)
1
― EN = 0 V, IOUT + IVCC + ISENSE
V
1.4
0.45
Shutdown ― ENSD = 0 V, IOUT + IVCC + ISENSE
mA
mA
1.7
10
1.3
1.4
µA
EN
Threshold voltage, falling
1.2
Hysteresis (1)
50
V
mV
0 V ≤ VEN ≤ 30 V
–1
0
1
Threshold voltage
Rising or falling edge
0.3
0.7
1.4
V
Pullup current
VENSD = 5 V
0.5
1.2
2
µA
1.25
1.35
1.45
Input leakage current
µA
ENSD
OV
Threshold voltage, rising
Hysteresis (1)
60
V
mV
Input leakage current
0 V ≤ VOV ≤ 30 V
–1
0
1
µA
Deglitch time
OV rising
0.5
1.2
1.5
µs
FLTb
Output low voltage
Sinking 2 mA
Input leakage current
VFLTb = 0 V, 30 V
0.11
0.25
V
–1
0
1
µA
140
240
340
mV
PGb
Threshold
Hysteresis
V(SENSE – OUT) rising, PGb going high
(1)
Measured V(SENSE – OUT) falling, PGb going low
70
Output low voltage
Sinking 2 mA
Input leakage current
VPGb = 0 V, 30 V
–1
VIMON threshold
Measured VIMON to GND
90
Output low voltage
Sinking 2 mA
Input leakage current
FFLTb = 0 V, 30 V
mV
0.11
0.25
V
0
1
µA
FFLTb
103
115
mV
0.11
0.25
V
–1
0
1
µA
PROG
Bias voltage
Sourcing 10 µA
0.65
0.678
0.7
V
Input leakage current
VPROG = 1.5 V
–0.2
0
0.2
µA
VTIMER = 0 V
8
10
12
µA
VTIMER = 2 V
8
10
12
µA
mA
TIMER
Sourcing current
Sinking current
2
4.5
7
Upper threshold voltage
VEN = 0 V, VTIMER = 2 V
1.3
1.35
1.4
V
Lower threshold voltage
0.33
0.35
0.37
V
Timer activation voltage
Raise GATE until ITIMER sinking, measure V(GATE – VCC), VVCC = 12 V
5
5.9
7
V
Bleed-down resistance
VENSD = 0 V, VTIMER = 2 V
70
104
130
kΩ
Current limit in regulation
660
675
690
mV
IMON
Summing threshold
(1)
6
Parameters are provided for reference only, and do not constitute part of TI’s published specifications for purposes of TI product
warranty.
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Electrical Characteristics (continued)
–40°C ≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, VENSD = 3 V, RSET = 190 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND.
All voltages referenced to GND, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
16
30
µA
1.5
mV
OUT
Input bias current
VOUT = 12 V
SET
Input referred offset
Measure SET to SENSE
–1.5
0
Output voltage
VOUT = 12 V
23.5
25.8
28
V
Clamp voltage
Inject 10 µA into GATE, measure V(GATE – VCC)
12
13.9
15.5
V
Sourcing current
VGATE = 12 V
20
30
40
µA
Fast turnoff, VGATE = 14 V
0.5
1
1.4
A
6
11
20
mA
In inrush current limit, VGATE = 4 V to 23 V
20
30
40
µA
Thermal shutdown or VENSD = 0 V
14
20
26
kΩ
GATE
Sinking current
Pulldown resistance
Sustained, VGATE = 4 V to 23 V
SENSE
Input bias current
VSENSE = 12 V, sinking current
Current limit threshold
VOUT = 12 V
Power limit threshold
30
40
µA
22.5
25
27.5
mV
VOUT = 7 V, RPROG = 50 kΩ
10
12.5
15
VOUT = 2 V, RPROG = 25 kΩ
10
12.5
15
52
60
68
mV
0.3
0.9
1.4
V
7
10
13
µA
130
140
°C
10
°C
Fast-trip threshold
mV
LATCH
Threshold, rising
Pullup current
VLATCH = 0 V
OTSD
Threshold, rising
Hysteresis
(1)
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
20
60
150
µs
8
14
18
µs
0.1
0.4
1
µs
0.75
1
µs
60
115
140
ms
2
3.4
6
ms
100
250
µs
13.5
18
µs
EN
Turnoff time
EN ↓ to VGATE < 1 V, CGATE = 33 nF
Deglitch time
EN ↑
Disable delay
EN ↓ to GATE ↓, CGATE = 0, tpff50–90, See
Figure 1
ENSD
Disable delay
ENSD to GATE, tpff50–90, See Figure 1
FFLTb
Delay
FFLTb falling
PG, PGb
Delay (deglitch) time
Rising or falling edge
GATE
VVCC rising to GATE sourcing, tprr50-50, See
Figure 3
Turn on delay
SENSE
Fast-turnoff duration
Fast-turnoff delay
(1)
8
V(VCC – SENSE) = 80 mV, CGATE = 0 pF,
tprf50–50, See Figure 4
(1)
200
ns
Parameters are provided for reference only, and do not constitute part of TI’s published specifications for purposes of TI product
warranty.
VGATE
VGATE
90%
90%
VENSD
VEN
50%
50%
0
Time
0
Time
t(pff50-90)
t(pff50-90)
T0493-01
T0492-01
Figure 1. tpff50–90 Timing Definition
IGATE
Figure 2. tpff50–90 Timing Definition
VGATE
50%
50%
VVCC
VVCC – VSENSE
50%
50%
0
0
Time
t(prr50-50)
Time
t(prf50-50)
T0494-01
Figure 3. tprr50–50 Timing Definition
8
T0495-01
Figure 4. tprf50–50 Timing Definition
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6.7 Typical Characteristics
1200
5
4
T = 25°C
Supply Current (µA)
Supply Current (µA)
T = 125°C
1000
T = 125°C
800
T = –40°C
T = 25°C
3
2
T = –40°C
600
1
400
0
4
2
6
8
10
12
14
Input Voltage, VVCC (V)
16
18
0
20
Figure 5. Supply Current vs Input Voltage at Normal
Operation (EN = High)
0
4
2
6
8
10
12
14
Input Voltage, VVCC (V)
16
18
20
Figure 6. Supply Current vs Input Voltage at Shutdown
(EN = 0 V)
32
26.5
28
Voltage ,V(VCC – SENSE) (mV)
VVCC = 2.5 V
25.5
25
24.5
VVCC = 18 V
24
T = 125°C
T = 25°C
20
16
T = –40°C
12
8
23.5
–50
–20
10
40
70
Temperature (°C)
100
4
130
Figure 7. Voltage Across RSENSE in Inrush Current Limiting
vs Temperature
0
2
4
6
8
10
Voltage, V(SENSE – OUT) (V)
12
0.25
1.8
Gate Current at Current Limiting
VVCC Voltage = 12 V
32
1.6
16
1.2
Gate Current (A)
24
1.4
T = 25°C
8
0
T = 125°C
–8
–16
T = –40°C
14
Figure 8. Voltage Across RSENSE in Inrush Power Limiting
vs VDS of Pass MOSFET
40
MOSFET Gate Current (µA)
24
VVCC = 12 V
0.2
T = –40°C
T = 25°C
0.15
0.1
0.05
1
0.8
0
V(VCC – SENSE)
T = 125°C
0.6
–0.05
0.4
–0.1
0.2
–0.15
Voltage, V(VCC – SENSE) (V)
Voltage, V(VCC – SENSE) (V)
VCC Voltage = 12 V
VVCC = 12 V
26
–24
0
–0.2
–32
–0.2
–10
–40
0
5
10
15 20 25 30 35 40
Voltage, V(VCC – SENSE) (mV)
45
50
55
Figure 9. MOSFET Gate Current vs Voltage Across RSENSE
During Inrush Power Limiting
0
10
20
30
40
–0.25
Time (µs)
Figure 10. Gate Current During Fast Trip,
VVCC = VGATE = 12 V
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0.25
0.2
T = –40°C
Gate Current (A)
0.6
0.15
T = 25°C
0.5
0.1
0.4
0.05
0.3
0
V(VCC – SENSE)
T = 125°C
0.2
–0.05
0.1
–0.1
0
–0.15
–0.1
–0.2
VVCC = 3.3 V
–0.2
–10
0
10
20
40
30
–0.25
Gate Voltage Referenced to GND, VGATE (V)
0.9
0.7
Voltage, V(VCC – SENSE) (V)
Typical Characteristics (continued)
Time (µs)
32
T = 25°C
28
T = 125°C
24
20
T = –40°C
16
12
8
Figure 11. Gate Current During Fast Trip,
VVCC = VGATE = 3.3 V
20
VVCC = 12 V
CT = 10 nF
Fault-Timer Period (ms)
TIMER Activation Voltage Threshold (V)
T = 25°C
6
T = –40°C
5
4
1.6
1.2
CT = 4.7 nF
0.8
CT = 1 nF
0.4
4
0
8
12
Input Voltage, VVCC (V)
16
0
–50
20
10
40
70
Temperature (°C)
100
130
2.36
VVCC = 12 V
VVCC = 12 V
UVLO Threshold Voltage (V)
EN Upper Threshold
1.6
1.2
ENSD Threshold
0.8
0.4
0
–50
–20
Figure 14. Fault-Timer vs Temperature With Various
TIMER Capacitors
2
EN and ENSD Threshold Voltage (V)
16
2
T = 125°C
Figure 13. TIMER Activation Voltage Threshold
vs Input Voltage at Various Temperatures
–20
–10
10
30
50
70
Temperature (°C)
90
110
130
Figure 15. EN and ENSD Threshold Voltage vs Temperature
10
8
12
Input Voltage, VVCC (V)
Figure 12. Gate Voltage With Zero Gate Current
vs Input Voltage
7
3
4
0
UVLO Upper Threshold
2.32
2.28
UVLO Lower Threshold
2.24
2.20
–50
–20
10
40
70
Temperature (°C)
100
130
Figure 16. UVLO Threshold Voltage vs Temperature
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Typical Characteristics (continued)
64
PGb Rising
Fast-Trip Threshold Voltage (mV)
V(SENSE – OUT) Threshold Voltage (mV)
240
220
200
180
PGb Falling
160
140
–50
–20
10
40
70
Temperature (°C)
100
120
VVCC = 18 V
VVCC = 2.5 V
100
80
VVCC = 12 V
60
–50
–20
10
40
70
Temperature (°C)
100
130
Figure 19. PGb Open-Drain Output Voltage in Low State
62
61.5
61
VVCC = 18 V
60.5
10
–20
120
VVCC = 2.5 V
80
VVCC = 12 V
60
–50
0.6
10
–20
VEN = 0 V
100
80
VVCC = 18 V
100
140
VVCC = 18 V
130
140
0.7
VVCC = 2.5 V
100
160
160
120
40
70
Temperature (°C)
40
70
Temperature (°C)
100
130
Figure 20. FLTb Open-Drain Output Voltage in Low State
Supply Current (µA)
Low-State Open-Drain Output Voltage (mV)
VVCC = 2.5 V
62.5
Figure 18. Fast-Trip Threshold Voltage vs Temperature
Low-State Open-Drain Output Voltage (mV)
Low-State Open-Drain Output Voltage (mV)
Figure 17. Threshold Voltage of VDS vs Temperature,
PGb Rising and Falling
140
VVCC = 12 V
63
60
–50
130
160
63.5
T = 125°C
T = 25°C
0.5
0.4
T = –40°C
0.3
VVCC = 12 V
60
–50
–20
10
40
70
Temperature (°C)
100
130
Figure 21. FFLTb Open-Drain Output Voltage in Low State
0.2
0
4
8
12
Input Voltage, VVCC (V)
16
20
Figure 22. Supply Current vs Input Voltage at Various
Temperatures When EN Pulled Low
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Typical Characteristics (continued)
0.365
Timer Lower Threshold Voltage (V)
Timer Upper Threshold Voltage (V)
1.344
1.342
VVCC = 18 V
VVCC = 12 V
1.34
1.338
VVCC = 2.5 V
1.336
1.334
–50
–20
10
40
70
Temperature (°C)
100
Figure 23. Timer Upper Threshold Voltage vs Temperature
at Various Input Voltages
–20
10
40
70
Temperature (°C)
10.3
VVCC = 18 V
Timer Sinking Current (µA)
Timer Sourcing Current (µA)
VVCC = 2.5 V
100
130
10.4
10.1
VVCC = 12 V
9.9
9.8
9.7
VVCC = 2.5 V
9.6
9.5
–50
0.36
Figure 24. Timer Lower Threshold Voltage vs Temperature
at Various Input Voltages
10.2
10
VVCC = 12 V
0.357
–50
130
VVCC = 18 V
0.362
VVCC = 18 V
VVCC = 12 V
10.2
10.1
10
VVCC = 2.5 V
9.9
9.8
–20
10
40
70
Temperature (°C)
100
130
Figure 25. Timer Sourcing Current vs Temperature at
Various Input Voltages
9.7
–50
–20
10
40
70
Temperature (°C)
100
130
Figure 26. Timer Sinking Current vs Temperature at Various
Input Voltages
OV, LATCH Threshold Voltage (V)
1.6
OV Upper Threshold
1.4
1.2
Latch Threshold
1
0.8
–50
–20
10
40
70
Temperature (°C)
100
130
Figure 27. OV and LATCH Threshold Voltage vs Temperature
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7 Detailed Description
7.1 Overview
7.2 Functional Block Diagram
M1
VIN
RSENSE
RSET
SET
SENSE
RGATE
GATE
11
7
OUT
10
8
60 mV
Charge
Pump
–
+
DC
VCC
–
Servo
Amplifier
Fast
Comparator
–
IMON
RIMON
Gate
Comparator
S
Q
R
Q
+
VCC
5.9 V
11 mA
1-shot
6
Inrush
Latch
+
30 µA
+
12
–
0~60 µA
+
A
–
æ KpA
Min ç
+
PROG
FFLTb
20 kΩ
Becomes Comparator
After Inrush Limit
Complete
OUT
DC
UVLO
+
2.32 V
2.22 V
OV
9
ö
, 675 mV ÷
ø Main Opamp in Inrush
–
2
RPROG
EN
B
è B
–
240 mV
170 mV
–
15 PGb
2 ms
+
PG
Comparator
+
1
1.35 V
1.3 V
–
1.35 V
1.29 V
+
14 µs
5
10 µA
13 FLTb
Fault Logic
1.2 μs
+
1.5 V
+
TSD
–
1.35 V
0.35 V
POR
10 µA
+
0.7 V
Turn Off Main Circuit
10 μA
4
+
ENSD 16
GND
0.9 V
3
14
LATCH
TIMER
CT
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Figure 28. Block Diagram of the TPS24720
7.3 Feature Description
7.3.1 Detailed Pin Descriptions
The following description relies on the typical application diagram shown on the front page of this data sheet, as
well as the functional block diagram in Figure 28.
7.3.1.1 EN
Applying a voltage of 1.35 V or more to this pin enables the gate driver. The addition of an external resistor
divider allows the EN pin to serve as an undervoltage monitor. Cycling EN low and then back high resets the
TPS24720 that has latched off due to a fault condition. This pin should not be left floating.
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Feature Description (continued)
7.3.1.2 ENSD
When this pin is pulled low, it shuts off all internal circuitry and thus places the device in a low-current standby
mode. While in standby, the PGb, FLTb, and FFLTb outputs assume high-impedance states. A 20-kΩ resistor
pulls GATE to GND in standby. This is a much weaker pulldown than the 11 mA drawn while the part is disabled
(e.g., by EN, UVLO, OV, or overload fault current). Applications requiring rapid turnoff should disable the device
using the EN pin before pulling ENSD low. This pin is preferably pulled up to a positive voltage from 2 V to 18 V,
if not otherwise connected.
7.3.1.3 FFLTb
This active-low open-drain output pulls low if VVCC is higher than the UVLO rising threshold and the voltage on
the IMON pin exceeds 103 mV when EN is disabled. The presence of this voltage indicates that current
continues to flow through the external circuitry even though the external MOSFET has been turned off. This
presumably indicates a shorted MOSFET. FFLTb assumes a high impedance if one of the following conditions
occurs:
• ENSD is pulled low.
• Temperature on the die exceeds the OTSD shutdown threshold.
• VVCC drops below the UVLO falling threshold.
FFLTb also asserts if VVCC is higher than the UVLO rising threshold, GATE is disabled by OV, and the voltage on
the IMON pin exceeds 103 mV. This pin can be left floating when not used.
7.3.1.4 FLTb
This active-low open-drain output pulls low when the TPS24720 has remained in current limit long enough for the
fault timer to expire. The behavior of the FLTb pin depends on the status of the LATCH pin. If the LATCH pin is
held high or left floating, the TPS24720 operates in latch mode. If the LATCH pin is held low, the TPS24720
operates in retry mode. In latch mode, a fault timeout disables the external MOSFET and holds FLTb low. The
latched mode of operation is reset by cycling EN, VCC, or ENSD. In retry mode, a fault timeout first disables the
external MOSFET, next waits sixteen cycles of TIMER charging and discharging, and finally attempts a restart.
This process repeats as long as the fault persists. In retry mode, the FLTb pin is pulled low whenever the
external MOSFET is disabled by the fault timer. In a sustained fault, the FLTb waveform becomes a train of
pulses. The FLTb pin does not assert if the external MOSFET is disabled by EN, ENSD, OV, overtemperature
shutdown, or UVLO. This pin can be left floating when not used.
7.3.1.5 GATE
This pin provides gate drive to the external MOSFET. A charge pump sources 30 µA to enhance the external
MOSFET. A 13.9-V clamp between GATE and VCC limits the gate-to-source voltage, because VVCC is very close
to VOUT in normal operation. During start-up, a transconductance amplifier regulates the gate voltage of M1 to
provide inrush current limiting. The TIMER pin charges timer capacitor CT during the inrush. Inrush current
limiting continues until the V(GATE – VCC) exceeds the Timer Activation Voltage (5.9 V for VVCC = 12 V). Then the
TPS24720 enters into circuit-breaker mode. The Timer Activation Voltage is defined as a threshold voltage.
When V(GATE-VCC) exceeds this threshold voltage, the inrush operation is finished and the TIMER stops sourcing
current and begins sinking current. In the circuit-breaker mode, the current flowing in RSENSE is compared with
the current-limit threshold derived from the MOSFET power-limit scheme (see PROG). If the current flowing in
RSENSE exceeds the current limit threshold, then MOSFET M1 is turned off. The GATE pin is disabled by the
following three mechanisms:
1. GATE is pulled down by an 11-mA current source when
– The fault timer expires during an overload current fault (VIMON > 675 mV)
– VEN is below its falling threshold
– VVCC drops below the UVLO threshold
– VOV is above its rising threshold
2. GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V(VCC –
SENSE) is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an
11-mA sustaining current ensures that the external MOSFET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising
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Feature Description (continued)
threshold or ENSD is pulled low.
GATE remains low in latch mode and attempts a restart periodically in retry mode.
No external resistor should be directly connected from GATE to GND or from GATE to OUT.
7.3.1.6 GND
This pin is connected to system ground.
7.3.1.7 IMON
A resistor connected from this pin to GND scales the current-limit and power-limit settings, as illustrated in
Figure 28. The voltage present at this pin is proportional to the current flowing through sense resistor RSENSE.
This voltage can be used as a means of monitoring current flow through the system. The value of RIMON can be
calculated from Equation 3. This pin should not have a bypass capacitor or any other load except for RIMON.
7.3.1.8 LATCH
This pin determines whether the TPS24720 operates in latch mode or retry mode. Applying a voltage of 2 V to 5
V to this pin or allowing it to float selects latch mode. Tying the pin to ground selects retry mode. In latch mode,
an overload current fault disables the TPS24720 until EN, ENSD, or VCC is cycled. In retry mode, the TPS24720
automatically attempts a restart after every sixteen cycles of TIMER charging and discharging. In a sustained
fault in retry mode, the external MOSFET conducts 3.93% of the time; i.e., the duty ratio is 0.0393. If the LATCH
pin is allowed to float, then its open-circuit voltage is approximately 2.28 V.
7.3.1.9 OUT
This pin allows the controller to measure the drain-to-source voltage across the external MOSFET M1. The
power-good indicator (PGb) relies on this information, as does the power-limiting engine. The OUT pin should be
protected from negative voltage transients by a clamping diode or sufficient capacitors. A Schottky diode of 3 A /
40 V in a SMC package is recommended as a clamping diode for high-power applications. The OUT pin should
be bypassed to GND with a low-impedance ceramic capacitor in the range of 10 nF to 1 µF.
7.3.1.10 OV
This pin is used to program the device overvoltage level. A voltage of more than 1.35 V on this pin turns off the
external MOSFET. A resistor divider connected from VCC to this pin provides overvoltage protection for the
downstream load. This pin should be tied to GND when not used.
7.3.1.11 PGb
This active-low, open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits.
PGb pulls low after the drain-to-source voltage of the FET has fallen below 170 mV and a 3.4-ms deglitch delay
has elapsed. It goes open-drain when VDS exceeds 240 mV. PGb assumes high-impedance status after a 3.4-ms
deglitch delay once VDS of M1 rises up, resulting from GATE being pulled to GND at any of the following
conditions:
• An overload current fault occurs (VIMON > 675 mV).
• A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, i.e., the fast-trip shutdown
threshold has been exceeded.
• VEN is below its falling threshold.
• VENSD is below its threshold.
• VVCC drops below the UVLO threshold.
• VOV is above its rising threshold.
• Die temperature exceeds the OTSD threshold.
This pin can be left floating when not used.
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Feature Description (continued)
7.3.1.12 PROG
A resistor from this pin to GND sets the maximum power permitted in the external MOSFET M1 during inrush. Do
not apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of 4.99 kΩ. To set
the maximum power, use Equation 1,
R
84375
PLIM =
´ SET
RPROG ´ RSENSE RIMON
(1)
where PLIM is the allowed power limit of MOSFET M1. RSENSE is the load-current-monitoring resistor connected
between the VCC pin and the SENSE pin. RPROG is the resistor connected from the PROG pin to GND. Both
RPROG and RSENSE are in ohms and PLIM is in watts. PLIM is determined by the maximum allowed thermal stress of
MOSFET M1, given by Equation 2,
TJ(MAX) - TC(MAX)
PLIM <
RθJC(MAX)
(2)
where TJ(MAX) is the maximum desired transient junction temperature and TC(MAX) is the maximum case
temperature prior to a start or restart. RӨJC(MAX) is the junction-to-case thermal impedance of the pass MOSFET
M1 in units of °C/W. Both TJ(MAX) and TC(MAX) are in °C.
7.3.1.13 SENSE
This pin connects to the negative terminal of RSENSE. It provides a means of sensing the voltage across this
resistor, as well as a way to monitor the drain-to-source voltage across the external FET. The current limit ILIM is
set by Equation 3.
0.675 V ´ RSET
ILIM =
RIMON ´ RSENSE
(3)
A fast-trip shutdown occurs when V(VCC – VSENSE) exceeds 60 mV.
7.3.1.14 SET
A resistor RSET is connected from this pin to the positive terminal of RSENSE. This resistor scales the current limit
and power limit settings. It coordinates with RIMON and RSENSE to determine the current limit value. The value of
RSET can be calculated from Equation 3 (see SENSE).
7.3.1.15 TIMER
A capacitor CT connected from the TIMER pin to GND determines the overload fault timing. TIMER sources 10
µA when an overload is present, and discharges CT at 10 µA otherwise. M1 is turned off when VTIMER reaches
1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period before
the external MOSFET is re-enabled. A minimum timing capacitance of 1 nF is recommended to ensure proper
operation of the fault timer. The value of CT can be calculated from the desired fault time tFLT, using Equation 4.
10 μA
CT =
´ tFLT
1.35 V
(4)
As is explained in the description of the LATCH pin, either latch mode or retry mode occurs if the load current
exceeds the current limit threshold or the fast-trip shutdown threshold, depending on the status of the LATCH
pin. While in latch mode, the TIMER pin continues to charge and discharge the attached capacitor periodically. In
retry mode, the external MOSFET is disabled for sixteen cycles of TIMER charging and discharging. The TIMER
pin is pulled to GND by a 2-mA current source at the end of the 16th cycle of charging and discharging. The
external MOSFET is then re-enabled. The TIMER pin capacitor, CT, can also be discharged to GND during latch
mode or retry mode in the following two ways:
1. A 2-mA current sinks TIMER whenever any of the following occurs:
– VEN is below its falling threshold.
– VVCC drops below the UVLO threshold.
– VOV is above its rising threshold.
2. A 100-kΩ resistor is connected to TIMER and discharges CT at the moment when VENSD drops below its
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Feature Description (continued)
threshold.
TIMER is not affected when the die temperature exceeds the OTSD threshold.
7.3.1.16 VCC
This pin performs three functions. First, it provides biasing power to the integrated circuit. Second, it serves as an
input to the power-on reset (POR) and undervoltage lockout (UVLO) functions. The VCC trace from the
integrated circuit should connect directly to the positive terminal of RSENSE to minimize the voltage sensing error.
Bypass capacitor C1, shown in the typical application diagram on the front page, should be connected to the
positive terminal of RSENSE. A capacitance of at least 10 nF is recommended.
7.4 Device Functional Modes
The TPS24720 provides all the features needed for a positive hot-swap controller. These features include:
• Undervoltage lockout
• Adjustable (system-level) enable
• Turn-on inrush limiting
• High-side gate drive for an external N-channel MOSFET
• MOSFET protection by power limiting
• Adjustable overload timeout, also called an electronic circuit breaker
• Charge-complete indicator for downstream converter coordination
• A choice of latch or automatic restart mode
• A low-power disable mode accessed by holding ENSD low
• MOSFET short detection
• Load overvoltage protection
The typical application diagram, shown on the front page of this datasheet, and oscilloscope plots, shown in
Figure 29 through Figure 31 and Figure 33 through Figure 36, demonstrate many of the functions described
previously.
7.4.1 Board Plug-In
Figure 29 and Figure 30 illustrate the inrush current that flows when a hot swap board under the control of the
TPS24720 is plugged into a system bus. Only the bypass capacitor charge current and small bias currents are
evident when a board is first plugged in. The TPS24720 is held inactive for a short period while internal voltages
stabilize. In this short period, GATE, PROG, and TIMER are held low and PGb, FLTb, and FFLTb are held opendrain. When the voltage on the internal VCC rail exceeds approximately 1.5 V, the power-on reset (POR) circuit
initializes the TPS24720 and a start-up cycle is ready to take place.
GATE, PROG, TIMER, PGb, FLTb and FFTb are released after the internal voltages have stabilized and the
external EN (enable) thresholds have been exceeded. The part begins sourcing current from the GATE pin to
turn on MOSFET M1. The TPS24720 monitors both the drain-to-source voltage across MOSFET M1 and the
drain current passing through it. Based on these measurements, the TPS24720 limits the drain current by
controlling the gate voltage so that the power dissipation within the MOSFET does not exceed the power limit
programmed by the user. The current increases as the voltage across the MOSFET decreases until finally the
current reaches the current limit ILIM.
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Device Functional Modes (continued)
Figure 29. Inrush Mode at Hot-Swap Circuit Insertion
7.4.2 Inrush Operation
After TPS24720 initialization is complete (as described in the Board Plug-In section) and EN is active, GATE is
enabled (VGATE starts increasing). When VGATE reaches the MOSFET M1 gate threshold, a current flows into the
downstream bulk storage capacitors. When this current exceeds the limit set by the power-limit engine, the gate
of the MOSFET is regulated by a feedback loop to make the MOSFET current rise in a controlled manner. This
not only limits the capacitor-charging inrush current but it also limits the power dissipation of the MOSFET to safe
levels. A more complete explanation of the power-limiting scheme is given in the section entitled Action of the
Constant-Power Engine. When GATE is enabled, the TIMER pin begins to charge the timing capacitor CT with a
current of approximately 10 µA. The TIMER pin continues to charge CT until V(GATE – VCC) reaches the timer
activation voltage (5.9 V for VVCC = 12 V). The TIMER then begins to discharge CT with a current of
approximately 10 µA. This indicates that the inrush mode is finished. If the TIMER exceeds its upper threshold of
1.35 V before V(GATE – VCC) reaches the timer activation voltage, the GATE pin is pulled to GND and the hot-swap
circuit enters either latch mode or auto-retry mode, depending upon the status of the LATCH pin (see LATCH).
The power limit feature is disabled once the inrush operation is finished and the hotswap circuit becomes a
circuit breaker. The TPS24720 turns off the MOSFET M1 after a fault timer period once the load exceeds the
current limit threshold.
7.4.3 Action of the Constant-Power Engine
Figure 30 illustrates the operation of the constant-power engine during start-up. The circuit used to generate the
waveforms of Figure 30 was programmed to a power limit of 29.3 W by means of the resistor connected between
PROG and GND. At the moment current begins to flow through the MOSFET, a voltage of 12 V appears across
it (input voltage VVCC = 12 V), and the constant-power engine therefore allows a current of 2.44 A (equal to 29.3
W divided by 12 V) to flow. This current increases in inverse ratio as the drain-to-source voltage diminishes, so
as to maintain a constant dissipation of 29.3 W. The constant-power engine adjusts the current by altering the
reference signal fed to the current limit amplifier. The lower part of Figure 31 shows the measured power
dissipated within the MOSFET, labeled FET PWR, remaining substantially constant during this period of
operation, which ends when the current through the MOSFET reaches the current limit ILIM. This behavior can be
considered a form of foldback limiting, but unlike the standard linear form of foldback limiting, it allows the power
device to operate near its maximum capability, thus reducing the start-up time and minimizing the size of the
required MOSFET.
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Device Functional Modes (continued)
I_IN: Input Current, 2 A/div
GAT: Voltage on GATE Pin, 5 V/div
V_DS: Drain-to-Source Voltage of M1, 5 V/div
TIMER: Voltage on TIMER Pin, 500 mV/div
FET_PWR: Power on M1 (product of V_DS and I_IN), 19 W/div
Time: 10 ms/div
C002
Figure 30. Computation of M1 Power Stress During Startup
7.4.4 Circuit Breaker and Fast Trip
The TPS24720 monitors load current by sensing the voltage across RSENSE. The TPS24720 incorporates two
distinct thresholds: a current-limit threshold and a fast-trip threshold.
The functions of circuit breaker and fast-trip turn off are shown in Figure 31 through Figure 34.
Figure 31 shows the behavior of the TPS24720 when a fault in the output load causes the current passing
through RSENSE to increase to a value above the current limit but less than the fast-trip threshold. When the
current exceeds the current-limit threshold, a current of approximately 10 μA begins to charge timing capacitor
CT. If the voltage on CT reaches 1.35 V, then the external MOSFET is turned off. The TPS24720 either latches
off or commences a restart cycle, depending upon the state of the LATCH pin. In either event, fault pin FLTb
pulls low to signal a fault condition. Overload between the current limit and the fast-trip threshold is permitted for
this period. This shutdown scheme is sometimes called an electronic circuit breaker.
The fast-trip threshold protects the system against a severe overload or a dead short circuit. When the voltage
across the sense resistor RSENSE exceeds the 60-mV fast-trip threshold, the GATE pin immediately pulls the
external MOSFET gate to ground with approximately 1 A of current. This extremely rapid shutdown may
generate disruptive transients in the system, in which case a low-value resistor inserted between the GATE pin
and the MOSFET gate can be used to moderate the turn off current. The fast-trip circuit holds the MOSFET off
for only a few microseconds, after which the TPS24720 turns back on slowly, allowing the current-limit feedback
loop to take over the gate control of M1. Then the hot-swap circuit goes into latch mode or auto-retry mode,
depending on pre-determined conditions. Figure 33 and Figure 34 illustrate the behavior of the system when the
current exceeds the fast-trip threshold.
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Device Functional Modes (continued)
Figure 31. Circuit-Breaker Mode During Overload Condition
ILIMIT
M1
RSENSE
RGATE
RSET
SET
VCC
12
7
SENSE
GATE
11
10
OUT
8
+
60 mV
–
Server
Amplifier
+
–
Fast Trip
Comparator
A1
60 μA
+
675 mV
IMON
RIMON
6
PROG
VCP
–
Current
Limit Amp
2
RPROG
A2
30 μA
+
B0439-01
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Figure 32. Partial Diagram of the TPS24720 With Selected External Components
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Device Functional Modes (continued)
Figure 33. Current Limit During Output-Load Short-Circuit
Condition (Overview)
Figure 34. Current Limit During Output-Load Short-Circuit
Condition (Onset)
7.4.5 Automatic Restart
If LATCH is connected to GND, then the TPS24720 automatically initiates a restart after a fault has caused it to
turn off the external MOSFET M1. Internal control circuits use CT to count 16 cycles before re-enabling M1 as
shown in Figure 35. This sequence repeats if the fault persists. The timer has a 1 : 1 charge-to-discharge current
ratio. For the very first cycle, the TIMER pin starts from 0 V and rises to the upper threshold of 1.35 V and
subsequently falls to 0.35 V before restarting. For the following 16 cycles, 0.35 V is used as the lower threshold.
This small duty cycle often reduces the average short-circuit power dissipation to levels associated with normal
operation and eliminates special thermal considerations for surviving a prolonged output short.
Figure 35. Auto-Restart Cycle Timing
Figure 36. Latch After Overload Fault
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Device Functional Modes (continued)
7.4.6 PGb, FLTb, and Timer Operations
The open-drain PGb output provides a deglitched end-of-inrush indication based on the voltage across M1. PGb
is useful for preventing a downstream dc/dc converter from starting while its input capacitor COUT is still charging.
PGb goes active-low about 3.4 ms after COUT is charged. This delay allows M1 to fully turn on and any transients
in the power circuits to end before the converter starts up. This type of sequencing prevents the downstream
converter from demanding full current before the power-limiting engine allows the MOSFET to conduct the full
current set by the current limit ILIM. Failure to observe this precaution may prevent the system from starting. The
pullup resistor shown on the PGb pin in the typical application diagram on the front page is illustrative only; the
actual connection to the converter depends on the application. The PGb pin may indicate that inrush has ended
before the MOSFET is fully enhanced, but the downstream capacitor will have been charged to substantially its
full operating voltage. Care should be taken to ensure that the MOSFET on-resistance is sufficiently small to
ensure that the voltage drop across this transistor is less than the minimum power-good threshold of 140 mV.
After the hot-swap circuit successfully starts up, the PGb pin can return to a high-impedance status whenever the
drain-to-source voltage of MOSFET M1 exceeds its upper threshold of 340 mV, which presents the downstream
converters a warning flag. This flag may occur as a result of overload fault, output short fault, input overvoltage,
higher die temperature, or the GATE shutdown by UVLO, EN or ENSD.
FLTb is an indicator that the allowed fault-timer period during which the load current can exceed the programmed
current limit (but not the fast-trip threshold) expires. The fault timer starts when a current of approximately 10 μA
begins to flow into the external capacitor, CT, and ends when the voltage of CT reaches TIMER upper threshold,
i.e., 1.35 V. FLTb pulls low at the end of the fault timer. Otherwise, FLTb assumes a high-impedance state.
The fault-timer state requires an external capacitor CT connected between the TIMER pin and GND pin. The
duration of the fault timer is the charging time of CT from 0 V to its upper threshold of 1.35 V. The fault timer
begins to count under any of the following three conditions:
1. In the inrush mode, TIMER begins to source current to the timer capacitor, CT, when MOSFET M1 is
enabled. TIMER begins to sink current from the timer capacitor, CT when V(GATE – VCC) exceeds the timer
activation voltage (see the Inrush Operation section). If V(GATE – VCC) does not reach the timer activation
voltage before TIMER reaches 1.35 V, then the TPS24720 disables the external MOSFET M1. After the
MOSFET turns off, the timer goes into either latch mode or retry mode, depending on the LATCH pin status.
2. In an overload fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of
1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground.
After the fault timer period, TIMER may go into latch mode or retry mode, depending on the LATCH pin
status.
3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the programmed current limits following a fast-trip shutdown of M1. When the timer capacitor voltage
reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the
GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode or retry mode,
depending on the LATCH pin status.
If the fault current drops below the programmed current limit within the fault timer period, VTIMER decreases and
the pass MOSFET remains enabled.
The behaviors of TIMER are different in the latch mode and retry mode. If the timer capacitor reaches the upper
threshold of 1.35 V, then:
• In latch mode, the TIMER pin continues to charge and discharge the attached capacitor periodically until
TPS24720 is disabled by UVLO, EN, ENSD, or OV, as shown in Figure 36.
• In retry mode, TIMER charges and discharges CT between the lower threshold of 0.35 V and the upper
threshold of 1.35 V for sixteen cycles before the TPS24720 attempts to re-start. The TIMER pin is pulled to
GND at the end of the 16th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the initial
half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload fault is
removed or the TPS24720 is disabled by UVLO, EN, ENSD, or OV.
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Device Functional Modes (continued)
7.4.7 Overtemperature Shutdown
The TPS24720 includes a built-in overtemperature shutdown circuit designed to disable the gate driver if the die
temperature exceeds approximately 140°C. An overtemperature condition also causes the FLTb, FFLTb and
PGb pins to go to high-impedance states. Normal operation resumes once the die temperature has fallen
approximately 10°C.
7.4.8 Start-Up of Hot-Swap Circuit by VCC or EN
The connection and disconnection between a load and the input power bus are controlled by turning on and
turning off the MOSFET, M1.
The TPS24720 has two ways to turn on MOSFET M1:
• Increasing VVCC above UVLO upper threshold while EN is already higher than its upper threshold sources
current to the GATE pin. After an inrush period, the TPS24720 fully turns on MOSFET M1.
• Increasing EN above its upper threshold while VVCC is already higher than the UVLO upper threshold sources
current to the GATE pin. After an inrush period, the TPS24720 fully turns on MOSFET M1.
The EN pin can be used to start up the TPS24720 at a selected input voltage VVCC.
To isolate the load from the input power bus, the GATE pin sinks current and pulls the gate of MOSFET M1 low.
The MOSFET can be disabled by any of the following conditions: UVLO, EN, ENSD, load current above the
current-limit threshold, hard short at load, OV, or OTSD. Three separate mechanisms pull down the GATE pin:
1. GATE is pulled down by an 11-mA current source when any of the following occurs.
– The fault timer expires during an overload current fault (VIMON > 675 mV).
– VEN is below its falling threshold.
– VVCC drops below the UVLO threshold.
– VOV is above its rising threshold.
2. GATE is pulled down by a 1-A current source for 13.5 μs when a hard output short circuit occurs and V(VCC –
SENSE) is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an
11-mA sustaining current ensures that the external MOSFET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising
threshold or ENSD is pulled low.
7.4.9 Minimization of Power Dissipation at STANDY by ENSD
The ENSD pin enables the use of TPS24720 in applications requiring a low-power standby mode. When this pin
is pulled below its threshold voltage, all the internal circuitry is switched off and the GATE pin is discharged to
GND through a 20-kΩ resistor. Thus, the MOSFET is disabled and power consumption is kept to a minimum.
The correct procedure to go into standby mode is first to shut down the TPS24720 by using the EN pin and then
to pull the ENSD pin low.
7.4.10 Fault Detection of MOSFET Short With FFLTb
One of the salient features of the TPS24720 is the detection of short-circuited MOSFETs by the FFLTb pin. The
FFLTb is pulled low to indicate a FET short if all the following conditions occur.
• EN is below its threshold voltage.
• VVCC is above the UVLO threshold.
• VIMON > 103 mV.
The fact that GATE is turned off but current is still flowing through RSENSE indicates a drain-to-source short.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS24720 is a hotswap used to manage inrush current and provide load fault protection. When designing a
hotswap, three key scenarios should be considered:
• Start-up
• Output of a hotswap is shorted to ground when the hotswap is on. This is often referred to as a hot-short.
• Powering-up a board when the output and ground are shorted. This is usually called a start-into-short.
Each of these scenarios place stress on the hotswap MOSFET. Take special care when designing the hotswap
circuit to keep the MOSFET within its SOA. The following design example is provided as a guide. Use the
TPS24720 Design Calculator (SLVC563) to assist with the detailed design equation calculations.
8.2 Typical Application
This section provides an application example utilizing power limited start-up and MOSFET SOA protection. The
design parameters are listed in the Design Requirements section and represent a more moderate level of fault
current. For more stringent current levels, refer to either the TPS24720EVM (SLUU458) (25 A design) or the
calculator tool (SLVC563) (50 A design).
RSENSE
2 mΩ
VIN
VOUT
COUT
470 μF
C1
0.1 μF
RSET
51.1 Ω
R7
R1
90.9 kΩ
M1
CSD16403Q5
SET
3V
RGATE
10 Ω
SENSE
GATE
R4
3.01 kΩ
OUT
R5
3.01 kΩ
R6
3.01 kΩ
FLTb
VCC
EN
PGb
R2
2.94 kΩ
TPS24720
FFLTb
OV
ENSD
IMON
PROG
LATCH
RPROG
53.6 kΩ
R3
10 kΩ
GND
TIMER
CT
56 nF
RIMON
1.43 kΩ
VUVLO = 10.83 V
VOV = 14.02 V
ILMT = 12 A
tFAULT = 7.56 ms
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Figure 37. Typical Application (12 V at 10 A)
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters shown in Table 1.
Table 1. Design Parameters
PARAMETER
VALUE
Input voltage
12 V ±2V
Maximum operating load current
10 A
Operating temperature
20°C —50°C
Fault trip current
12 A
Load capacitance
470 µF
8.2.2 Detailed Design Procedure
8.2.2.1 Power-Limited Start-Up
This design example assumes a 12-V system voltage with an operating tolerance of ±2 V. The rated load current
is 10 A, corresponding to a dc load of 1.2 Ω. If the current exceeds 12 A, then the controller should shut down
and then attempt to restart. Ambient temperatures may range from 20°C to 50°C. The load has a minimum input
capacitance of 470 μF. Figure 38 shows a simplified system block diagram of the proposed application.
This design procedure seeks to control the junction temperature of MOSFET M1 under both static and transient
conditions by proper selection of package, cooling, rDS(on), current limit, fault timeout, and power limit. The design
procedure further assumes that a unit running at full load and maximum ambient temperature experiences a brief
input power interruption sufficient to discharge COUT, but short enough to keep M1 from cooling. A full COUT
recharge then takes place. Adjust this procedure to fit the application and design criteria.
PROTECTION
RSENSE
0.1 μF
LOAD
M1
0.1 μF
RSET
RGATE
Specifications (at Output):
Peak Current Limit = 12 A
Nominal Current = 10 A
COUT
470 μF
OUT
GATE
SENSE
SET
VCC
12-V Main Bus Supply
RLOAD
1.2 W
IMON
GND
TPS24720
RIMON
TIMER
CT
B0440-01
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Figure 38. Simplified Block Diagram of the System Constructed in the Design Example
8.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON
The recommended range of the current-limit threshold voltage, V(VCC – SENSE), extends from 10 mV to 42 mV.
Values near the low threshold of 10 mV may be affected by system noise. Values near the upper threshold of
42 mV may be too close to the minimum fast-trip threshold voltage of 52 mV. Values near the middle of this
range help minimize both concerns.
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To achieve high efficiency, the power dissipation in RSENSE must be kept to a minimum. A RSENSE of 2 mΩ
develops a voltage of 24 mV at the specified peak current limit of 12 A, while dissipating only 200 mW at the
rated 10-A current. This represents a 0.17% power loss.
For best performance, a current of approximately 0.5 mA (referring to the RECOMMENDED OPERATING
CONDITIONS table) should flow into the SET pin and out of the IMON pin when the TPS24720 is in current limit.
The voltage across RSET nominally equals the voltage across RSENSE, or 24 mV. Dividing 24 mV by 0.5 mA gives
a recommended value of RSET of 48 Ω. A 51.1-Ω, 1% resistor was chosen. Using Equation 3, the value of RIMON
must equal 1437 Ω, or as near as practically possible. A 1.43-kΩ, 1% resistor was chosen.
0.675 V ´ RSET
RIMON =
,
ILIM ´ RSENSE
therefore,
RIMON =
0.675 V ´ 51.1 W
= 1437 W
12 A ´ 2 mW
(5)
8.2.2.1.2 STEP 2. Choose MOSFET M1
The next design step is to select M1. The TPS24720 is designed to use an N-channel MOSFET with a gate-tosource voltage rating of 20 V.
Devices with lower gate-to-source voltage ratings can be used if a Zener diode is connected so as to limit the
maximum gate-to-source voltage the transistor sees.
The next factor to consider is the drain-to-source voltage rating, VDS(MAX), of the MOSFET. Although the
MOSFET only sees 12 V dc, it may experience much higher transient voltages during extreme conditions, such
as the abrupt shutoff that occurs during a fast trip. A TVS may be required to limit inductive transients under such
conditions. A transistor with a VDS(MAX) rating of at least twice the nominal input power-supply voltage is
recommended regardless of whether a TVS is used or not.
Next select the on-resistance of the transistor, rDS(on). The maximum on-resistance must not generate a voltage
greater then the minimum power-good threshold voltage of 140 mV. Assuming a current limit of 12 A, a
maximum rDS(on) of 11.67 mΩ is required. Also consider the effect of rDS(on) on the maximum operating
temperature TJ(MAX) of the MOSFET. Equation 6 computes the value of rDS(on)(MAX) at a junction temperature of
TJ(MAX). Most manufacturers list rDS(on)(MAX) at 25°C and provide a derating curve from which values at other
temperatures can be derived. Compute the maximum allowable on-resistance, rDS(on)(MAX), using Equation 6.
TJ(MAX) - TA(MAX)
rDS(on)(MAX) =
,
IMAX2 ´ RqJA
therefore,
rDS(on)(MAX) =
150°C - 50°C
(12 A )2 ´ 51°C / W
= 13.6 mW
(6)
Taking these factors into consideration, the TI CSD16403Q5 was selected for this example. This transistor has a
VGS(MAX) rating of 16 V, a VDS(MAX) rating of 25 V, and a maximum rDS(on) of 2.8 mΩ at room temperature. During
normal circuit operation, the MOSFET can have up to 10 A flowing through it. The power dissipation of the
MOSFET equates to 0.24 W and an 9.6°C rise in junction temperature. This is well within the data sheet limits for
the MOSFET. The power dissipated during a fault (e.g., output short) is far larger than the steady-state power.
The power handling capability of the MOSFET must be checked during fault conditions.
8.2.2.1.3 STEP 3. Choose Power-Limit Value, PLIM, and RPROG
MOSFET M1 dissipates large amounts of power during inrush. The power limit PLIM of the TPS24720 should be
set to prevent the die temperature from exceeding a short-term maximum temperature, TJ(MAX)2. The short-term
TJ(MAX)2 could be set as high as 150°C while still leaving ample margin to the usual manufacturer’s rating of
175°C. Equation 7 is an expression for calculating PLIM,
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(
TJ(MAX)2 - é IMAX2 ´ r DS(on) ´ RqCA
ë
£ 0.8 ´
RqJC
) +T
ù
A(MAX) û
,
therefore,
PLIM £ 0.8 ´
130°C - é
ëê
((12 A ) ´ 0.002 W ´ (51°C / W - 1.8°C / W )) + 50°Cûúù = 29.3 W
2
1.8°C / W
(7)
where RθJC is the junction-to-case thermal resistance of the MOSFET, rDS(on) is the its resistance at the maximum
operating temperature, and the factor of 0.8 represents the tolerance of the constant-power engine. For an
ambient temperature of 50°C, the calculated maximum PLIM is 29.3 W. From Equation 1, a 53.6-kΩ, 1% resistor
is selected for RPROG (see Equation 8).
R SET
84375
RPROG =
´
PLIM ´ R SENSE R IMON
therefore,
RPROG =
84375
51.1W
´
= 51.45 kW
29.3 W ´ 0.002W 1430W
(8)
Power limit fold back (PLIM-FB) is the ratio of operating current limit (ILIM) and minimum power limited (regulated)
current (when VOUT = 0 V). Degradation of programmed power limit (PLIM) accuracy and start up issues may
occur if PLIM-FB is too large. Equation 9 calculates VSNS-PL_MIN (minimum sense voltage during power limit) and
PLIM-FB. To ensure reliable operation, verify that PLIM-FB < 10 and VSNS,PL,MIN > 3 mV.
P ´ RSENSE 29.3 W ´ 2 mW
=
= 4.19 mV (> 3 mV)
VSNS -PL _ MIN = LIM
VIN _ MAX
14 V
PLIM-FB =
ILIM ´ VIN _ MAX
PLIM
=
12 A ´ 14 V
= 5.73 (< 10)
29.3 W
(9)
8.2.2.1.4 STEP 4. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT
The maximum output voltage rise time, tON, set by timer capacitor CT must suffice to fully charge the load
capacitance COUT without triggering the fault circuitry. Equation 10 defines tON for two possible inrush cases.
Assuming that only the load capacitance draws current during startup,
COUT ´ PLIM
2 ´ ILIM2
+
COUT ´ VVCC(MAX)2
2 ´ PLIM
-
COUT ´ VVCC(MAX)
ILIM
if
PLIM < ILIM ´ VVCC(MAX)
t ON =
COUT ´ VVCC(MAX)
ILIM
if
PLIM > ILIM ´ VVCC(MAX)
therefore,
t ON =
470 μF ´ 29.3 W
2
2 ´ (12 A )
2
+
470 μF ´ (12 V )
2 ´ 29.3 W
-
470 μF ´ 12 V
= 0.614 ms
12 A
(10)
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The next step is to determine the minimum fault-timer period. In Equation 10, the output rise time is tON. This is
the amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer
uses the difference between the input voltage and the gate voltage to determine if the TPS24720 is still in inrush
limit. The fault timer continues to run until VGS rises 5.9 V (for VVCC = 12 V) above the input voltage. Some
additional time must be added to the charge time to account for this additional gate voltage rise. The minimum
fault time can be calculated using Equation 11,
5.9 V ´ CISS
tFLT = t ON +
,
IGATE
therefore,
tFLT = 0.614 ms +
5.9 V ´ 2040 pF
= 1.22 ms
20 μA
(11)
where CISS is the MOSFET input capacitance and IGATE is the minimum gate sourcing current of TPS24720, or
20 μA. Using the example parameters and the CSD16403Q5 data sheet in Equation 11 leads to a minimum fault
time of 1.22 ms. This time is derived considering the tolerances of COUT, CISS, ILIM, PLIM, IGATE, and VVCC(MAX).
The fault timer must be set to a value higher than 1.22 ms to avoid turning off during start-up, but lower than any
maximum fault time limit determined by the device SOA curve (see Figure 39) derated for operating junction
temperature.
For this example, select 7 ms to allow for variation of system parameters such as temperature, load, component
tolerance, and input voltage. The timing capacitor is calculated in Equation 12 as 52 nF. Selecting the nexthighest standard value, 56 nF, yields a 7.56-ms fault time.
10 μA
CT =
´ tFLT ,
1.35 V
therefore,
CT =
10 μA
´ 7 ms = 52 nF
1.35 V
(12)
8.2.2.1.5 STEP 5. Calculate the Retry-Mode Duty Ratio
In retry mode, the TPS24720 is on for one charging cycle and off for 16 charge/discharge cycles, as can be seen
in Figure 35. The first CT charging cycle is from 0 V to 1.35 V, which gives 7.56 ms. The first CT discharging
cycle is from 1.35 V to 0.35 V, which gives 5.6 ms. Therefore, the total time is 7.56 ms + 33 x 5.6 ms = 192.36
ms. As a result, the retry mode duty ratio is 7.56 ms/192.36 ms = 3.93%.
8.2.2.1.6 STEP 6. Select R1, R2, and R3 for UV and OV
Next, select the values of the OV and UV resistors, R1, R2, and R3, as shown in the typical application diagram
on the front page. From the TPS24720 electrical specifications, VOVTHRESH = 1.35 V and VENTHRESH = 1.35 V. VOV
is the overvoltage trip voltage, which in this case is 14 V. VUV is the undervoltage trip voltage, which for this
example equals 10.8 V.
R3
VENTHRESH =
´ VOV
R1 + R2 + R3
(13)
VUVTHRESH =
R 2 + R3
´ VUV
R1 + R2 + R3
(14)
Assume R3 is 1 kΩ and use Equation 13 to solve for (R2 + R3). Use Equation 14 and the (R2 + R3) from
Equation 13 to solve for R2 and finally for R3. From Equation 13, (R2 + R3) = 9370.4 Ω. From Equation 14,
R2 = 296 Ω and R1 = 9.074 kΩ. Scaling all three resistors by a factor of ten to use less supply current for these
voltage references and using standard 1% resistor values gives R1 = 90.9 kΩ, R2 = 2.94 kΩ, and R3 = 10 kΩ.
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8.2.2.1.7 STEP 7. Choose RGATE, R4, R5, R6, and C1
In the typical application diagram on the front page, the gate resistor, RGATE, is intended to suppress highfrequency oscillations. A resistor of 10 Ω serves for most applications, but if M1 has a CISS below 200 pF, then 33
Ω is recommended. Applications with larger MOSFETs and very short wiring may not require RGATE. R4, R5, and
R6 are required only if PGb, FLTb, and FFLTb are used; these resistors serve as pullups for the open-drain
output drivers. The current sunk by each of these pins should not exceed 2 mA ( referring to the Recommended
Operating Conditions). C1 is a bypass capacitor to help control transient voltages, unit emissions, and local
supply noise while in the disabled state. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is
recommended.
8.2.2.2 Additional Design Considerations
8.2.2.2.1 Use of PGb
Use the PGb pin to control and coordinate a downstream dc/dc converter. If this is not done, then a long time
delay is needed to allow COUT to fully charge before the converter starts. An undesirable latch-up condition can
be created between the TPS24720 output characteristic and the dc/dc converter input characteristic if the
converter starts while COUT is still charging; using the PGb pin is one way to avoid this.
8.2.2.2.2 Output Clamp Diode
Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a
current-limit event. The OUT pin ratings can be satisfied by connecting a diode from OUT to GND. The diode
should be selected to control the negative voltage at the full short-circuit current. Schottky diodes are generally
recommended for this application.
8.2.2.2.3 Gate Clamp Diode
The TPS24720 has a relatively well-regulated gate voltage of 12 V–15.5 V with a supply voltage VVCC higher
than 4 V. A small clamp Zener from gate to source of M1 is recommended if VGS of M1 is rated below 12 V. A
series resistance of several hundred ohms or a series silicon diode is recommended to prevent the output
capacitance from discharging through the gate driver to ground.
8.2.2.2.4 High-Gate-Capacitance Applications
Gate voltage overstress and abnormally large fault-current spikes can be caused by large gate capacitance. An
external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M1
exceeds about 4000 pF.
8.2.2.2.5 Bypass Capacitors
It is a good practice to provide low-impedance ceramic capacitor bypassing of the VCC and OUT pins. Values in
the range of 10 nF to 1 µF are recommended. Some system topologies are insensitive to the values of these
capacitors; however, some are not and require minimization of the value of the bypass capacitor. Input
capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the lowimpedance power bus when inserted. This stresses the connector contacts and causes a short voltage sag on
the input bus. Small amounts of capacitance (e.g., 10 nF to 0.1 µF) are often tolerable in these systems.
8.2.2.2.6 Output Short-Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
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8.2.3 Application Curve
IDS – Drain-to-Source Current – A
1k
100
1ms
10
10ms
100ms
Area Limited
by RDS(on)
1
1s
0.1
Single Pulse
RθJA = 94ºC/W (min Cu)
0.01
0.01
0.1
DC
1
10
100
VDS – Drain-to-Source Voltage – V
G009
Figure 39. CSD16403Q5 SOA Curve
9 Power Supply Recommendations
Use a 10-nF to 1-μF ceramic capacitor to bypass the VCC pin to GND. When the input bus power feed is
inductive, then a transient voltage suppressor (TVS) may also be required.
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10 Layout
10.1 Layout Guidelines
TPS24720 applications require careful attention to layout to ensure proper performance and to minimize
susceptibility to transients and noise. In general, all traces should be as short as possible, but the following list
deserves first consideration:
• Decoupling capacitors on VCC pin should have minimal trace lengths to the pin and to GND.
• Traces to SET and SENSE must be short and run side-by-side to maximize common-mode rejection. Kelvin
connections should be used at the points of contact with RSENSE (see Figure 40).
• SET runs must be short on both sides of RSET.
• Power path connections should be as short as possible and sized to carry at least twice the full-load current,
more if possible.
• Connections to GND and IMON pins should be minimized after the previously described connections have
been placed.
• The device dissipates low power, so soldering the thermal pad to the board is not a requirement. However,
doing so improves thermal performance and reduces susceptibility to noise.
• Protection devices such as snubbers, TVS, capacitors, or diodes should be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, the
protection Schottky diode shown in the typical application diagram on the front page of the data sheet should
be physically close to the OUT pin.
10.2 Layout Example
LOAD CURRENT
PATH
LOAD CURRENT
PATH
RSENSE
SET
RSET
VCC
SET
SENSE
RSET
TPS24720
TPS24720
Method 1
Method 2
M0217-01
Figure 40. Recommended RSENSE Layout
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Product Folder Links: TPS24720
31
TPS24720
SLVSAL1E – MARCH 2011 – REVISED APRIL 2016
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
Using the TPS24720EVM, SLUU458.
TPS24720 Design Calculator, SLVC563
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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Product Folder Links: TPS24720
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS24720RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
24720
TPS24720RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
24720
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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