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TPS24750, TPS24751
SLVSC87C – OCTOBER 2013 – REVISED DECEMBER 2018
TPS2475x 12-A eFuse Circuit Protector with Current Monitor
1 Features
3 Description
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The TPS2475x provide highly integrated load
protection for 2.5 V to 18 V applications. The devices
integrate a hot swap controller and a power MOSFET
in a single package for small form factor applications.
These devices protect source, load and internal
MOSFET from potentially damaging events. During
startup, load current and MOSFET power dissipation
are limited to user-selected values. After startup,
currents above the user-selected limit will be allowed
to flow until programmed timeout – except in extreme
overload events when load is immediately
disconnected from source.
1
2.5 V to 18 V Bus Operation
Continuous Current up to 12 A
Integrated MOSFET with RDS(on) of 3 mΩ (Typical)
Programmable Current Limit
Programmable FET SOA Protection
High ILimit Accuracy from 10 mA to 12 A
Programmable Fault Timer
Fast Breaker for Short-Circuit Protection
Programmable VOUT Slew Rate, UV and OV
Power-Good and Fault Outputs
Analog Load Current Monitor
Thermal Shutdown
UL 2367 Recognized – File No. E339631
2 Applications
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Server
High Current Load Switch
Communications Equipment
Plug-In Modules
RAID Systems
Base Stations
Fan Control
Programmable FET SOA protection ensures the
internal MOSFET operates within its safe operating
area (SOA) at all times and the load starts up at a
defined ramp rate. This enhances the internal
MOSFET performance while improving system
reliability. Power good, Fault, and current monitor
outputs are provided for system status monitoring and
downstream load control.
The devices are available in a 36-pin, 7-mm × 3.5mm, QFN (RUV) package and fully specified over the
–40°C to +125°C operating junction temperature.
Device Information(1)
PART NUMBER
TPS24750
TPS24751
PACKAGE
VQFN
BODY SIZE (NOM)
7.00 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Schematic (12 V at 10 A)
Transient Output Short Circuit Response
SENSE DRAIN
OUT
FLT
PG
IMON
10k
PROG
GND
TIMER
15k
RPROG
CT
GATE
64.9k
47nF
CLOAD
R2
OV
1.58k
470mF
Output to Voltage Bus or
DC/DC Converter
VCC SET
RIMON
130k
EN
R3
Input Voltage Bus
R1
0.002
RSET
51.1
5 A/div 5 V/div 500 mV/div
10 V/div
Rsense
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS24750, TPS24751
SLVSC87C – OCTOBER 2013 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
6
7.1
7.2
7.3
7.4
7.5
7.6
6
6
6
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 14
Detailed Descriptions .......................................... 15
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description ................................................
Device Functional Modes........................................
15
15
16
19
10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Application ................................................ 26
10.3 System Examples ................................................. 33
11 Power Supply Recommendations ..................... 35
11.1 Transient Thermal Impedance .............................. 35
12 Layout................................................................... 36
12.1 Layout Guidelines ................................................. 36
12.2 Layout Example .................................................... 36
13 Device and Documentation Support ................. 38
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Export Control Notice............................................
Glossary ................................................................
38
38
38
38
38
38
39
39
14 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2016) to Revision C
•
Page
Added UL 2367 Recognized – File No. E339631 to the Features section ............................................................................ 1
Changes from Revision A (September 2015) to Revision B
Page
•
Added designator C1 to Figure 41 ....................................................................................................................................... 27
•
Updated STEP 5. Select R1, R2, and R3 for UV and OV section ........................................................................................ 30
Changes from Original (October 2013) to Revision A
Page
•
Added the ESD Ratings table, Detailed Descriptions, Feature Description, Device Functional Modes, Application
and Implementation, Power Supply Recommendations, Device and Documentation Support, and Mechanical,
Packaging, and Orderable Information................................................................................................................................... 1
•
Deleted Features "FET short detection (TPS24752, TPS24753)" ........................................................................................ 1
•
Changed the Application Schematic image. Deleted CVIN and D1 ......................................................................................... 1
•
Deleted devices TPS24752 and TPS24753 from the data sheet........................................................................................... 4
•
Deleted list item from the Overview section: "Internal MOSFET short detection (TPS24752/3 only)"................................. 15
•
Removed notes for pin 30 and 31 from the Functional Block Diagram................................................................................ 15
•
Deleted section Fault Detection of Internal Mosfet Short ..................................................................................................... 25
•
Changed Figure 40. Deleted CVIN and D1 ............................................................................................................................ 26
•
Changed text in STEP 3. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT From: "maximum
steady state junction temperature (TJDMAX = TA(MAX) + ILIM2 x R(DS)ON)." To: " maximum steady state junction
temperature (TJDMAX = TA(MAX) + ILIM2 x R(DS)ON x RθJA)." ....................................................................................................... 29
•
Changed Figure 46 and Figure 47. Deleted CVIN and D1..................................................................................................... 33
•
Added text and Figure 48 to System Examples ................................................................................................................... 34
•
Changed Figure 51 .............................................................................................................................................................. 36
2
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•
SLVSC87C – OCTOBER 2013 – REVISED DECEMBER 2018
Added Figure 52 .................................................................................................................................................................. 37
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SLVSC87C – OCTOBER 2013 – REVISED DECEMBER 2018
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5 Device Comparison Table
Part Number
Operating Voltage
Range
Function
TPS24750RUV
2.5 V-18 V
TPS24751RUV
2.5 V-18 V
Fault Response
Status
Integrated hot swap protector
Latch
Active
Integrated hot swap protector
Auto retry
Active
6 Pin Configuration and Functions
OUT
OUT
OUT
OUT
25
24
23
22
21
20
19
32
GND
EN
33
PROG
34
TIMER
35
DRAIN
GND
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
Thermal pad-2
Thermal pad-1
6
7
8
IMON
SET
GND
DRAIN
OUT
OUT
OUT
9
10
11
12
13
OUT
5
OUT
4
OUT
3
OUT
2
OUT
1
OV
36
GND
18
GATE
26
17
SENSE
27
16
DRAIN
28
15
GND
29
14
VCC
30
OUT
FLTb
31
OUT
PGb
TPS24750, TPS24751 RUV Package
36-Pin VQFN
Top View
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
5, 14-18, 27
I
The drain of the internal pass MOSFET. Connect to a terminal of current sense resistor in the
power path
EN
33
I
Active high enable input. Logic input. Connects to resistor divider
FLTb
30
I
Active-low, open-drain output indicates overload fault timer has turned internal FET off
GATE
25
I/O
GND
4, 28, 32, 36
GND
IMON
2
O
Load current analog and current limit program point. Connect RIMON to ground
OUT
6-13, 19-24
I/O
Internally connect to the source of internal pass MOSFET. Connect to output capacitors and load
OV
1
I
Overvoltage comparator input. Connects to resistor divider. GATE is pulled low when OV exceeds
the threshold
Pad-1
—
—
Tied to GND
Pad-2
—
—
Tied to DRAIN
PGb
31
O
Active-low, open-drain power good indicator. Status is determined by the voltage across the
MOSFET
DRAIN
4
Gate driver output for the internal MOSFET
Ground
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SLVSC87C – OCTOBER 2013 – REVISED DECEMBER 2018
Pin Functions (continued)
PIN
NAME
NO.
TYPE
DESCRIPTION
PROG
34
I
Power-limiting programming pin. A resistor from this pin to GND sets the maximum power
dissipation for the internal pass MOSFET
SENSE
26
I
Current sensing input for resistor shunt from VCC to SENSE. Connect to a terminal of current
sense resistor
Current limit programming set pin. A resistor is connected from this pin to VCC
SET
3
I
TIMER
35
I/O
VCC
29
I
A capacitor connected from this pin to GND provides a fault timing function
Input voltage sense and power supply
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SLVSC87C – OCTOBER 2013 – REVISED DECEMBER 2018
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, all voltages referred to GND (unless otherwise noted)
Input voltage
Sink current
MAX
–0.3
30
OV
–0.3
20
PROG (2)
–0.3
3.6
[SET, SENSE] to VCC
–0.3
0.3
IMON, TIMER
–0.3
5
TSTG
Storage temperature
V
mA
Internally limited
IMON
Maximum junction temperature
UNIT
5
PROG
TJ
(2)
MIN
DRAIN, EN, FLTb (2), GATE, OUT, PGb (2), SENSE, SET (2), VCC
FLTb, PGb
Source current
(1)
(1)
5
mA
150
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Do not apply voltage directly to these pins.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
OV
Input voltage
(1)
(2)
(3)
MAX
0
16
UNIT
2.5
18
EN, FLTb, GATE (2), PGb, OUT (2), DRAIN (2)
0
18
Sink current
FLTb, PGb
0
2
mA
Source current
IMON
0
1
mA
Resistance
PROG
4.99
500
kΩ
TIMER
1
External capacitance
TJ
SENSE, SET (1), VCC (2)
MIN
GATE (3)
Operating junction temperature
–40
V
nF
1
µF
125
°C
Do not apply voltage directly to these pins.
See the Gate Clamp Diode section for additional precaution to be taken for operating voltages >14 V.
External capacitance tied to GATE must be in series with a resistor no less than 1 kΩ.
7.4 Thermal Information
TPS2475x
THERMAL METRIC (1)
RUV (VQFN)
UNIT
36 PINS
RθJA
Junction-to-ambient thermal resistance
33.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
28.2
°C/W
RθJB
Junction-to-board thermal resistance
5.8
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVSC87C – OCTOBER 2013 – REVISED DECEMBER 2018
Thermal Information (continued)
TPS2475x
THERMAL METRIC (1)
RUV (VQFN)
UNIT
36 PINS
ψJB
Junction-to-board characterization parameter
5.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.1
°C/W
7.5 Electrical Characteristics
–40°C ≤ TJ ≤ +125°C, VCC = 12 V, VEN = 3 V, RSET = 191 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND. All voltages
referenced to GND, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
UVLO threshold, rising
2.20
2.32
2.45
V
UVLO threshold, falling
2.10
2.22
2.35
V
1.4
mA
VCC
UVLO hysteresis (1)
0.1
Enabled ― IOUT + IVCC + ISENSE
Supply current
0.5
Disabled (1) ― EN = 0 V, IOUT + IVCC + ISENSE
1
V
0.45
mA
OUT
RON
On-resistance
1 A ≤ IOUT ≤ 10 A at TJ = 25°C
3
3.5
mΩ
1 A ≤ IOUT ≤ 10 A at TJ = 125°C
5
6
mΩ
16
30
µA
0.8
1
V
VEN = 0 V, VOUT = 0 V, VDRAIN = 18 V at 25°C
0
1
µA
VEN = 0 V, VOUT = 0 V, VDRAIN = 18 V at 125°C
2
5
µA
2710
3250
pF
635
762
pF
48
60
pF
17.5
21.5
nC
Input bias current
VOUT = 12 V
Diode forward voltage
VEN = 0 V, IOUT = –100 mA, VOUT > VSENSE
Leakage current - DRAIN to OUT
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
Qg
Gate charge total (4.5 V)
Qg(th)
Gate charge at Vth
10
VGS = 0 V, VDRAIN-OUT = 15 V, f = 1 MHz
VDRAIN-OUT = 15 V, IOUT = 20 A
4.1
nC
EN
Threshold voltage, falling
1.2
Hysteresis (1)
1.3
1.4
50
V
mV
Input leakage current
0 V ≤ VEN ≤ 30 V
–1
0
1
µA
Turnoff time
EN ↓ to VGATE < 1 V
3
8
25
µs
Deglitch time
EN ↑
8
14
21
µs
Disable delay
EN ↓ to GATE ↓, CGATE = 0, tpff50–90, See Figure 28
0.1
0.4
1.8
µs
Turnon delay
COUT = 2.2 uF, VEN ↑ to VOUT ↑, VEN: 0 V to 3 V, VOUT : 90%
VCC
800
µs
OV
Threshold voltage, rising
1.25
Hysteresis (1)
1.35
1.45
60
V
mV
Input leakage current
0 V ≤ VOV ≤ 30 V
–1
0
1
µA
Deglitch time
OV rising
0.5
1.2
1.5
µs
Output low voltage
Sinking 2 mA
Input leakage current
VFLTb = 0 V, 30 V
Threshold
V(SENSE – OUT) rising, PGb going high
Hysteresis (1)
Measured V(SENSE – OUT) falling, PGb going low
Output low voltage
Sinking 2 mA
Input leakage current
VPGb = 0 V, 30 V
FLTb
0.11
0.25
V
–1
0
1
µA
140
220
340
mV
PGb
(1)
70
–1
mV
0.11
0.25
V
0
1
µA
These parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
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Electrical Characteristics (continued)
–40°C ≤ TJ ≤ +125°C, VCC = 12 V, VEN = 3 V, RSET = 191 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND. All voltages
referenced to GND, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
NOM
MAX
2
3.4
6
Sourcing 10 µA
0.65
0.675
0.7
V
VPROG = 1.5 V
–0.2
0
0.2
µA
VTIMER = 0 V
8
10
12
µA
VTIMER = 2 V
8
10
12
µA
VEN = 0 V, VTIMER = 2 V
2
4.5
7
mA
Upper threshold voltage
1.3
1.35
1.4
V
Lower threshold voltage
0.33
0.35
0.37
V
5
5.8
7
V
Delay (deglitch) time
Rising or falling edge
Bias voltage
Input leakage current
Sourcing current
UNIT
ms
PROG
TIMER
Sinking current
Timer activation voltage
Raise GATE until ITIMER sinking, measure V(GATE – VCC), VVCC
= 12 V
Retry duty cycle
During over current and short circuit conditions (TPS24751
only)
4%
IMON
Circuit breaker threshold
650
675
696
mV
–1
0
1
mV
TJ from –40°C to +125°C
–1.5
0
1.5
mV
Input referred offset of servo amplifier
Measure SET to SENSE
–1.5
0
1.5
mV
Output voltage
VOUT = 12 V
23.5
25.7
28
V
Clamp voltage
Inject 10 µA into GATE, measure V(GATE – VCC)
12
13.9
15.5
V
Sourcing current
VGATE = 12 V
20
30
40
µA
Fast turnoff, VGATE = 14 V
0.4
1
1.4
A
6
11
20
mA
In inrush current limit, VGATE = 4 V to 23 V
20
30
40
µA
Thermal shutdown or VEN = 0 V
14
20
26
kΩ
8
13
18
µs
100
375
µs
Input referred offset of servo amplifier
At TJ = 25°C
SET
GATE
Sinking current
Sustained, VGATE = 4 V to 23 V
Pulldown resistance
Fast turnoff duration
Turnon delay
VVCC rising to GATE sourcing, tprr50-50, See Figure 29
SENSE
Input bias current
VSENSE = 12 V, sinking current
Current limit threshold
VOUT = 12 V
22.5
VDRAIN–OUT = 8 V, RPROG = 100 kΩ
Power limit threshold
Fast-turnoff delay
40
µA
25
27.5
mV
4
VDRAIN–OUT = 8 V, RPROG = 50 kΩ
6.6
8
9.6
VDRAIN–OUT = 5.37 V, RPROG = 50 kΩ
10
12
14
VDRAIN–OUT = 10.3 V, RPROG = 25 kΩ
10
12.5
15
52
60
68
Fast-trip threshold
(1)
30
V(VCC – SENSE) = 80 mV, CGATE = 0 pF, tprf50–50, See
Figure 30
mV
mV
200
ns
140
°C
10
°C
OTSD
Threshold, rising
Hysteresis
(2)
8
Temperature referenced to PAD1 of the device. See (2)
(1)
130
The temperature difference between PAD1 and PAD2 must be minimized. See the SOA curve Figure 27 and Power-Limited Start-Up
section for temperature limited design.
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7.6 Typical Characteristics
1200
5
4
T = 25°C
Supply Current (µA)
Supply Current (µA)
T = 125°C
1000
T = 125°C
800
T = –40°C
T = 25°C
3
2
T = –40°C
600
1
400
0
4
2
6
8
10
12
14
Input Voltage, VVCC (V)
16
18
0
20
EN = High
0
4
2
6
8
10
12
14
Input Voltage, VVCC (V)
16
18
20
EN = 0 V
Figure 1. Supply Current vs Input Voltage at Normal
Operation
Figure 2. Supply Current vs Input Voltage at Shutdown
32
26.5
28
Voltage ,V(VCC – SENSE) (mV)
VVCC = 2.5 V
25.5
25
24.5
VVCC = 18 V
24
T = 125°C
T = 25°C
20
16
T = –40°C
12
8
23.5
–50
–20
10
40
70
Temperature (°C)
100
4
130
Figure 3. Voltage Across RSENSE in Inrush Current Limiting
vs Temperature
0
2
4
6
8
10
Voltage, V(SENSE – OUT) (V)
12
0.25
1.8
Gate Current at Current Limiting
VVCC Voltage = 12 V
32
1.6
16
1.2
Gate Current (A)
24
1.4
T = 25°C
8
0
T = 125°C
–8
14
Figure 4. Voltage Across RSENSE in Inrush Power Limiting vs
VDS of Internal FET
40
MOSFET Gate Current (µA)
24
VVCC = 12 V
0.2
T = –40°C
T = 25°C
0.15
0.1
0.05
1
0.8
0
V(VCC – SENSE)
T = 125°C
0.6
–0.05
0.4
–0.1
0.2
–0.15
–16
T = –40°C
–24
0
–32
–0.2
–10
–40
0
5
10
15 20 25 30 35 40
Voltage, V(VCC – SENSE) (mV)
45
50
Voltage, V(VCC – SENSE) (V)
Voltage, V(VCC – SENSE) (V)
VCC Voltage = 12 V
VVCC = 12 V
26
–0.2
0
10
20
30
40
–0.25
Time (µs)
55
VVCC = VGATE = 12 V
Figure 6. Gate Current During Fast Trip
Figure 5. Internal FET Gate Current vs Voltage Across
RSENSE During Inrush Power Limiting
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0.25
0.2
T = –40°C
Gate Current (A)
0.6
0.15
T = 25°C
0.5
0.1
0.4
0.05
0.3
0
V(VCC – SENSE)
T = 125°C
0.2
–0.05
0.1
–0.1
0
–0.15
–0.1
–0.2
VVCC = 3.3 V
–0.2
–10
0
10
20
40
30
–0.25
Gate Voltage Referenced to GND, VGATE (V)
0.9
0.7
Voltage, V(VCC – SENSE) (V)
Typical Characteristics (continued)
Time (µs)
32
T = 25°C
28
T = 125°C
24
20
T = –40°C
16
12
8
4
0
8
12
Input Voltage, VVCC (V)
VVCC = VGATE = 3.3 V
16
20
Figure 7. Gate Current During Fast Trip
Figure 8. Gate Voltage With Zero Gate Current vs Input
Voltage
2
T = 125°C
T = 25°C
6
T = –40°C
5
4
3
1.6
1.2
CT = 4.7 nF
0.8
CT = 1 nF
0.4
0
4
8
12
Input Voltage, VVCC (V)
16
0
–50
20
–20
10
40
70
Temperature (°C)
100
130
Figure 10. Fault-Timer vs Temperature with Various TIMER
Capacitors
Figure 9. TIMER Activation Voltage Threshold vs Input
Voltage at Various Temperatures
1.6
2.36
VVCC = 12 V
UVLO Threshold Voltage (V)
1.4
EN Threshold Voltage (V)
VVCC = 12 V
CT = 10 nF
Fault-Timer Period (ms)
TIMER Activation Voltage Threshold (V)
7
1.2
EN Upper Threshold
1
0.8
0.6
0.4
VCC = 12 V
UVLO Upper Threshold
2.32
2.28
UVLO Lower Threshold
2.24
0.2
0
–50
0
50
Temperature (°C)
100
150
Figure 11. EN Threshold Voltage vs Temperature
10
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–50
–20
10
40
70
Temperature (°C)
100
130
Figure 12. UVLO Threshold Voltage vs Temperature
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Typical Characteristics (continued)
64
PGb Rising
Fast-Trip Threshold Voltage (mV)
V(SENSE – OUT) Threshold Voltage (mV)
240
220
200
180
PGb Falling
160
140
–50
10
–20
40
70
Temperature (°C)
100
140
120
VVCC = 18 V
VVCC = 2.5 V
100
80
VVCC = 12 V
60
–50
10
–20
40
70
Temperature (°C)
100
130
Figure 15. PGb Open-Drain Output Voltage in Low State
61.5
61
VVCC = 18 V
60.5
–20
10
40
70
Temperature (°C)
100
130
160
140
120
VVCC = 2.5 V
VVCC = 18 V
100
80
VVCC = 12 V
60
–50
–20
10
40
70
Temperature (°C)
100
130
1.344
Timer Upper Threshold Voltage (V)
VEN = 0 V
T = 125°C
0.6
Supply Current (µA)
62
Figure 16. FLTb Open-Drain Output Voltage in Low State
0.7
T = 25°C
0.5
0.4
T = –40°C
0.3
0.2
VVCC = 2.5 V
62.5
Figure 14. Fast-Trip Threshold Voltage vs Temperature
Low-State Open-Drain Output Voltage (mV)
Low-State Open-Drain Output Voltage (mV)
Figure 13. Threshold Voltage of VDS vs Temperature, PGb
Rising and Falling
VVCC = 12 V
63
60
–50
130
160
63.5
0
4
8
12
Input Voltage, VVCC (V)
16
20
Figure 17. Supply Current vs Input Voltage at Various
Temperatures when EN Pulled Low
1.342
VVCC = 12 V
VVCC = 18 V
1.34
1.338
VVCC = 2.5 V
1.336
1.334
–50
–20
10
40
70
Temperature (°C)
100
130
Figure 18. Timer Upper Threshold Voltage vs Temperature
at Various Input Voltages
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Typical Characteristics (continued)
10.2
Timer Sourcing Current (µA)
Timer Lower Threshold Voltage (V)
0.365
VVCC = 18 V
0.362
VVCC = 12 V
0.36
10
–20
40
70
Temperature (°C)
100
9.9
9.8
9.7
VVCC = 2.5 V
10
–20
40
70
Temperature (°C)
100
130
Figure 20. Timer Sourcing Current vs Temperature at
Various Input Voltages
1.6
10.4
10.3
1.4
VVCC = 18 V
OV Threshold Voltage (V)
Timer Sinking Current (µA)
VVCC = 12 V
9.5
–50
130
Figure 19. Timer Lower Threshold Voltage vs Temperature
at Various Input Voltages
VVCC = 12 V
10.2
10.1
10
VVCC = 2.5 V
9.9
1.2
OV Upper Threshold
1
0.8
0.6
0.4
0.2
9.8
9.7
–50
10
VVCC = 18 V
9.6
VVCC = 2.5 V
0.357
–50
10.1
10
–20
40
70
Temperature (°C)
100
0
–50
130
0
50
Temperature (°C)
100
150
Figure 22. OV Threshold Voltage vs Temperature
Figure 21. Timer Sinking Current vs Temperature at Various
Input Voltages
0.9
5
0.85
Diode Drop 100 mA (V)
Rds(ON) (mW)
4.5
4
3.5
3
2.5
2
-50
0.75
0.7
0.65
0.6
0.55
0
50
o
Temperature ( C)
100
Figure 23. RDS(ON) vs Temperature
12
0.8
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150
0.5
-50
0
50
o
Temperature ( C)
100
150
Figure 24. Diode Drop vs Temperature
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Typical Characteristics (continued)
3
ID = 20A
VDS = 15V
2.5
8
2
Leakage (mA)
VGS - Gate-to-Source Voltage (V)
10
6
4
1.5
1
0.5
2
0
0
0
5
10
15
20
25
30
Qg - Gate Charge - nC (nC)
35
-0.5
-50
40
Figure 25. Gate Charge – Internal MOSFET
0
50
o
Temperature ( C)
100
150
Figure 26. Leakage Current vs Temperature
IDS – Drain-to-Source Current – A
1000
Area Limited
by RDS(on)
100
1 ms
10
10 ms
100 ms
1
0.1
0.1
Single Pulse
RqJA = 62.3ºC/W
TA = 25ºC
1
10
100
VDS – Drain-to-Source Voltage – V
Figure 27. TPS2475x Maximum Safe Operating Area (SOA)
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8 Parameter Measurement Information
VGATE
90%
VEN
50%
0
Time
t(pff50-90)
T0492-01
Figure 28. tpff50–90 Timing Definition
IGATE
50%
VVCC
50%
0
Time
t(prr50-50)
T0494-01
Figure 29. tprr50–50 Timing Definition
VGATE
50%
VVCC – VSENSE
50%
0
Time
t(prf50-50)
T0495-01
Figure 30. tprf50–50 Timing Definition
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9 Detailed Descriptions
9.1 Overview
The TPS2475x provides all the features needed for a positive hot-swap protector. These features include:
• Undervoltage lockout
• Adjustable (system-level) enable
• Turnon inrush limiting
• Integrated N-channel MOSFET
• MOSFET protection by power limiting
• Electronic circuit breaker operation with adjustable overload timeout
• Charge-complete indicator for downstream converter coordination
• A choice of latch or automatic restart mode
• Load overvoltage protection
• Precise current monitor output
The typical application diagram, shown on the front page of this data sheet, and oscilloscope plots, shown in
Figure 31 through Figure 33 and Figure 35 through Figure 39, demonstrate many of the functions of the device.
9.2 Functional Block Diagram
VIN
RSENSE
RSET
SENSE
SET
DRAIN
3
26
5
14
OUT
15
16
17
18
27
6
7
8
9
10
11
12
13
19
20
21
22
23
24
60mV
+
VCC
Charge
Pump
DC
+
30uA
29
+
Fast
Comparator
-
IMON
25
GATE
31
PGb
30
FLTb
Inrush
Latch
Gate
Comparator
S
Q
R
Q
+
2
VCC
1- shot
Servo
Amplifier
5.8 V
0 ~ 60 uA
RIMON
+
A
B
+
PROG
-
34
PG
Comparator
OUT
RPROG
UVLO
VCC
EN
33
220 mV
150 mV
+
1.35 V
1.30 V
1.35 V
1.28 V
OV
20 k
DC
+
2.32 V
2.22 V
3.4 mS
+
14 uS
+
10.0 uA
1
Fault Logic
1.2 uS
VCC
+
+
TSD
10.0 uA
1.50 V
1.35
0.35
POR
36 GND
Turn off Main Circuit
28 GND
4
GND
35
TIMER
CT
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9.3 Feature Description
9.3.1 DRAIN
The drain of the internal pass MOSFET. Connect to a terminal of current sense resistor in the power path.
9.3.2 EN
Applying a voltage of 1.3 V or more to this pin enables the gate driver. The addition of an external resistor divider
allows the EN pin to serve as an undervoltage monitor. Cycling EN low and then back high resets the TPS24750
that has latched off due to a fault condition. This pin must not be left floating.
9.3.3 FLTb
This active-low open-drain output pulls low when the TPS2475x has remained in current limit long enough for the
fault timer to expire. The TPS24750 operates in latch mode while the TPS24751 operates in retry mode. In latch
mode, a fault timeout disables the internal MOSFET and holds FLTb low. The fault is reset when EN is pulled
low or VCC falls under UVLO. In retry mode, a fault timeout first disables the internal MOSFET, next waits
sixteen cycles of TIMER charging and discharging, and finally attempts a restart. This process repeats as long as
the fault persists. In retry mode, the FLTb pin is pulled low whenever the internal MOSFET is disabled by the
fault timer. In a sustained fault, the FLTb waveform becomes a train of pulses. The FLTb pin does not assert if
the internal MOSFET is disabled by EN, OV, overtemperature shutdown, or UVLO. This pin can be left floating
when not used.
9.3.4 GATE
This pin provides gate drive to the internal MOSFET. A charge pump sources 30 µA to enhance the internal
MOSFET. A 13.9 V clamp between GATE and VCC limits the gate-to-source voltage since VVCC is close to VOUT
in normal operation. During start up, a transconductance amplifier regulates the gate voltage of the internal FET
to provide inrush current limiting. The TIMER pin charges timer capacitor CT during the inrush. Inrush current
limiting continues until the V(GATE – VCC) exceeds the Timer Activation Voltage 5.8 V for VVCC = 12 V. Then the
TPS2475x enters into circuit breaker mode. In the circuit breaker mode, the current flowing in RSENSE is
compared with the current limit threshold derived from the MOSFET power limit scheme (see the PROG
definition). If the current flowing in RSENSE exceeds the current limit threshold, then the internal pass MOSFET
will be turned off. The GATE pin is disabled by the following three mechanisms:
1. GATE is pulled down by an 11-mA current source when
– The fault timer expires during an overload current fault (VIMON > 675 mV)
– VEN is below its falling threshold
– VVCC drops below the UVLO threshold
– VOV is above its rising threshold
2. GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V(VCC –
SENSE) is greater than 60 mV, that is, the fast-trip shutdown threshold. After fast-trip shutdown is complete, an
11-mA sustaining current ensures that the internal FET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
GATE remains low in latch mode (TPS24750) and attempts a restart periodically in retry mode (TPS24751).
Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can
be left floating to obtain a predetermined slew rate on the output.
If used, any capacitor connecting GATE and GND must not exceed 1 μF and it must be connected in series with
a resistor of no less than 1 kΩ. No external resistor must be directly connected from GATE to GND or from
GATE to OUT.
9.3.5 GND
This pin is connected to system ground.
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Feature Description (continued)
9.3.6 IMON
A resistor connected from this pin to GND scales the current-limit and power-limit settings, as illustrated in the
Functional Block Diagram. The voltage present at this pin is proportional to the current flowing through sense
resistor RSENSE. This voltage can be used as a means of monitoring current flow through the system. The value
of RIMON can be calculated from Equation 3. This pin must not have a bypass capacitor or any other load except
for RIMON.
9.3.7 OUT
This pin is connected to the source of the internal MOSFET inside the chip. It allows the device to measure the
drain-to-source voltage across the internal MOSFET. The power good indicator (PGb) relies upon this
information, as does the power limiting engine. The OUT pin must be bypassed to GND with a low-impedance
ceramic capacitor in the range of 10 nF to 1 μF. Connect all the OUT pins to output capacitors and load. In the
presence of cable inductance, the OUT pin must be protected from negative voltage transients by using a
clamping/Schottky diode.
9.3.8 OV
This pin is used to program the device overvoltage level. A voltage of more than 1.35 V on this pin turns off the
internal FET. A resistor divider connected from VCC to this pin provides overvoltage protection for the
downstream load. This pin must be tied to GND when not used.
9.3.9 PGb
This active low, open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits.
PGb pulls low after the drain-to-source voltage of the internal FET has fallen below 150 mV and a 3.4 ms
deglitch delay has elapsed. It goes open drain when VDS exceeds 220 mV. PGb assumes high impedance status
after a 3.4 ms deglitch delay once VDS of internal FET rises up, resulting from GATE being pulled to GND at the
following conditions:
• An overload current fault occurs (VIMON > 675 mV) and the fault timer times out.
• A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, that is, the fast-trip shutdown
threshold has been exceeded.
• VEN is below its falling threshold.
• VVCC drops below the UVLO threshold.
• VOV is above its rising threshold.
• Die temperature exceeds the OTSD threshold.
This pin can be left floating when not used.
9.3.10 PROG
A resistor from this pin to GND sets the maximum power permitted in the internal MOSFET during inrush. Do not
apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of 4.99 kΩ. To set the
maximum power, use Equation 1.
84375 ´ RSET
PLIM =
RPROG ´ RSENSE ´ RIMON
(1)
where PLIM is the allowed power limit of the internal MOSFET. RSENSE is the load current monitoring resistor
connected between the VCC pin and the SENSE pin. RPROG is the resistor connected from the PROG pin to
GND. Both RPROG and RSENSE are in ohms and PLIM is in watts. PLIM is determined by the maximum allowed
thermal stress of internal MOSFET, given by Equation 2.
TJ(MAX) - TC(MAX)
PLIM <
RθJC(MAX)
(2)
where TJ(MAX) is the maximum desired transient junction temperature and TC(MAX) is the maximum case
temperature prior to a start or restart. RӨJC(MAX) is the junction-to-case thermal impedance of the internal pass
FET in units of °C/W. Both TJ(MAX) and TC(MAX) are in °C.
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Feature Description (continued)
9.3.11 SENSE
This pin connects to the negative terminal of RSENSE. It provides a means of sensing the voltage across this
resistor, as well as a way to monitor the drain-to-source voltage across the internal FET. The current limit ILIM is
set by Equation 3.
0.675 V ´ RSET
ILIM =
RIMON ´ RSENSE
(3)
A fast-trip shutdown occurs when V(VCC – VSENSE) exceeds 60 mV.
SET: A resistor RSET is connected from this pin to the positive terminal of RSENSE. This resistor scales the current
limit and power limit settings. It coordinates with RIMON and RSENSE to determine the current limit value. The value
of RSET can be calculated from Equation 3 (see the SENSE definition).
9.3.12 TIMER
A capacitor CT connected from the TIMER pin to GND determines the overload fault timing. TIMER sources 10
µA when an overload is present, and discharges CT at 10 µA otherwise. Internal FET is turned off when VTIMER
reaches 1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period
before the internal FET is re-enabled. A minimum timing capacitance of 1 nF is recommended to ensure proper
operation of the fault timer. The value of CT can be calculated from the desired fault time tFLT, using Equation 4.
10 μA
CT =
´ tFLT
1.35 V
(4)
Either latch mode (TPS24750) or retry mode (TPS24751) occurs if the load current exceeds the current limit
threshold or the fast trip shutdown threshold. While in latch mode, the TIMER pin continues to periodically charge
and discharge the attached capacitor. In retry mode, the internal MOSFET is disabled for sixteen cycles of
TIMER charging and discharging. The TIMER pin is pulled to GND by a 2 mA current source at the end of the
16th cycle of charging and discharging. The internal MOSFET is then re-enabled. The TIMER pin capacitor, CT,
can also be discharged to GND during latch mode or retry mode in the following way:
• A 2-mA current sinks TIMER whenever any of the following occurs:
– VEN is below its falling threshold.
– VVCC drops below the UVLO threshold.
– VOV is above its rising threshold.
TIMER is not affected when the die temperature exceeds the OTSD threshold.
9.3.13 VCC
This pin performs three functions. First, it provides biasing power to the integrated circuit. Second, it serves as an
input to the power-on reset (POR) and undervoltage lockout (UVLO) functions. Bypass capacitor C1, shown in
the typical application diagram on the front page, must be connected to the positive terminal of VVCC. A
capacitance of at least 10 nF is recommended.
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9.4 Device Functional Modes
9.4.1 Board Plug-In
Figure 31 and Figure 32 illustrate the inrush current that flows when a hot swap board under the control of the
TPS2475x is plugged into a system bus. Only the bypass capacitor charge current and small bias currents are
evident when a board is first plugged in. The TPS2475x is held inactive for a short period while internal voltages
stabilize. In this short period, GATE, PROG, and TIMER are held low and PGb, and FLTb, are held open-drain.
When the voltage on the internal VCC rail exceeds approximately 1.5 V, the power-on reset (POR) circuit
initializes the TPS2475x and a start-up cycle is ready to take place.
5 A/div
200 mV/div
500 mV/div
10 V/div
GATE, PROG, TIMER, PGb, and FLTb are released after the internal voltages have stabilized and the external
EN (enable) thresholds have been exceeded. The part begins sourcing current from the GATE pin to turnon
internal FET. The TPS2475x monitors both the drain-to-source voltage across internal MOSFET and the drain
current passing through it. Based on these measurements, the TPS2475x limits the drain current by controlling
the gate voltage so that the power dissipation of the internal FET does not exceed the power limit programmed
by the user. The current increases as the voltage across the FET decreases until finally the current reaches the
current limit ILIM.
Figure 31. Inrush Mode at Hot-Swap Circuit Insertion
9.4.2 Inrush Operation
After the TPS2475x initialization is complete (as described in the Board Plug-in section) and EN is active, GATE
is enabled (VGATE starts increasing), when VGATE reaches the internal FET gate threshold, a current flows into the
downstream bulk storage capacitors. When this current exceeds the limit set by the power-limit engine, the gate
of the internal FET is regulated by a feedback loop to make the internal FET current rise in a controlled manner.
This not only limits the capacitor-charging inrush current but it also limits the power dissipation of the internal
FET to safe levels. A more complete explanation of the power-limiting scheme is given in the Action of the
Constant-Power Engine section. When the GATE is enabled, the TIMER pin begins to charge the timing
capacitor CT with a current of approximately 10 µA. The TIMER pin continues to charge CT until V(GATE-VCC)
reaches the timer activation voltage (5.8 V for VVCC = 12V). The TIMER then begins to discharge CT with a
current of approximately 10 µA. This indicates that the inrush mode is finished. If the TIMER exceeds its upper
threshold of 1.35 V before V(GATE – VCC) reaches the timer activation voltage, the GATE pin is pulled to GND and
the hot-swap circuit enters either latch mode (TPS24750) or auto-retry mode (TPS24751).
The power limit feature is disabled once the inrush operation is finished and the hotswap circuit becomes a
circuit breaker. The TPS2475x turns off the internal FET after a fault timer period once the load exceeds the
current limit threshold.
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Device Functional Modes (continued)
9.4.3 Action of the Constant-Power Engine
4 W/div
2 A/div
5 V/div
Figure 32 illustrates the operation of the constant-power engine during start-up. The circuit used to generate the
waveforms of Figure 32 was programmed to a power limit of 21 W by means of the resistor connected between
PROG and GND. At the moment current begins to flow through the internal FET, a voltage of 12 V appears
across it (input voltage VVCC = 12 V), and the constant-power engine therefore allows a current of 1.75 A (equal
to 21 W divided by 12 V) to flow. This current increases in inverse ratio as the drain-to-source voltage
diminishes, so as to maintain a constant dissipation of 21 W. The constant-power engine adjusts the current by
altering the reference signal fed to the current limit amplifier. The lower part of Figure 32 shows the measured
power dissipated in the internal FET, labeled FET PWR, remaining substantially constant during this period of
operation, which ends when the current through the FET reaches the current limit ILIM. This behavior can be
considered a form of foldback limiting, but unlike the standard linear form of foldback limiting, it allows the power
device to operate near its maximum capability, thus reducing the start-up time.
Figure 32. Computation of Power Stress During Startup
9.4.4 Circuit Breaker and Fast Trip
The TPS2475x monitors load current by sensing the voltage across RSENSE. The TPS2475x incorporates two
distinct thresholds: a current-limit threshold and a fast-trip threshold.
The functions of circuit breaker and fast-trip turnoff are shown in Figure 33 through Figure 36.
Figure 33 shows the behavior of the TPS2475x when a fault in the output load causes the current passing
through RSENSE to increase to a value above the current limit but less than the fast-trip threshold. When the
current exceeds the current-limit threshold, a current of approximately 10 μA begins to charge timing capacitor
CT. If the voltage on CT reaches 1.35 V, then the internal FET is turned off. The TPS24750 version latches off,
while as the TPS24751 version commences a restart cycle. In either event, fault pin FLTb pulls low to signal a
fault condition. Overload between the current limit and the fast-trip threshold is permitted for this period. This
shutdown scheme is sometimes called an electronic circuit breaker.
The fast-trip threshold protects the system against a severe overload or a dead short circuit. When the voltage
across the sense resistor RSENSE exceeds the 60-mV fast-trip threshold, the GATE pin immediately pulls the
internal FET gate to ground with approximately 1 A of current. The fast-trip circuit holds the internal FET off for
only a few microseconds, after which the TPS2475x turns back on slowly, allowing the current-limit feedback
loop to take over the gate control of the internal FET. Then the hot-swap circuit goes into latch mode (TPS24750)
or auto-retry mode (TPS24751). Figure 35 and Figure 36 illustrate the behavior of the system when the current
exceeds the fast-trip threshold.
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500 mV/div
5 A/div
5 V/div
10 V/div
Device Functional Modes (continued)
Figure 33. Circuit-Breaker Mode During Overload Condition
ILIMIT
RSENSE
RSET
VCC
SET
SENSE
DRAIN
GATE
OUT
Internal FET
+
A2
675mV
IMON
PROG
RIMON
RPROG
30PA
+
Fast Trip
Comparator
Server Amp A1
60PA
+
60mV
VCP
Current
Limit Amp
+
-
Figure 34. Partial Diagram of the TPS2475x with Selected External Components
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5 V/div 5 V/div 10 A/div
5 A/div 5 V/div 500 mV/div
500 mV/div
10 V/div
Device Functional Modes (continued)
Figure 35. Current Limit During Output-Load Short-Circuit
Condition (Overview)
Figure 36. Current Limit During Output-Load Short-Circuit
Condition (Onset)
9.4.5 Automatic Restart
5 A/div
Figure 37. Auto-Restart Cycle Timing
22
5 V/div
5 A/div
5 V/div
5 V/div
500 mV/div
10 V/div
500 mV/div 10 V/div
In Auto-retry versions (TPS24751), device automatically initiates a restart after a fault has caused it to turnoff the
internal FET. Internal control circuits use CT to count 16 cycles before re-enabling the FET as shown in
Figure 37. This sequence repeats if the fault persists. The timer has a 1:1 charge-to-discharge current ratio. For
the very first cycle, the TIMER pin starts from 0 V and rises to the upper threshold of 1.35 V and subsequently
falls to 0.35 V before restarting. For the following 16 cycles, 0.35 V is used as the lower threshold. This small
duty cycle often reduces the average short-circuit power dissipation to levels associated with normal operation
and eliminates special thermal considerations for surviving a prolonged output short.
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Figure 38. Latch After Overload Fault
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Device Functional Modes (continued)
9.4.6 Start-Up with Short on Output
The TPS2475x has ability of detecting the short at the output during start-up and ensure shutdown of the hotswap circuit/system with fault indication. During start-up, after the initialization process is complete and the GATE
is enabled, the device limits the power as explained in the Action of the Constant-Power Engine section and the
TIMER pin begins to charge the timing capacitor CT with approximately 10 µA constant current source. If the
voltage on CT reaches its upper limit threshold of 1.35V, during start-up cycle itself, then the internal FET is
turned off and fault pin FLTb is pulled low to signal the fault condition. After this, the hot-swap circuit enters either
in latch mode (TPS24750) or auto-retry mode (TPS24751). Figure 39 shows the behavior of the TPS2475x for
start-up with short on the output.
5 A/div
5 V/div
500 mV/div
10 V/div
This feature help to ensure early detection of fault and quick isolation of the subsystem to ensure stability of the
other units connected on the DC bus.
Figure 39. Start-Up with Short on Output
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Device Functional Modes (continued)
9.4.7 PGb, FLTb, and Timer Operations
The open-drain PGb output provides a deglitched end-of-inrush indication based on the voltage across internal
FET. PGb is useful for preventing a downstream dc/dc converter from starting while its input capacitor COUT is
still charging. PGb goes active-low about 3.4 ms after COUT is charged. This delay allows the internal FET to fully
turnon and any transients in the power circuits to end before the converter starts up. This type of sequencing
prevents the downstream converter from demanding full current before the power-limiting engine allows the
internal FET to conduct the full current set by the current limit ILIM. Failure to observe this precaution may prevent
the system from starting. The pullup resistor shown on the PGb pin in the typical system block diagram
application diagram Figure 41 is illustrative only; the actual connection to the converter depends on the
application. The PGb pin may indicate that inrush has ended before the MOSFET is fully enhanced, but the
downstream capacitor will have been charged to substantially its full operating voltage. After the hot-swap circuit
successfully starts up, the PGb pin can return to a high-impedance status whenever the drain-to-source voltage
of internal FET exceeds its upper threshold of 340 mV, which presents the downstream converters a warning
flag. This flag may occur as a result of overload fault, output short fault, input overvoltage, higher die
temperature, or the GATE shutdown by UVLO, EN.
FLTb is an indicator that the allowed fault-timer period during which the load current can exceed the programmed
current limit (but not the fast-trip threshold) expires. The fault timer starts when a current of approximately 10 μA
begins to flow into the external capacitor CT, and ends when the voltage of CT reaches TIMER upper threshold,
that is, 1.35 V. FLTb pulls low at the end of the fault timer. Otherwise, FLTb assumes a high-impedance state.
The fault-timer state requires an external capacitor CT connected between the TIMER pin and GND pin. The
duration of the fault timer is the charging time of CT from 0 V to its upper threshold of 1.35 V. The fault timer
begins to count under any of the following three conditions:
1. In the inrush mode, TIMER begins to source current to the timer capacitor, CT, when device is enabled.
TIMER begins to sink current from the timer capacitor, CT when V(GATE – VCC) exceeds the timer activation
voltage (see the Inrush Operation section). If V(GATE – VCC) does not reach the timer activation voltage before
TIMER reaches 1.35 V, then the TPS2475x disables the internal FET. After the MOSFET turns off, the timer
goes into either latch mode (TPS24750) or retry mode (TPS24751).
2. In an overload fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of
1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground.
After the fault timer period, TIMER may go into latch mode (TPS24750) or retry mode (TPS24751).
3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the programmed current limits following a fast-trip shutdown of internal FET. When the timer
capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer
capacitor, CT, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch
mode (TPS24750) or retry mode (TPS24751).
If the fault current drops below the programmed current limit within the fault timer period, VTIMER decreases and
the internal pass MOSFET remains enabled.
The behaviors of TIMER are different in the latch mode and retry mode. If the timer capacitor reaches the upper
threshold of 1.35 V, then:
• In latch mode(TPS24750), the TIMER pin continues to charge and discharge the attached capacitor
periodically until device is disabled by UVLO, EN, or OV, as shown in Figure 38.
• In retry mode(TPS24751), TIMER charges and discharges CT between the lower threshold of 0.35 V and the
upper threshold of 1.35 V for sixteen cycles before the device attempts to re-start. The TIMER pin is pulled to
GND at the end of the 16th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the initial
half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload fault is
removed or the TPS2475x is disabled by UVLO, EN or OV.
24
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Device Functional Modes (continued)
9.4.7.1 Overtemperature Shutdown
The TPS2475x includes a built-in overtemperature shutdown circuit designed to disable the gate driver and
hence turnoff the internal FET if the die temperature exceeds approximately 140°C. An overtemperature
condition also causes the FLTb and PGb pins to go to high-impedance states. Normal operation resumes once
the die temperature has fallen approximately 10°C.
9.4.7.2 Start-Up of Hot-Swap Circuit by VCC or EN
The connection and disconnection between a load and the input power bus are controlled by turning on and
turning off the internal FET.
The TPS2475x has two ways to turnon the internal FET:
• Increasing VVCC above UVLO upper threshold while EN is already higher than its upper threshold sources
current to the gate of internal FET. After an inrush period, the TPS2475x fully turns on internal FET.
• Increasing EN above its upper threshold while VVCC is already higher than the UVLO upper threshold sources
current to the gate of internal FET. After an inrush period, the TPS2475x fully turns on internal FET.
The EN pin can be used to start up the TPS2475x at a selected input voltage VVCC.
To isolate the load from the input power bus, the internal FET can be disabled by any of the following conditions:
UVLO, EN, load current above the current-limit threshold, hard short at load, OV, or OTSD. Three separate
mechanisms disable the internal FET by pulling down the GATE as described below:
1. GATE is pulled down by an 11-mA current source when any of the following occurs.
– The fault timer expires during an overload current fault (VIMON > 675 mV).
– VEN is below its falling threshold.
– VVCC drops below the UVLO threshold.
– VOV is above its rising threshold.
2. GATE is pulled down by a 1-A current source for 13.5 μs when a hard output short circuit occurs and V(VCC –
SENSE) is greater than 60 mV, that is, the fast-trip shutdown threshold. After fast-trip shutdown is complete, an
11-mA sustaining current ensures that the internal FET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS2475x provide highly integrated load protection for 2.5 V to 18 V applications. The devices integrate a
hot swap controller and a power MOSFET in a single package for small form factor applications. These devices
protect source, load and internal MOSFET from potentially damaging events in applications such as Servers,
Plug-In Modules, RAID systems, Base stations and Fan Control.
The following design procedure can be used to select component values for the device.
Additionally, a spreadsheet design tool TPS2475x Design Calculator Tool (SLVC545) is available on web folder.
10.2 Typical Application
R3
VCC SET
SENSE DRAIN
OUT
FLT
EN
PG
OV
IMON
RPROG
REXT
CLOAD
TIMER
RIMON
GND
CT
PROG
CEXT
R2
GATE
R4
Input Voltage Bus
R1
RSET
Output to Voltage Bus or
DC/DC Converter
Rsense
Figure 40. Gate Capacitor (dV/dt) Control Inrush Mode
10.2.1 Design Requirements
For this design example, use the parameters shown in Table 1.
Table 1. Design Parameters
Parameter
26
Value
Input voltage V(VCC)
12 V
Undervoltage lockout set point, VUV
8.4 V
Overvoltage protection set point , VOV
14 V
Load after PG asserted , RLOAD
1.2 Ω
Current limit, ILIM
11 A
Load capacitance , COUT
470 μF
Maximum ambient temperatures , TA
60°C
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10.2.2 Detailed Design Procedure
10.2.2.1 Power-Limited Start-Up
This design example assumes a 12-V system voltage with an operating tolerance of ±2 V. The rated load current
is 10 A. If the current exceeds 11 A, then the device must shut down and then attempt to restart. Ambient
temperatures may range from 20°C to 60°C. The load has a minimum input capacitance of 470 μF. The load is
turned on only after the PG signal is asserted. Figure 41 shows a simplified system block diagram of the
proposed application.
This design procedure seeks to control the junction temperature of device under both static and transient
conditions by proper selection of current limit, fault timeout, and power limit. The design procedure assumes the
worst case as a unit running at full load and maximum ambient temperature experiences a short circuit event.
Adjust this procedure to fit the application and design criteria.
Rsense
PROTECTION
LOAD
5VDC
EN
PGb
OV
RPROG
R3
R5
IMON
PROG
GND
TIMER
RIMON
GATE
OUT
FLTb
Load Switch
DRAIN
RLOAD
1.2 :
SENSE
COUT
470 PF
SET
CT
Specifications (at output) :
Peak Current Limit = 11A
Nominal Current = 10A
VCC
C1
0.1 PF
R2
12V Main Bus
Supply
R4
R1
RSET
Figure 41. Simplified Block Diagram of the System Constructed in the Design Example
10.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON
The recommended range of the current-limit threshold voltage, V(VCC – SENSE), extends from 10 mV to 42 mV.
Values near the low threshold of 10 mV may be affected by system noise. Values near the upper threshold of
42 mV may be too close to the minimum fast-trip threshold voltage of 52 mV. Values near the middle of this
range help minimize both concerns.
To achieve high efficiency, the power dissipation in RSENSE must be kept to a minimum. A RSENSE of 2 mΩ
develops a voltage of 22 mV at the specified peak current limit of 11 A, while dissipating only 200 mW at the
rated 10-A current. This represents a 0.17% power loss.
For best performance, a current of approximately 0.5 mA (see the Recommended Operatings Conditions table)
must flow into the SET pin and out of the IMON pin when the TPS2475x is in current limit. The voltage across
RSET nominally equals the voltage across RSENSE, or 22 mV. Dividing 22 mV by 0.5 mA gives a recommended
value of RSET of 44 Ω. A 51.1-Ω, 1% resistor was chosen. Using Equation 3, the value of RIMON must equal 1568
Ω, or as near as practically possible. A 1.58-kΩ, 1% resistor was chosen. See Equation 5.
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ILIM =
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0.675 V ´ RSET
RIMON ´ RSENSE
therefore,
RIMON =
0.675 V ´ 51.1
= 1567.8
11 ´ 0.002
(5)
10.2.2.1.2 STEP 2. Choose Power-Limit Value, PLIM, and RPROG
The internal MOSFET dissipates large amounts of power during inrush. The power limit PLIM of the TPS2475x
must be set to prevent the internal FET die temperature from exceeding a short-term maximum temperature,
TJ(MAX)2. The short-term TJ(MAX)2 could be set ≤125°C to have sufficient margin to the internal maximum FET
junction temperature. Equation 6 is an expression for calculating PLIM.
TJ(MAX)2 - é IMAX2 ´ R DS(on) ´ RqCA + TA(MAX) ù
ë
û
PLIM £ 0.8 ´
RqJC
(
)
therefore,
PLIM £ 0.8 ´
125°C - é
ëê
((11 A ) ´ 5 mW ´ (33.7°C / W - 1.1°C / W )) + 60°Cùûú = 32.93 W
2
1.1°C / W
(6)
In the above equation, RθCA= RθJA – RθJC
Where, RθCA is the case-to-ambient thermal resistance (RθCA is a strong function of the user defined PCB layout
and heat sinking provided on Pad-2 of the device and can vary accordingly), RθJA is the junction-to-ambient
thermal resistance and RθJC is the junction-to-case thermal resistance of the device, (In Equation 6 , the values
are used from the TPS2475x Thermal Information table), rDS(on) is internal FET on-resistance at the maximum
operating temperature, and the factor of 0.8 represents the tolerance of the constant-power engine. For an
ambient temperature of 60°C, the calculated maximum PLIM is 33 W. Power limit selected must be lower than
value obtained in Equation 6, to have substantial safe margin considering the tolerance of components and
extended system temperatures. Power limit (PLIM) of 21 W is considered for this design. From Equation 1, a 64.9kΩ, 1% resistor is selected for RPROG (see Equation 7).
84375 ´ R SET
RPROG =
PLIM ´ R SENSE ´ R IMON
therefore,
RPROG =
84375 ´ 51.1
= 64.97 kW
21´ 0.002W ´ 1580W
(7)
Power Limit fold back (PLIM-FB) is the ratio of operating current (ILIM) and minimum power limited (regulated)
current (when VOUT = 0V). Degradation of programmed power limit (PLIM) accuracy and start up issues may occur
if PLIM-FB is too large. Equation 8 calculates VSNS-PL_MIN (minimum sense voltage during power limit) and PLIM-FB.
To ensure reliable operation, verify that PLIM-FB < 12 and VSNS-PL_MIN ≥ 3mV.
P ´ RSENSE 21W ´ 2 mW
=
= 3 mV ( ³ 3 mV)
VSNS -PL _ MIN = LIM
VCC(MAX)
14 V
PLIM-FB =
28
ILIM ´ VCC(MAX)
PLIM
=
11 A ´ 14 V
= 7.33 (< 12)
21 W
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If the above conditions are not met, please adjust and align RSENSE, PLIM set, and TA(MAX) appropriately to satisfy
the above conditions.
10.2.2.1.3 STEP 3. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT
The maximum output voltage rise time, tON, set by timer capacitor CT must suffice to fully charge the load
capacitance COUT without triggering the fault circuitry. Equation 9 defines tON for two possible inrush cases.
Assuming that only the load capacitance draws current during startup,
COUT ´ PLIM
2 ´ I2LIM
+
COUT ´ V 2 VCC(MAX)
2 ´ PLIM
if
PLIM < ILIM ´ VVCC(MAX)
t ON =
COUT ´ VVCC(MAX)
ILIM
if
PLIM > ILIM ´ VVCC(MAX)
therefore,
t ON =
470 μF ´ 21 W 470 μF ´ 14 ´ 14
+
= 2.234 ms
2 ´ (11´ 11)
2 ´ 21
(9)
The next step is to determine the minimum fault-timer period. In Equation 9, the output rise time is tON. This is the
amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer uses
the difference between the input voltage and the gate voltage to determine if the TPS2475x is still in inrush limit.
The fault timer continues to run until VGS rises 5.8 V (for VVCC = 12 V) above the input voltage. Some additional
time must be added to the charge time to account for this additional gate voltage rise. The minimum fault time
can be calculated using Equation 10.
+ QGBLK
Q
tFLT = t ON + GINT
IG
therefore,
tFLT = t ON +
22 nC + 17 nC
= t ON + 1.95 ms = 4.184 ms
20 μA
(10)
where QGINT is the Gate charge of the internal FET to reach the 5.8 V gate voltage (see Figure 25), QGBLK is the
Gate charge of blocking FET (for this design, it is considered that CSD17501Q5A SLPS303 blocking FET is
used, take this as '0' if blocking FET is not used) and IGATE is the minimum gate sourcing current of the
TPS2475x, or 20 μA. Overall, Equation 10 leads to a minimum fault time of 4.184 ms. Considering the tolerances
of COUT, CT, ILIM , ITIMER and PLIM, the fault timer must be set to a value ≥ 1.4 times of tFLT obtained, to avoid
turning off during start-up, but need to be lower than any maximum fault time limit determined by the device SOA
curve (see Figure 27).
For this example, we select 6.3 ms (1.5 x TFLT) to allow for variation of system parameters such as temperature,
load, component tolerance, and input voltage. As per SOA curve (TA = 25oC), for approximately 6.5 ms, the
power handled by the device is approximately 70 W at 12 V (value obtained from extrapolation). This need to be
scaled (derated) by a factor of (150 –TJDCMAX))/(150 – TA), where TJDCMAX is the maximum steady state junction
temperature (TJDMAX = TA(MAX) + ILIM2 × R(DS)ON × RθJA). The scaled power is approximately 34 W. So the power
limit of 21 W considered has safe margin of 38% over the derated SOA. This can be depicted through the
Figure 42. Also, from Figure 42, from the blue dotted line shown, it can be analyzed that the device at TA = 25oC,
can tolerate 12 V and 10 A for approximately time 1 ms and can take power of 21 W for duration of
approximately 70 to 75 ms.
The timing capacitor is calculated in Equation 11 as 46.67 nF. Selecting the next-highest standard value, 47 nF,
yields a 6.35 ms fault time.
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CT =
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10 μA ´ t FLT
1.35
therefore,
CT =
10 μA ´ 6.3 ms
= 46.67 nF
1.35
(11)
IDS – Drain-to-Source Current – A
1000
Area Limited
by RDS(on)
100
1 ms
10
10 ms
Margin
1 msms
100
1
Single Pulse
RqJA = 62.5ºC/W
TA = 25ºC
0.1
0.1
1
10
100
VDS – Drain-to-Source Voltage – V
Figure 42. Design Example SOA
10.2.2.1.4 STEP 4. Calculate the Retry-Mode Duty Ratio
In retry mode, the TPS24751 is on for one charging cycle and off for 16 charge-discharge cycles, as can be seen
in Figure 37. The first CT charging cycle is from 0 V to 1.35 V, which gives 6.35 ms. The first CT discharging
cycle is from 1.35 V to 0.35 V, which gives 4.7 ms. Therefore, the total time is 6.35 ms + 33 × 4.7 ms = 161.45
ms. As a result, the retry mode duty ratio is 6.35 ms/161.45 ms = 3.93%. So effective steady state power
dissipation in device during continuos short conditions is 4% of PLIM.
10.2.2.1.5 STEP 5. Select R1, R2, and R3 for UV and OV
Next, select the values of the OV and UV resistors, R1, R2, and R3, as shown in the typical system application
diagram Figure 41 . From the TPS2475x electrical specifications, VOVTHRESH = 1.35 V and VENTHRESH = 1.35 V.
VOV is the overvoltage trip voltage, which in this case is 14 V. VUV is the undervoltage trip voltage, which for this
example equals 8.4 V.
VOVTHRESH =
VENTHRESH =
R3
u VOV
R1 + R2 + R3
(12)
R2 + R3
u VUV
R1 + R2 + R3
(13)
Assume R3 is 1.5 kΩ and use Equation 12 to solve for (R1 + R2). Use Equation 13 and the (R1 + R2) from
Equation 12 to solve for R2 and finally for R1. From Equation 12, (R1 + R2) = 14.05 kΩ. From Equation 13, R2 = 1
kΩ and R1 = 13.05 kΩ. Scaling all three resistors by a factor of ten to use less supply current for these voltage
references and using standard 1% resistor values gives R1 = 130 kΩ, R2 = 10 kΩ, and R3 = 15 kΩ.
10.2.2.1.6 STEP 6. Choose R4, R5, and C1
As per the typical application diagram on the front page, R4, and R5 are required only if PGb, and FLTb are used;
these resistors serve as pull-ups for the open-drain output drivers. The current sunk by each of these pins must
not exceed 2 mA (refer to the Recommended Operating Conditions table). C1 is a bypass capacitor to help
control transient voltages, unit emissions, and local supply noise while in the disabled state. Where acceptable, a
value in the range of 0.001 μF to 0.1 μF is recommended.
30
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10.2.2.2 Alternative Design Example: Gate Capacitor (dv/dt) Control in Inrush Mode
The TPS2475x can be used in applications that expect a constant inrush current. This current is controlled by a
capacitor connected from the GATE terminal to GND. A resistor of 1 kΩ placed in series with this capacitor
prevents it from slowing a fast-turnoff event. In this mode of operation, the internal FET operates as a source
follower, and the slew rate of the output voltage approximately equals the slew rate of the gate voltage (see
Figure 43).
To implement a constant-inrush-current circuit, choose the time to charge, ∆t, using Equation 14.
C
´ VVCC
Dt = OUT
ICHG
(14)
where COUT is the output capacitance, VVCC is the input voltage, and ICHG is the desired charge current. Choose
ICHG < PLIM / VVCC to prevent power limiting from affecting the desired current.
To select the gate capacitance use Equation 15. where, IGATE is the nominal gate current and CINTRS, the
effective capacitance contributed by the internal FET (approximately 175 pF). In addition, the effect of other
capacitances like the capacitance offered by the usage of the Blocking FET (CBLK) and other component
capacitances CPR (due to external gate protection diodes, such as Zener diode and board parasitic) to be
accounted for arriving at exact value of CGATE. The TIMER capacitor, CT, must be programmed for timing greater
than the total turnon time (tON), to ensure and avoid fault detection during start-up.
Typical application circuit with Gate Capacitor (dV/dt) Control Inrush Mode is shown in Figure 43. The turnon
waveform with CGATE of 4.7 nF and series resistor of 1 kΩ is shown in Figure 44.
æ
Dt ö
CGATE = ç IGATE ´
÷ - CINTRS
V
VCC ø
è
(15)
To Load
From Source
CBLK
Part of
TPS24750
CPR
Other capacitances that
can be on board
GATE
CGATE
IG
30 A
1 kŸ
GND
Figure 43. Gate Capacitor (dV/dt) Control Inrush Mode.
10.2.2.3 Additional Design Considerations
10.2.2.3.1 Use of PGb
Use the PGb pin to control and coordinate a downstream dc/dc converter. If this is not done, then a long time
delay is needed to allow COUT to fully charge before the converter starts. An undesirable latch-up condition can
be created between the TPS2475x output characteristic and the dc/dc converter input characteristic if the
converter starts while COUT is still charging; using the PGb pin is one way to avoid this.
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10.2.2.3.2 Output Clamp Diode
Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a
current-limit event. The OUT pin ratings can be satisfied by connecting a diode from OUT to GND. The diode
must be selected to control the negative voltage at the full short-circuit current. Schottky diodes are generally
recommended for this application.
10.2.2.3.3 Gate Clamp Diode
The TPS2475x has a relatively well-regulated gate voltage of 12 V-15.5 V with a supply voltage VVCC higher than
4 V. For the applications with operating voltage greater than 14 V, a negative gate clamp (of ≤15.5 V) is needed
as shown in Figure 47. In addition, a series resistance of several hundred ohms or a series silicon diode is
recommended to prevent the output capacitance from discharging through the gate driver to ground. For
applications with Blocking FET, a small clamp Zener from gate to OUT is recommended if VGS of external
blocking FET is rated below 12 V.
10.2.2.3.4 Bypass Capacitors
It is a good practice to provide low-impedance ceramic capacitor bypassing of the VCC and OUT pins. Values in
the range of 10 nF to 1 µF are recommended. Some system topologies are insensitive to the values of these
capacitors; however, some are not and require minimization of the value of the bypass capacitor. Input
capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the lowimpedance power bus when inserted. This stresses the connector contacts and causes a short voltage sag on
the input bus. Small amounts of capacitance (that is, 10 nF to 0.1 µF) are often tolerable in these systems.
10.2.2.3.5 Output Short-Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
10 V/div
500 mV/div
VOUT
Gate
200 mV/div
I_IN
Timer
5 A/div
500 mV/div
5 A/div 10 V/div
5 V/div
10.2.3 Application Curves
Figure 44. Turnon with Gate Capacitor (dv/dt) Control
32
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Figure 45. Inrush Mode at Hot-Swap Circuit Insertion
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10.3 System Examples
Rsense
OUT
SENSE DRAIN
FLT
EN
PG
OV
IMON
GATE
GND
TIMER
RIMON
CT
RPROG
R4
R2
PROG
Output to Voltage Bus or
DC/DC Converter
VCC SET
CLOAD
Input Voltage Bus
R3
R1
RSET
Figure 46. Reverse Blocking Implementation
R3
VCC SET
SENSE
DRAIN
OUT
FLT
EN
PG
OV
IMON
GND
TIMER
CLOAD
PROG
RIMON
CT
RPROG
Z1
D2
R2
GATE
R4
Input Voltage Bus
R1
RSET
Output to Voltage Bus or
DC/DC Converter
Rsense
Figure 47. Negative Voltage Gate Protection
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System Examples (continued)
The TPS2475x can be configured as a high current load switch with low external part count. The schematic
diagram of load switch configuration is shown in Figure 48. The output voltage ramp rate is controlled with RC
circuit (Rgate and Cgate) at the Gate pin of the device. For detailed design process refer to the application note 12A Integrated Load Switch Using TPS24750/51.
Due to their robust protection features along with low RDS(on) of 3 mΩ integrated MOSFET and precise currentlimiting, the TPS2475x eFuses finds usage in power supply modules for Position Encoder Interfaces in
applications such as Servo Drives and Position Control. Refer to the following TI Designs for system usage
examples of the TPS2475x in these applications.
Power Supply with Programmable Output Voltage and Protection for Position Encoder Interfaces
SENSE DRAIN
FLT
EN
PG
OV
GATE
OUT
IMON
PROG
GND
TIMER
Cgate
Rgate
Output to Voltage Bus or
DC/DC Converter
VCC SET
CLOAD
Input Voltage Bus
Interface to a 5-V BiSS® Position Encoder
Figure 48. TPS2475x Configured as Simple 12-A Load Switch
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11 Power Supply Recommendations
The device is designed for supply voltage range of 2.5 V ≤ V(VCC) ≤ 18 V. If the input supply is located more than
a few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power
supply must be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.
11.1 Transient Thermal Impedance
TA = 25°C (unless otherwise stated)
1 in
TPS24750
Typ R JA = 62.3oC/W
Max R JA = 65oC/W
when mounted on a
1 inch2 (6.45-cm2) of
1oz.(0.0355-mm thick) Cu.
1 in
Copper
Figure 49. Board Details - Thermal Impedance Characteristic
10
ZqJA - Normalized Thermal Impedance
1
0.5
0.3
0.1
0.1
0.05
0.02
0.01
0.01
Duty Cycle = t1/t2
0.001
P
0.0001
t1
t2
0.00001
Typical RqJA = 62.3°C/W
TJ = P ´ ZqJA ´ RqJA
Single Pulse
0.000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
10k
tp - Pulse Duration - s
Figure 50. Transient Thermal Impedance with Test Board Details as Shown in Figure 49
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12 Layout
12.1 Layout Guidelines
The TPS2475x applications require careful attention to layout to ensure proper performance and to minimize
susceptibility to transients and noise. In general, all traces must be as short as possible, but the following list
deserves first consideration:
• Decoupling capacitors on VCC pin must have minimal trace lengths to the pin and to GND.
• Traces to SET and SENSE must be short and run side-by-side to maximize common-mode rejection. Kelvin
connections must be used at the points of contact with RSENSE. See Figure 51 and Figure 52 for a PCB layout
example.
• SET runs must be short on both sides of RSET.
• High current carrying Power path connections must be as short as possible and sized to carry at least twice
the full-load current, more if possible.
• Connections to IMON pin must be minimized after the previously described connections have been placed.
• The reference must should be a copper plane or island. Use via holes if necessary for direct connections of
components to their appropriate return ground plane or island.
• Thermal Considerations: When properly mounted the PowerPAD package provides significantly greater
cooling ability than an ordinary package. To operate at rated power, PowerPAD-2 must be soldered directly to
the PC board DRAIN plane directly under the device. The PowerPAD-2 is at the DRAIN potential and can be
connected using multiple vias to the inner and bottom layers of the DRAIN. The bottom side of the circuit
board is highly recommended to be used for DRAIN plane to increase heat sinking in higher current
applications. Refer to Technical Briefs: PowerPADTM Thermally Enhanced Package, SLMA002) and
PowerPAD™ Made Easy, SLMA004) for more information on using this PowerPad package.
• The thermal via land pattern specific to the TPS2475x can be downloaded from the device webpage.
• Protection devices such as snubbers, TVS, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, the
protection Schottky diode suggested to address transients due to heavy inductive loads, must be physically
close to the OUT pins.
12.2 Layout Example
RSET
LOAD CURRENT
PATH
VCC
VCC
SET
SET
SENSE
SENSE
RSENSEx
VCC
SET
SENSE
RSET
LOAD CURRENT
PATH
TPS24750
TPS24750
Method 1
Method 2
Figure 51. Recommended RSENSE Layout
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Layout Example (continued)
Top Layer
Top Layer Signal Ground Plane
Bottom Layer Drain plane
Via to Bottom Layer
Track in bottom or internal layer
BOTTOM LAYER (DRAIN PLANE)
Having DRAIN plane copper pour
area on bottom layer maximizes heat
sinking ability
RSENSE
VOUT
VIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
18
17
16
15
14
OUT
19
13 OUT
OUT
20
12 OUT
OUT
21
11 OUT
OUT
22
10 OUT
OUT 23
9
OUT
24
8
OUT
GATE 25
7
OUT
SENSE 26
6
OUT
DRAIN 27
5
DRAIN
GND 28
4
GND
VCC 29
3
SET
FLTb 30
2
IMON
PGb 31
1
OV
OUT
See Note 1
EN
PROG
36 GND
34
35 TIMER
33
32 GND
SIGNAL GROUND
TOP LAYER
Power Ground
(1)
Optional: Needed only to suppress the transients caused by inductive load switching.
Figure 52. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• PowerPADTM Thermally Enhanced Package (TI Literature Number
• PowerPAD™ Made Easy
• Power Supply with Programmable Output Voltage and Protection for Position Encoder Interfaces
• Interface to a 5-V BiSS® Position Encode
• 12-A Integrated Load Switch Using TPS24750/51
• TPS2475X EVM User Guide
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS24750
Click here
Click here
Click here
Click here
Click here
TPS24751
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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13.7 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS24750RUVR
ACTIVE
VQFN
RUV
36
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS24750
TPS24750RUVT
ACTIVE
VQFN
RUV
36
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS24750
TPS24751RUVR
ACTIVE
VQFN
RUV
36
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS24751
TPS24751RUVT
ACTIVE
VQFN
RUV
36
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS24751
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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