Typical Size
3,5 mm x 7 mm
TPS54617
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3-V TO 6-V INPUT, 6-A, SMALL SYNCHRONOUS-BUCK
SWITCHER WITH INTEGRATED FETs (SWIFT™)
FEATURES
1
DESCRIPTION
• 30-mΩ MOSFET Switches for High Efficiency
at 6-A Continuous Output
• Adjustable Output Voltage Down to 0.9 V With
1% Accuracy
• Externally Compensated for Design Flexibility
• Wide PWM Frequency: Fixed 350 kHz, 550 kHz,
or Adjustable 280 kHz to 1.6 MHz
• Synchronizable to 1.6MHz
• Load Protected by Peak Current Limit and
Thermal Shutdown
• Small 3.5mm x 7mm Package and Similar
Layout to TPS54610 Reduces Board Area and
Total Cost
• SWIFT Documentation Application Notes, and
SwitcherPro™ Software: www.ti.com/swift
23
As a member of the SWIFT™ family of dc/dc
regulators, the TPS54617 low-input voltage
high-output current synchronous buck PWM
converter offers the same features as the TPS54610
in a small package and higher switching frequency.
Included on the substrate with the listed features are
a true, high performance, voltage error amplifier that
enables maximum performance under transient
conditions and flexibility in choosing the output filter L
and C components; an undervoltage-lockout circuit to
prevent start-up until the input voltage reaches 3 V;
an internally and externally set slow-start circuit to
limit in-rush currents; and a power good output useful
for processor/logic reset, fault signaling, and supply
sequencing.
The TPS54617 is available in a thermally enhanced
34 pin QFN (RUV) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SwitcherPro™ design software tool
to aid in achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
APPLICATIONS
•
•
•
Low-Voltage, High-Density Systems With
Power Distributed at 3.3 V or 5 V
Point of Load Regulation for High Performance
DSPs, FPGAs, ASICs, and Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
SIMPLIFIED SCHEMATIC
EFFICIENCY vs OUTPUT CURRENT
TPS54617
Input
VIN
95
PH
89
Output
83
RT
SYNC
BOOT
PGND
Efficiency − %
SS/ENA
PWRGD
COMP
VBIAS
77
71
65
47
Compensation
Network
VI = 3.3 V
59
53
AGND VSENSE
VI = 3 V
VI = 5 V
41
35
VI = 6 V
fs = 1600 kHz
VO = 1.8 V
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
IO − Output Current − A
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SwitcherPro, SWIFT, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
TPS54617
SLVS880A – NOVEMBER 2008 – REVISED JANUARY 2009 ........................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TJ
–40°C to 125°C
(1)
(2)
OUTPUT VOLTAGE
PACKAGE
Adjustable down to 0.9 V
QFN (RUV)
PART NUMBER
(2)
TPS54617RUV
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
The RUV package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54617RUVR). See the application
section of this data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE / UNIT
VI
VO
Input voltage range
Output voltage range
SS/ENA, SYNC
–0.3 V to 7 V
RT
–0.3 V to 6 V
VSENSE
–0.3 V to 4 V
VIN
–0.3 V to 7 V
BOOT
–0.3 V to 17 V
VBIAS, PWRGD, COMP
–0.6 V to 7 V
PH
–0.6 V to 10 V
PH (transient < 10 nsec)
IO
IS
Source current
Sink current
Voltage differential
-2.0 V
PH
Internally Limited
COMP, VBIAS
6 mA
PH
12 A
COMP
6 mA
SS/ENA, PWRGD
10 mA
AGND to PGND
±0.3 V
TJ
Operating virtual junction temperature range
–40°C to 125°C
Tstg
Storage temperature
–65°C to 150°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
VI
Input voltage range
TJ
Operating junction temperature
2
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NOM
MAX
UNIT
3
6
V
–40
125
°C
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PACKAGE DISSIPATION RATINGS
(1)
(2)
(1)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
THERMAL IMPEDANCE
JUNCTION-TO-CASE
34-Pin RUV with solder
14.5°C/W
0.5 °C/W (2)
Test board conditions:
a. 3 inch × 3 inch, 4 layers, Thickness: 0.062 inch
b. 2.0 oz copper traces located on the top of the PCB
c. 2.0 oz copper ground plane on the bottom of the PCB
d. 2.0 oz copper ground planes on the 2 internal layers
e. 12 thermal vias
Maximum power dissipation may be limited by overcurrent protection.
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
VIN input voltage range
Quiescent current
3
6
fs = 350 kHz, SYNC ≤ 0.8 V, RT open, PH pin open
9.2
15.8
fs = 550 kHz, SYNC ≥ 2.5 V, RT open, PH pin open
13.9
23.5
1
1.4
2.95
3.0
Shutdown, SS/ENA = 0 V
V
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
2.70
Hysteresis voltage, UVLO
Rising and falling edge deglitch,
UVLO (1)
2.80
V
0.16
V
2.5
µs
BIAS VOLTAGE
VO
Output voltage, VBIAS
I(VBIAS) = 0
2.70
2.80
Output current, VBIAS (2)
2.90
V
100
µA
0.900
V
CUMULATIVE REFERENCE
Vref
Accuracy
0.882
0.891
REGULATION
Line regulation (1)
Load regulation (1)
IL = 3 A, fs = 350 kHz, TJ = 85°C
0.04
IL = 3 A, fs = 550 kHz, TJ = 85°C
0.04
IL = 0 A to 6 A, fs = 350 kHz, TJ = 85°C
0.03
IL = 0 A to 6 A, fs = 550 kHz, TJ = 85°C
0.03
%/V
%/A
OSCILLATOR
Internally set free-running frequency
range
SYNC ≤ 0.8 V, RT open
280
350
420
SYNC ≥ 2.5 V, RT open
440
550
660
Externally set free-running frequency
range
RT = 100 kΩ (1% resistor to AGND)
460
500
540
RT = 27 kΩ (1% resistor to AGND)
1480
1600
1720
High-level threshold voltage, SYNC
2.5
0.8
50
Frequency range, SYNC
330
Ramp valley (1)
Ramp amplitude (peak-to-peak) (1)
Minimum controllable on time
(1)
(2)
1600
V
kHz
0.75
V
1
V
160
Maximum duty cycle
kHz
V
Low-level threshold voltage, SYNC
Pulse duration, SYNC (1)
kHz
ns
90%
Specified by design
Static resistive loads only
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ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
90
110
3
5
MAX
UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain
Error amplifier unity gain bandwidth
1 kΩ COMP to AGND (3)
Parallel 10 kΩ, 160 pF COMP to AGND
Error amplifier common-mode input
voltage range
Powered by internal LDO
IIB
Input bias current, VSENSE
VSENSE = Vref
VO
Output voltage slew rate (symmetric),
COMP (3)
(3)
(3)
0
MHz
VBIAS
60
1
dB
250
1.4
V
nA
V/µs
PWM COMPARATOR
PWM comparator propagation delay
time, PWM comparator input to PH pin
(excluding dead time)
10 mV overdrive (3)
70
85
ns
1.20
1.40
V
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
0.82
Enable hysteresis voltage, SS/ENA(1)
Falling edge deglitch, SS/ENA(1)
Internal slow-start time
Charge current, SS/ENA
SS/ENA = 0 V
Discharge current, SS/ENA
SS/ENA = 1.3 V, VI = 1.5 V
0.03
V
2.5
µs
2.6
3.35
4.1
3
5
8
ms
µA
1.5
2.3
4
mA
POWER GOOD
Power good threshold voltage
VSENSE falling
Power good hysteresis voltage(1)
(1)
Power good falling edge deglitch
90
%Vref
3
%Vref
35
Output saturation voltage, PWRGD
I(sink) = 2.5 mA
Leakage current, PWRGD
VI = 5.5 V
0.18
µs
0.3
V
1
µA
CURRENT LIMIT
Current limit trip point
VI = 3 V(1), Output shorted
7.2
10
VI = 6 V(1), Output shorted
10
12
A
Current limit leading edge blanking
time (3)
100
ns
Current limit total response time (3)
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point(1)
135
(1)
Thermal shutdown hysteresis
150
165
10
°C
°C
OUTPUT POWER MOSFETS
rDS(on)
(3)
4
Power MOSFET switches
VI = 3 V
26
47
VI = 3.6 V
36
65
mΩ
Specified by design
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PIN ASSIGNMENTS
PGND
PGND
PGND
1
34
32
30 29
33
31
2
28
3
27
4
26
5
25
THERMAL
PAD
6
24
7
23
8
22
9
21
10
20
11
19
17 18
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
14 15 16
PGND
PGND
12 13
PGND
PGND
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PGND
PGND
RUV PACKAGE
(Top VIEW)
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor
and SYNC pin. Connect PowerPAD to AGND.
BOOT
5
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE.
PGND
13–20
30–34
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single
point connection to AGND is recommended.
PH
6–12
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or internal shutdown signal active.
RT
29
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA
27
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SYNC
28
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin
select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor
must be connected to the RT pin.
VBIAS
26
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low ESR 0.1-µF to 1-µF ceramic capacitor.
VIN
VSENSE
21–25
2
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high-quality, low-ESR 10-µF ceramic capacitor.
Error amplifier inverting input. Connect to output voltage compensation network/output divider.
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INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VIN
Enable
Comparator
SS/ENA
Falling
Edge
Deglitch
1.2 V
Hysteresis: 0.03 V
2.5 ms
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16 V
REG
VBIAS
SHUTDOWN
VIN
ILIM
Comparator
Thermal
Shutdown
o
150 C
3−4V
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
15 mW
2.5 ms
SS_DIS
SHUTDOWN
Internal/External
Slow-start
(Internal Slow-start Time = 3.35 ms
PH
+
−
R Q
Error
Amplifier
Reference
Vref = 0.891 V
PWM
Comparator
VO
CO
Adaptive Dead-Time
S
LOUT
and
Control Logic
VIN
15 mW
OSC
PGND
Powergood
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.90 Vref
TPS54617
Hysteresis: 0.03 Vref
VSENSE
COMP
RT
SHUTDOWN
35 ms
SYNC
RELATED DC/DC PRODUCTS
•
•
•
•
6
TPS40000 – dc/dc controller
TPS56300 – dc/dc controller
TPS54610 - SWIFT 6A converter
TPS54917 and TPS54910 - SWIFT 9A converters
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TYPICAL CHARACTERISTICS
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
40
35
30
25
20
−40
0
25
85
TJ − Junction Temperature − °C
HRds
25
LRds
20
15
−40
0
25
85
TJ − Junction Temperature − °C
650
SYNC ≥ 2.5 V
550
450
SYNC ≤ 0.8 V
350
250
−40
125
0
25
85
125
TJ − Junction Temperature − °C
Figure 1.
Figure 2.
Figure 3.
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
DEVICE POWER LOSSES
vs
LOAD CURRENT
5
0.895
4.5
VI = 3.3 V
o
Tj = 125 C
1600
RT = 27 kΩ
Vref − Voltage Reference − V
1400
Device Power Losses - W
0.893
0.891
1200
1000
0.889
800
4
3.5
3
2.5
2
1.5
1
0.887
RT = 100 kΩ
600
0.5
0
400
−40
0
25
85
TJ − Junction Temperature − °C
0.885
−40
125
1
0
0
25
85
TJ − Junction Temperature − °C
125
5
2
4
3
IL - Load Current - A
6
7
Figure 4.
Figure 5.
Figure 6.
OUTPUT VOLTAGE REGULATION
INPUT VOLTAGE
ERROR AMPLIFIER
vs
OPEN LOOP RESPONSE
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
0
140
RL = 10 kΩ,
CL = 160 pF,
TA = 25°C
120
0.893
3.80
−20
3.65
−40
100
−60
80
Gain − dB
0.891
0.889
Phase
−80
−100
60
−120
40
Gain
20
−140
−160
0.887
0.885
3
3.1
3.2
3.3
3.4
VI − Input Voltage − V
3.5
0
−180
−20
−200
1 k 10 k 100 k 1 M 10 M
3.6
Figure 7.
1
10
100
f − Frequency − Hz
Figure 8.
Internal Slow-Start Time − ms
0.895
Phase − Degrees
f − Externally Set Oscillator Frequency − kHz
30
125
1800
VO − Output Voltage Regulation − V
VI = 3.6 V
IO = 500 mA
35
750
f − Internally Set Oscillator Frequency − kHz
40
VI = 3 V
IO = 500 mA
Drain Source On-State Resistance − mΩ
Drain Source On-State Resistance − mΩ
45
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
3.50
3.35
3.20
3.05
2.90
2.75
−40
0
25
85
TJ − Junction Temperature − °C
Figure 9.
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APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical TPS54617 application. The TPS54617 (U1) can provide up
to 6A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the exposed
thermal PowerPAD underneath the integrated circuit, TPS54617, package must be soldered to the printed-circuit
board.
U1
TPS54617RUV
L1
0.82 mH
TP4
VOUT = 1.8 V, 6 A MAX
VIN = 3 - 6 V
C1
22 mF
C2
22 mF
C12
0.01 mF
R4
10.0 kW
C10
150 pF
C9
0.01 mF
C8
0.047 mF
C3
100 mF
C6
0.047 mF
R6
4.99 kW
C7
2700 pF
R5
27.4 kW
R8
10.0 kW
C4
100 mF
C5 1200 pF
C11
0.01 mF
R7 590 W
R1 10.0 kW
R2
10.0 kW
Analog and power grounds are ties at the pad under the package of the IC
Figure 10. Application Circuit
COMPONENT SELECTION
INPUT FILTER
The values for the components used in this design
example were selected for best load transient
response and small PCB area. Additional design
information is available at www.ti.com.
The input voltage is a nominal 3.3 or 5 VDC. The
input filter capacitors (C1 and C2) are 10-µF ceramic
capacitors (MuRata). C12 is a 0.01-µF ceramic
capacitor that provides high-frequency decoupling of
the TPS54617 from the input supply. C1, C2 and C12
must be located as close as possible to the device.
Input ripple current is shared among C1, C2 and C12.
8
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FEEDBACK CIRCUIT
The values for these components are selected to
provide fast transient response times.
The resistor divider network of R1 and R2 sets the
output voltage for the circuit at 1.8 V. R1 along with
R6, R7, C5, C7, and C10 forms the loop
compensation network for the circuit. For this design,
a Type-3 topology is used. The feedback loop is
compensated so that the closed loop crossover
frequency is approximately 45 kHz at 5 V input.
OPERATING FREQUENCY
In the application circuit, RT is grounded through a
27.4-kΩ resistor to select the operating frequency of
1.6 MHz. To set a different frequency, place a 27-kΩ
to 180-kΩ resistor between RT (pin 29) and analog
ground or leave RT floating to select the default of
350 kHz. The switching frequency in MHz can be
approximated using the following equation:
51000
FSW =
(RT + 4400 )
(1)
OUTPUT FILTER
The output filter is composed of a 0.82-µH inductor
and 2 × 100-µF capacitors. The inductor is a Vishay
IHLM-2525CZ-01 type. The capacitors used are
100-µF, 6.3-V ceramic types with X5R dielectric.
PCB LAYOUT
Figure 11 shows a generalized PCB layout guide for
the TPS54617. The VIN pins should be connected
together on the printed circuit board (PCB) and
bypassed with a low ESR ceramic bypass capacitor.
Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN
pins, and the TPS54617 ground pins. The minimum
recommended bypass capacitance is 10 µF ceramic
with a X5R or X7R dielectric and the optimum
placement is closest to the VIN pins and the PGND
pins.
The TPS54617 has two internal grounds (analog and
power). The analog ground ties to all of the
noise-sensitive signals, while the power ground ties to
the noisier power signals. Noise injected between the
two grounds can degrade the performance of the
TPS54617, particularly at higher output currents.
Ground noise on an analog ground plane can also
cause problems with some of the control and bias
signals. For these reasons, separate analog and
power ground traces are recommended. There
should be an area of ground on the top layer directly
under the IC, with an exposed area for connection to
the PowerPAD. Use vias to connect this ground area
to any internal ground planes. Use additional vias at
the ground side of the input and output filter
capacitors as well. The AGND and PGND pins should
be tied to the PCB ground by connecting them to the
ground area under the device as shown. Use a
separate wide traces for the analog ground signal
path. This analog ground should be used for the
voltage set point divider, timing resistor RT, slow start
capacitor, and bias capacitor grounds. Connect this
trace the topside groud area near AGND (Pin 1).
The PH pins should be tied together and routed to
the output inductor. Since the PH connection is the
switching node, the inductor should be located very
close to the PH pins and the area of the PCB
conductor minimized to prevent excessive capacitive
coupling.
Connect the boot capacitor between the phase node
and the BOOT pin as shown. Keep the boot capacitor
close to the IC and minimize the conductor trace
lengths.
Connect the output filter capacitor(s) as shown
between the VOUT trace and PGND. It is important to
keep the loop formed by the PH pins, Lout, Cout and
PGND as small as practical.
Place the compensation components from the VOUT
trace to the VSENSE and COMP pins. Do not place
these components too close to the PH trace. Due to
the size of the IC package and the device pinout, the
components will have to be routed somewhat close,
but maintain as much separation as possible while
still keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to
analog ground using the isolated analog ground
trace. If a slow-start capacitor or RT resistor is used,
or if the SYNC pin is used to select 350 kHz
operating frequency, connect them to this trace as
well.
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VOUT
TOPSIDE
GROUND
AREA
PGND
PH
PH
PGND
EXPOSED
POWERPAD
AREA
PGND
VIN
Vin
INPUT
BULK
FILTER
INPUT
BYPASS
CAPACITOR
OUTPUT
INDUCTOR
PGND
PGND
PGND
PGND
PGND
OUTPUT
FILTER
CAPACITOR
PH
PH
PH
VIN
PH
VIN
PH
VIN
PH
VIN
BOOT
VBIAS
PWRGD
SS/ENA
COMP
SYNC
VSENSE
BOOT
CAPACITOR
COMPENSATION
NETWORK
BIAS CAPACITOR
RT
AGND
PGND
PGND
PGND
PGND
PGND
SLOW START
CAPACITOR
FREQUENCY SET RESISTOR
ANALOG GROUND TRACE
ANALOG GROUND TRACE
VIA to Ground Plane
Figure 11. TPS54617 PCB Layout
Estimated Circuit Area
The estimated printed circuit board area for the components used in the design of Figure 11 is 0.55 in2. This area
does not include test points or connectors.
heat, and any area available must be used when 6 A
or greater operation is desired. Connection from the
LAYOUT CONSIDERATIONS FOR THERMAL
exposed area of the PowerPAD to the analog ground
PERFORMANCE
plane layer must be made using 0.013-inch diameter
The RUV package has been chosen to enable a
vias to avoid solder wicking through the vias.
thermal management scheme, allowing a ground
12 vias must be in the PowerPAD area located under
plane to extend beyond both ends of the package.
the device package. Additional vias beyond the
For operation at full rated load current, the analog
twelve recommended may be added in the ground
ground plane must provide an adequate heat
area outside the package footprint to enhance
dissipating area. A 3-inch by 3-inch plane of 1 ounce
thermal performance. The size of the vias outside of
copper is recommended, though not mandatory,
the package, not in the exposed thermal pad area,
depending on ambient temperature and airflow. Most
can be increased to 0.018.
applications have larger areas of internal ground
plane available, and the PowerPAD must be
connected to the largest area available. Additional
areas on the top or bottom layers also help dissipate
10
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PERFORMANCE GRAPHS
EFFICIENCY
vs
OUTPUT CURRENT
LOAD REGULATION
vs
OUTPUT CURRENT
89
Percent Deviation - %
Efficiency − %
83
77
71
VI = 3 V
VI = 3.3 V
VI = 5 V
65
59
VI = 6 V
53
fs = 1600 kHz
VO = 1.8 V
47
41
35
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
IO − Output Current − A
0.3
0.25
VI = 3 V
VI = 5 V
fs = 1600 kHz
o
TA = 25 C
VO = 1.8 V
0
1
2
fs = 1600 kHz
TA = 25oC
VO = 1.8 V
0.2
VI = 3.3 V
Percent Deviation - %
95
LINE REGULATION
vs
INPUT VOLTAGE
VI = 6 V
0.15
0.1
IO = 0 A
0.05
0
-0.05
-0.1
IO = 3 A
-0.15
-0.2
IO = 6 A
-0.25
3
4
5
-0.3
6
3
3.5
4
4.5
5
5.5
IO − Output Current − A
VI − Input Voltage − V
Figure 12.
Figure 13.
Figure 14.
AMBIENT TEMPERATURE
vs
LOAD CURRENT(1)
OUTPUT RIPPLE VOLTAGE
TRANSIENT RESPONSE
6
100
75
Tj = 125°C
50
VI = 3.3 V
VO = 1.8 V
fs = 1600 kHz
25
0
1
2
3
4
5
6
7
8
fs = 1600 kHz
VO = 6 A
VO − Output Voltage − 10 mV/div
Output Ripple Voltage − 10 mV/div
Ambient Temperature - oC
125
VI = 5 V
VO = 1.8 V
VI = 5 V
VO = 1.8 V
t − Time − 1 ms/div
t − Time − 5 ms/div
Figure 15.
Figure 16.
Figure 17.
SLOW-START TIMING
INPUT RIPPLE VOLTAGE
CLOSED LOOP RESPONSE
180 deg
60 dB
150 deg
t − Time − 5 ms/div
Figure 18.
1-Phase
40 dB
fs = 1600 kHz
VO = 6 A
VI = 5 V
VO = 1.8 V
t − Time − 1 ms/div
Figure 19.
120 deg
30 dB
90 deg
20 dB
60 deg
10 dB
Gain
0.047 mF
Slow-Start Capacitor
Input Ripple Voltage − 10 mV/div
50 dB
1-Gain
30 deg
0 dB
0 deg
-10 dB
-30 deg
-20 dB
-60 deg
-30 dB
-90 deg
Phase
VI = 5 V
VO = 1.8 V
VO − Output Voltage − 1 mV/div
VI − Input Voltage − 1 mV/div
IO − Output Current − A
-40 dB
-120 deg
-50 dB
-150 deg
-60 dB
100 Hz
-180 deg
1 kHz
10 kHz
100 kHz
1M
Frequency
Figure 20.
(1)
Safe operating area is applicable to the test board conditions listed in the dissipation rating table section of this
data sheet.
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VBIAS Regulator (VBIAS)
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
The TPS54617 incorporates an under voltage lockout
circuit to keep the device disabled when the input
voltage (VIN) is insufficient. During power up, internal
circuits are held inactive until VIN exceeds the
nominal UVLO threshold voltage of 2.95 V. Once the
UVLO start threshold is reached, device start-up
begins. The device operates until VIN falls below the
nominal UVLO stop threshold of 2.8 V. Hysteresis in
the UVLO comparator, and a 2.5-µs rising and falling
edge deglitch circuit reduce the likelihood of shutting
the device down due to noise on VIN.
Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions.
First, the pin acts as an enable (shutdown) control by
keeping the device turned off until the voltage
exceeds the start threshold voltage of approximately
1.2 V. When SS/ENA exceeds the enable threshold,
device start-up begins. The reference voltage fed to
the error amplifier is linearly ramped up from 0 V to
0.891 V in 3.35 ms. Similarly, the converter output
voltage reaches regulation in approximately 3.35 ms.
Voltage hysteresis and a 2.5-µs falling edge deglitch
circuit reduce the likelihood of triggering the enable
due to noise.
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with
a low-value capacitor connected between SS/ENA
and AGND.
Adding a capacitor to the SS/ENA pin has two effects
on start-up. First, a delay occurs between release of
the SS/ENA pin and start-up of the output. The delay
is proportional to the slow-start capacitor value and
lasts until the SS/ENA pin reaches the enable
threshold. The start-up delay is approximately:
1.2 V
t +C
d
(SS)
5 mA
(2)
Second, as the output becomes active, a brief
ramp-up at the internal slow-start rate may be
observed before the externally set slow-start rate
takes control and the output rises at a rate
proportional to the slow-start capacitor. The slow-start
time set by the capacitor is approximately:
0.7 V
t
+C
(SS)
(SS)
5 mA
(3)
The VBIAS regulator provides internal analog and
digital blocks with a stable supply voltage over
variations in junction temperature and input voltage. A
high quality, low-ESR, ceramic bypass capacitor is
required on the VBIAS pin. X7R or X5R grade
dielectrics are recommended because their values
are more stable over temperature. The bypass
capacitor must be placed close to the VBIAS pin and
returned to AGND.
External loading on VBIAS is allowed, with the
caution that internal circuits require a minimum
VBIAS of 2.70 V, and external loads on VBIAS with
ac or digital switching noise may degrade
performance. The VBIAS pin may be useful as a
reference voltage for external circuits.
Voltage Reference
The voltage reference system produces a precise
Vref signal by scaling the output of a temperature
stable bandgap circuit. During manufacture, the
bandgap and scaling circuits are trimmed to produce
0.891 V at the output of the error amplifier, with the
amplifier connected as a voltage follower. The trim
procedure adds to the high precision regulation of the
TPS54617, since it cancels offset errors in the scale
and error amplifier circuits.
Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the SYNC pin as
a static digital input. If a different frequency of
operation is required for the application, the oscillator
frequency can be externally adjusted from 280 to
1600 kHz by connecting a resistor between the RT
pin to ground and floating the SYNC pin. The
switching frequency in MHz is approximated by the
following equation, where R is the resistance in Ohms
from RT to AGND:
51000
FSW =
(RT + 4400 )
(4)
External synchronization of the PWM ramp is
possible over the frequency range of 330 kHz to 1600
kHz by driving a synchronization signal into SYNC
and connecting a resistor from RT to AGND. Choose
a RT resistor that sets the free running frequency to
80% of the synchronization signal. Table 1
summarizes the frequency selection configurations:
The actual slow-start time is likely to be less than the
above approximation due to the brief ramp-up at the
internal rate.
12
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Table 1. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz to 1.6MHz
Float
R = 27 k to 180 k
Externally synchronized frequency
Synchronization signal
R = RT value for 80% of external synchronization frequency
Error Amplifier
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54617 apart from most dc/dc
converters. The user is given the flexibility to use a
wide range of output L and C filter components to suit
the particular application needs. Type-2 or Type-3
compensation can be employed using external
compensation components.
PWM Control
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the
control logic includes the PWM comparator, OR gate,
PWM latch, and portions of the adaptive dead-time
and control-logic block. During steady-state operation
below the current limit threshold, the PWM
comparator output and oscillator pulse train
alternately reset and set the PWM latch. Once the
PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse width.
During this period, the PWM ramp discharges rapidly
to its valley voltage. When the ramp begins to charge
back up, the low-side FET turns off and high-side
FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator
resets the latch, thus turning off the high-side FET
and turning on the low-side FET. The low-side FET
remains on until the next oscillator pulse discharges
the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or
above the PWM peak voltage. If the error amplifier is
high, the PWM latch is never reset, and the high-side
FET remains on until the oscillator pulse signals the
control logic to turn the high-side FET off and the
low-side FET on. The device operates at its
maximum duty cycle until the output voltage rises to
the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually
reset and the high-side FET does not turn on. The
low-side FET remains on until the VSENSE voltage
decreases to a range that allows the PWM
comparator to change states. The TPS54617 is
capable of sinking current continuously until the
output reaches the regulation set-point.
If the current limit comparator trips for longer than
100 ns, the PWM latch resets before the PWM ramp
exceeds the error amplifier output. The high-side FET
turns off and low-side FET turns on to decrease the
energy in the output inductor and consequently the
output current. This process is repeated each cycle in
which the current limit comparator is tripped.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power
MOSFETs during the switching transitions by actively
controlling the turnon times of the MOSFET drivers.
The high-side driver does not turn on until the voltage
at the gate of the low-side FET is below 2 V. While
the low-side driver does not turn on until the voltage
at the gate of the high-side MOSFET is below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to drive the power
MOSFETs gates. The low-side driver is supplied from
VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency
and reduces external component count.
Overcurrent Protection
The cycle-by-cycle current limiting is achieved by
sensing the current flowing through the high-side
MOSFET and comparing this signal to a preset
overcurrent threshold. The high side MOSFET is
turned off within 200 ns of reaching the current limit
threshold. A 100-ns leading edge blanking circuit
prevents current limit false tripping. Current limit
detection occurs only when current flows from VIN to
PH when sourcing current to the output filter. Load
protection during current sink operation is provided by
thermal shutdown.
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Thermal Shutdown
Power Good (PWRGD)
The device uses the thermal shutdown to turn off the
power MOSFETs and disable the controller if the
junction temperature exceeds 150°C. The device is
released from shutdown automatically when the
junction temperature decreases to 10°C below the
thermal shutdown trip point, and starts up under
control of the slow-start circuit.
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is
10% below the reference voltage, the open-drain
PWRGD output is pulled low. PWRGD is also pulled
low if VIN is less than the UVLO threshold or SS/ENA
is low. When VIN ≥ UVLO threshold, SS/ENA ≥
enable threshold, and VSENSE > 90% of Vref, the
open drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35 µs
falling edge deglitch circuit prevent tripping of the
power good comparator due to high frequency noise.
Thermal shutdown provides protection when an
overload condition is sustained for several
milliseconds. With a persistent fault condition, the
device cycles continuously; starting up by control of
the soft-start circuit, heating up due to the fault
condition, and then shutting down upon reaching the
thermal shutdown trip point. This sequence repeats
until the fault condition is removed.
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PACKAGE OPTION ADDENDUM
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13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54617RUVR
ACTIVE
VQFN
RUV
34
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
54617
TPS54617RUVR/2801
ACTIVE
VQFN
RUV
34
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
54617
TPS54617RUVT
ACTIVE
VQFN
RUV
34
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
54617
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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