TPS3813J25, TPS3813L30, TPS3813K33, TPS3813I50
SLVS331I – DECEMBER 2000 – REVISED OCTOBER 2021
TPS3813xxx Family Processor Supervisory Circuits With Window-Watchdog
1 Features
3 Description
•
The TPS3813xxx family of supervisory circuits provide
circuit initialization and timing supervision, primarily
for DSPs and processor-based systems.
•
•
•
•
•
•
Window-watchdog with programmable delay and
window ratio
6-Pin SOT-23 package
Supply current of 9 µA (Typical)
Power-on reset generator with a fixed delay time of
25 ms
Precision supply voltage monitor (VIT):
2.5 V, 3 V, 3.3 V, and 5 V
Open-drain reset output
Temperature range: –40°C to 85°C
2 Applications
•
•
•
•
•
•
Active Antenna System mMIMO (AAS)
Storage area network
Electricity meters
Safety critical systems
Infustion pump
HVAC controller
VDD
0.1 µF
0.1 µF
R
VDD
VDD
WDR
RESET
TPS3813
WDT
CWP
WDI
GND
RESET
µC
I/O
GND
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Typical Operating Circuit
During power on, RESET is asserted when supply
voltage (VDD) becomes higher than 1.1 V. Thereafter,
the supervisory circuit monitors VDD and keeps
RESET active as long as VDD remains below the
threshold voltage (VIT). An internal timer delays the
return of the output to the inactive state (high) to
ensure proper system reset. The delay time,
td = 25 ms typical, starts after VDD has risen above
the threshold voltage (VIT). When the supply voltage
drops below the threshold voltage (VIT), the output
becomes active (low) again. No external components
are required. All the devices of this family have a
fixed-sense threshold voltage (VIT) set by an internal
voltage divider.
For safety critical applications the TPS3813xxx
family incorporates a so-called window-watchdog
with programmable delay and window ratio. The
upper limit of the watchdog time-out can be set
by either connecting WDT to GND, VDD, or using
an external capacitor. The lower limit and thus the
window ratio is set by connecting WDR to GND or
VDD. The supervised processor now needs to trigger
the TPS3813xxx within this window not to assert a
RESET.
The product spectrum is designed for supply voltages
of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available
in a 6-pin SOT-23 package.
The TPS3813xxx devices are characterized for
operation over a temperature range of –40°C to 85°C.
Device Information
(1)
PART NUMBER
PACKAGE (1)
BODY SIZE (NOM)
TPS3813xxx
SOT-23 (6)
2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3813J25, TPS3813L30, TPS3813K33, TPS3813I50
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SLVS331I – DECEMBER 2000 – REVISED OCTOBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements.................................................. 6
7.7 Switching Characteristics............................................7
7.8 Dissipation Ratings..................................................... 7
7.9 Typical Characteristics................................................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................11
8.5 Programming............................................................ 12
9 Application and Implementation.................................. 14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
10 Power Supply Recommendations..............................16
11 Layout........................................................................... 17
11.1 Layout Guidelines................................................... 17
11.2 Layout Example...................................................... 17
12 Device and Documentation Support..........................18
12.1 Related Links.......................................................... 18
12.2 Receiving Notification of Documentation Updates..18
12.3 Support Resources................................................. 18
12.4 Trademarks............................................................. 18
12.5 Electrostatic Discharge Caution..............................18
12.6 Glossary..................................................................18
13 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (February 2016) to Revision I (October 2021)
Page
• Changed tw parameter name to tGI_VIT in 7.6 Timing Requirements section and added Glitch immunity VIT in
parameter definition. .......................................................................................................................................... 6
• Added Input Voltage (VDD), VDD Hysteresis, and VDD Glitch Immunity sections into datasheet...................10
Changes from Revision G (October 2013) to Revision H (February 2016)
Page
• Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ........... 1
• Changed "Power up reset voltage" to "Power-on rest voltage" in Electrical Characteristics ............................. 6
• Changed the function table in Device Functional Modes .................................................................................11
• Updated text in Implementing Window-Watchdog Settings section..................................................................12
Changes from Revision F (August 2012) to Revision G (October 2013)
Page
• Changed voltage from 0.6 V to 1.1 V for bottom figure...................................................................................... 7
Changes from Revision E (October 2010) to Revision F (August 2012)
Page
• Changed from Rev E to Rev F, August 2012......................................................................................................1
• Deleted the Pull-up resistor value row in the ROC table.................................................................................... 5
Changes from Revision D (October 2010) to Revision E (October 2010)
Page
• Added Pull-up resistor value to ROC table for RESET ......................................................................................5
Changes from Revision C (April, 2008) to Revision D ()
Page
• Changed external capacitor value recommendations in paragraph 2 of Programmable Window-Watchdog
section.............................................................................................................................................................. 13
• Added Power-Up Considerations section......................................................................................................... 13
2
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•
SLVS331I – DECEMBER 2000 – REVISED OCTOBER 2021
Changed Figure 9-1 .........................................................................................................................................14
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SLVS331I – DECEMBER 2000 – REVISED OCTOBER 2021
5 Device Comparison Table
TA (1)
–40°C to +85°C
(1)
DEVICE NAME
THRESHOLD VOLTAGE
MARKING
TPS3813J25DBV
2.25 V
PCDI
TPS3813L30DBV
2.64 V
PEZI
TPS3813K33DBV
2.93 V
PFAI
TPS3813I50DBV
4.55 V
PFBI
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
6 Pin Configuration and Functions
WDI
1
6
RESET
GND
2
5
WDR
WDT
3
4
VDD
Figure 6-1. DBV Package
6-Pin SOT-23
Top View
Table 6-1. Pin Functions
PIN
4
I/O
DESCRIPTION
NO.
NAME
1
WDI
I
Watchdog timer input. This input must be driven at all times and not left floating.
2
GND
I
Ground
3
WDT
I
Programmable watchdog delay input
4
VDD
I
Supply voltage and supervising input
5
WDR
I
Selectable watchdog window ratio input. This input must be tied to VDD or GND and not left floating.
6
RESET
O
Open-drain reset output
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SLVS331I – DECEMBER 2000 – REVISED OCTOBER 2021
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
MIN
Supply voltage (2)
VDD
MAX
UNIT
7
V
RESET
–0.3
VDD + 0.3
V
All other pins (2)
–0.3
7
V
IOL
Maximum low output current
5
mA
IOH
Maximum high output current
–5
mA
IIK
Input clamp current (VI < 0 or VI > VDD)
±20
mA
IOK
Output clamp current (VO < 0 or VO > VDD)
±20
mA
Continuous total power dissipation
See Section 7.8
Soldering temperature
260
°C
TA
Operating free-air temperature
–40
85
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t = 1000h
continuously.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
At specified temperature range.
VDD
Supply voltage
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
Δt/ΔV
Input transition rise and fall rate
tw
Pulse width of WDI trigger pulse
TA
Operating free-air temperature
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MIN
MAX
2
6
V
0
VDD + 0.3
V
0.7 × VDD
V
0.3 × VDD
V
100
ns/V
85
°C
50
–40
UNIT
ns
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7.4 Thermal Information
TPS3813xxx
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
208.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
123.3
°C/W
RθJB
Junction-to-board thermal resistance
37.2
°C/W
ψJT
Junction-to-top characterization parameter
14.6
°C/W
ψJB
Junction-to-board characterization parameter
36.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted).
PARAMETER
VOL
Low-level output voltage
VPOR
Power up reset voltage (1)
VIT
Negative-going input threshold
voltage (2)
TEST CONDITIONS
MIN
VDD = 2 V to 6 V, IOL = 500 µA
0.2
VDD = 3.3 V IOL = 2 mA
0.4
VDD = 6 V, IOL = 4 mA
0.4
VDD ≥ 1.1 V, IOL = 50 µA
0.2
TPS3813J25
2.2
2.25
2.3
TPS3813L30
2.58
2.64
2.7
2.87
2.93
3
4.45
4.55
4.65
TPS3813K33
TA = –40°C to +85°C
TPS3813I50
VHYS
Hysteresis
TPS3813J25
30
TPS3813L30
35
TPS3813K33
40
TPS3813I50
IIH
High-level input current
IIL
Low-level input current
IOH
High-level output current
IDD
Supply current
Ci
Input capacitance
(1)
(2)
TYP MAX
UNIT
V
V
V
mV
60
WDI, WDR
WDI = VDD = 6 V, WDR = VDD = 6 V
WDT
WDT = VDD = 6 V, VDD > VIT, RESET =
High
WDI, WDR
WDI = 0 V, WDR = 0 V, VDD = 6 V
WDT
WDT = 0 V, VDD > VIT, RESET = High
–25
25
–100
100
–25
25
–100
100
VDD = VIT + 0.2 V, VOH = VDD
25
VDD = 2-V output unconnected
9
13
VDD = 5-V output unconnected
20
25
VI = 0 V to VDD
5
nA
nA
µA
pF
The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.
To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) must be placed near to the supply terminals.
7.6 Timing Requirements
At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to +85°C.
MIN
tGI_VIT Glitch immunity VIT (Pulse width at VDD)
6
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VDD = VIT + 0.2 V, VDD = VIT – 0.2 V
3
TYP
MAX
UNIT
µs
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7.7 Switching Characteristics
At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to +85°C.
PARAMETER
td
tt(out)
TEST CONDITIONS
Delay time
Watchdog time-out
Upper limit
MIN
20
25
30
WDT = 0 V
0.2
0.25
0.3
WDT = VDD
2
2.5
3
WDT = programmable (1)
See (2)
WDR = 0 V, WDT = 0 V
1:31.8
WDR = 0 V, WDT = VDD
1:32
tPHL
(1)
(2)
VDD to RESET delay
UNIT
ms
s
ms
1:25.8
WDR = VDD, WDT = 0 V
1:124.9
WDR = VDD, WDT = VDD
1:127.7
WDR = VDD, WDT = programmable
Propagation (delay) time,
high-to-low-level output
MAX
VDD ≥ VIT + 0.2 V, See Figure 7-1
WDR = 0 V, WDT = programmable
Watchdog window ratio
TYP
1:64.5
VIL = VIT – 0.2 V, VIH = VIT + 0.2 V
30
50
µs
155 pF < C(ext) < 63 nF
(C(ext) ÷ 15.55 pF + 1) × 6.25 ms
7.8 Dissipation Ratings
PACKAGE
TA < 25°C POWER
RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 80°C
POWER RATING
DBV
437 mW
3.5 mW/°C
280 mW
227 mW
VDD
VIT
1.1 V
t
td
td
td
RESET
Output Condition
Undefined
Output Condition
Undefined
t
WDI
1st Window
Without Lower
Boundary
t
2nd Window
With Lower
Boundary
3rd Window
With Lower
Boundary
Trigger Pulse
1st Window
Lower Window
Without Lower 2nd Window
Boundary
Boundary
1st Window
With Lower
Without Lower
Boundary
Boundary
3rd Window
With Lower
Boundary
Figure 7-1. Timing Diagram
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7.9 Typical Characteristics
2
20
WDI = GND,
WDT = GND,
WDR = GND
16
85°C
14
12
25°C
10
8
−40°C
6
0°C
4
1.50
25°C
1.25
1
0.75
85°C
0°C
0.50
−40°C
0.25
2
0
VDD = 2 V,
WDI = GND,
WDT = GND,
WDR = GND
1.75
VOL − Low-Level Output Voltage − V
I DD − Supply Current − mA
18
0
1
2
3
5
4
0
6
0
1
VDD − Supply Voltage − V
1000
800
I − Input Current − nA
25°C
400
85°C
200
0°C
0
−200
−40°C
−400
I
VDD = 6 V,
WDI = GND,
WDR = GND
−600
−800
−1000
0
1
2
3
3
4
5
6
7
Figure 7-3. Low-Level Output Voltage vs Low-Level
Output Current
VIT − Normalized Input Threshold Voltage − V (25 ° C)
Figure 7-2. Supply Current vs Supply Voltage
600
2
IOL − Low-Level Output Current − mA
4
5
6
1.001
1.000
0.999
0.998
0.997
WDI = Triggered,
WDR = GND,
WDT = GND
0.996
0.995
−40
VI − Input Voltage at WDT − V
−20
0
20
40
60
80
TA − Free-Air Temperature At VDD − °C
Figure 7-4. Input Current vs Input Voltage at WDT
Figure 7-5. Normalized Input Threshold Voltage vs
Free-Air Temperature at VDD
t W − Minimum Pulse Duration at V DD − ms
20
18
16
14
12
10
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
VDD − Threshold Overdrive Voltage − V
Figure 7-6. Minimum Pulse Duration at VDD vs VDD Threshold Overdrive Voltage
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8 Detailed Description
8.1 Overview
The TPS3813xxx family of supervisory circuits provide circuit initialization and timing supervision signals. During
power on, RESET is asserted (low) when the supply voltage (VDD) increases above 1.1 V. Thereafter, the
supervisory circuit monitors VDD and keeps RESET low as long as VDD remains below the threshold voltage
(VIT). Once VDD increases above VIT, an internal timer delays the deassertion of the output to allow for a proper
system reset before RESET transitions to a high state. The delay time (td) is 25 ms typical and starts after VDD
rises above the VIT. When the supply voltage drops below VIT, the output transitions low again. All the devices of
this family have a fixed threshold voltage set by an internal voltage divider.
The TPS3813xxx family incorporates a so-called window-watchdog timer, which has a programmable delay
and window ratio. The supervised processor must trigger the WDI pin of the TPS3813xxx within the userprogrammable window to keep RESET from asserting. The upper limit of the watchdog time-out can be set by
either connecting WDT to GND, VDD, or using an external capacitor. The lower limit and thus the window ratio is
set by connecting WDR to GND or VDD.
8.2 Functional Block Diagram
RESET
Oscillator
WDT
Reset Logic
and Timer
Detection
Circuit
VDD
GND
Power t o c ircuitry
R1
+
_
Watchdog
Ratio
Detection
WDR
R2
Bandgap
Voltage
Reference
GND
GND
Rising Edge
Detection
WDI
GND
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8.3 Feature Description
The TPS3813xxx family incorporates both a voltage supervisor and a window-watchdog timer into a single
device. The device monitors the input voltage and the supervised processor must trigger the WDI pin of the
TPS3813xxx within the user-programmable window to keep RESET from asserting.
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8.3.1 Input Voltage (VDD)
VDD pin is monitored by the internal comparator with integrated reference to indicate when VDD falls below the
fixed threshold voltage. VDD also functions as the supply for the following:
•
•
•
•
•
Internal bandgap (reference voltage)
Internal regulator
State machine
Buffers
Other control logic blocks
Good design practice involves placing a 0.1 µF to 1 µF bypass capacitor at VDD input for noisy applications and
to ensure enough charge is available for the device to power up correctly. The reset output is undefined when
VDD is below VPOR.
8.3.1.1 VDD Hysteresis
The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD
pin falls below the falling voltage threshold VIT, the output reset is asserted. When the voltage at the VDD pin
rises above the rising voltage threshold (VIT+ = VIT + VHYS), the output reset is deasserted after tD reset time
delay.
8.3.1.2 VDD Glitch Immunity
These devices are immune to quick voltage transient or excursion on VDD. Sensitivity to transients depends on
both pulse duration (t GI_VIT) found in Section 7.6 and transient overdrive. Overdrive is defined by how much VDD
exceeds the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as
shown in Equation 1.
Overdrive = | ((VDD / VIT) – 1) × 100% |
(1)
where
•
•
•
VIT = VIT- is the threshold voltage
VIT+ = VIT + VHYS is the rising threshold voltage
VDD is the input voltage crossing VIT
VDD
VIT+
VITOverdrive
Pulse
Duration
Figure 8-1. Overdrive Versus Pulse Duration
TPS3813xxx devices have built-in glitch immunity (tGI_VIT) as shown in Section 7.6. Figure 8-1 shows that VDD
must fall below VIT for tGI_VIT, otherwise the faling transistion is ignored. When VDD falls below VIT for tGI_VIT,
RESET transitions low to indicate a fault condition after the propagation delay high-to-low (tPHL). When VDD
rises above VIT+ = VIT + VHYS, RESET deasserts to a logic high indicating there is no more fault condition only if
VDD remains above VIT+ for longer than the reset delay (tD).
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8.3.2 User-Programmable Watchdog Timer (WDI)
The TPS3813xxx family of devices have a watchdog timer that must be periodically triggered by either a positive
or negative transition at the WDI pin to avoid a reset signal being issued. When the supervising system fails to
retrigger the watchdog circuit within the time-out interval, tt(out), RESET becomes asserts for the time period td.
This event also reinitializes the watchdog timer. After the reset of the supervisor is released, the lower boundary
of the first WDI window is disabled. After the first WDI low-to-high transition is detected, the lower boundary
function of the window is enabled. All further WDI pulses must fit into the configured window frame.
Both the upper and lower boundary of the window can be adjusted by the user. See Section 8.5 for more details
on how to set the upper and lower boundaries of the window.
8.3.3 RESET Output
RESET remains high (deasserted) as long as VDD is above the threshold voltage (VIT) and the user-programable
watchdog timer criteria are met. If VDD falls below the VIT or if WDI is not triggered within the appropriate window,
then RESET is asserted, driving the RESET pin to a low impedance.
When VDD is once again above VIT, a delay circuit is enabled that holds RESET low for a specified reset delay
period (td) which is 25 ms typical. When the reset delay has elapsed, the RESET pin goes to a high-impedance
state and uses a pullup resistor to hold RESET high. Connect the pullup resistor to the proper voltage rail to
enable the outputs to be connected to other devices at the correct interface voltage level. RESET can be pulled
up to any voltage up to 6 V, independent of the device supply voltage. To ensure proper voltage levels, give
some consideration when choosing the pullup resistor value and consider the required low-level output voltage
(VOL), the output capacitive loading, and the output leakage current.
8.4 Device Functional Modes
Table 8-1 summarizes the various functional modes of the device.
Table 8-1. TPS3813xxx Function/Truth Table
VDD
WDI
RESET
VDD < VPOR
—
Undefined
VPOR < VDD < VIT
—
L
VDD > VIT
Outside window
L
VDD > VIT
Inside window
H
8.4.1 Normal Operation (VDD > VIT)
When VDD is greater than VIT, the RESET signal is determined by the last WDI pulse.
• WDI pulse inside window: as long as pulses occur within the user-programmable window, the RESET signal
remains high.
• WDI pulse outside window: if a pulse occurs outside the user-programmable window or not at all, the RESET
signal goes low.
8.4.2 Above Power-On Reset But Less Than Threshold (VPOR < VDD < VIT)
When the voltage on VDD is less than the VIT voltage, and greater than the power-on reset voltage (VPOR), the
RESET signal is asserted regardless of the WDI signal.
8.4.3 Below Power-On Reset (VDD < VPOR)
When the voltage on VDD is lower than VPOR, the device does not have enough voltage to internally pull the
asserted output low, and RESET is undefined and must not be relied upon for proper device function.
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8.5 Programming
8.5.1 Implementing Window-Watchdog Settings
There are two ways to configure the watchdog timer window the most flexible is to connect a capacitor to WDT
to set the upper boundary of the window watchdog while connecting WDR to either VDD or GND, thus setting the
lower boundary. The other way to configure the timing is by wiring the WDT and WDR pin to either VDD or GND.
By hardwiring the pins to either VDD or GND there are four different timings available; these settings are listed in
Table 8-2.
Table 8-2. Cap-Free Timer Settings
SELECTED OPERATION MODE
WDR = 0 V
WDT = 0 V
WDR = VDD
WDR = 0 V
WDT = VDD
WDR = VDD
WINDOW FRAME
LOWER WINDOW FRAME
Max = 0.3 s
Max = 9.46 ms
Typ = 0.25 s
Typ = 7.86 ms
Min = 0.2 s
Min = 6.27 ms
Max = 0.3 s
Max = 2.43 ms
Typ = 0.25 s
Typ = 2 ms
Min = 0.2 s
Min = 1.58 ms
Max = 3 s
Max = 93.8 ms
Typ = 2.5 s
Typ = 78.2 ms
Min = 2 s
Min = 62.5 ms
Max = 3 s
Max = 23.5 ms
Typ = 2.5 s
Typ = 19.6 ms
Min = 2 s
Min = 15.6 ms
To visualize the values named in the table, a timing diagram was prepared. It is used to describe the upper and
lower boundary settings. For an application, the important boundaries are the tboundary,max and twindow,min. Within
these values, the watchdog timer must be retriggered to avoid a time-out condition or a boundary violation in
the event of a trigger pulse in the lower boundary. The values in the table above are typical and worst-case
conditions. They are valid over the whole temperature range of –40°C to +85°C.
In the shaded area of Figure 8-2, it cannot be predicted if the device detects a violation or not and release a
reset. This is also the case between the boundary tolerance of tboundary,min and tboundary,max as well as between
twindow,min and twindow,max. It is important to set up the trigger pulses accordingly to avoid violations in these areas.
WDI
Detection of
Rising Edge
Window Frame to Reset the WDI
tboundary, min
tboundary, max
t
tboundary, typ
twindow, typ
twindow, min
twindow, max
Figure 8-2. Upper and Lower Boundary Visualization
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8.5.2 Programmable Window-Watchdog by Using an External Capacitor
The upper boundary of the watchdog timer can be set by an external capacitor connected between the WDT
pin and GND. Common consumer electronic capacitors can be used to implement this feature. They must have
low ESR and low tolerances because the tolerances have to be considered if the calculations are performed.
The first formula is used to calculate the upper window frame. After calculating the upper window frame, the
lower boundary can be calculated. As in the last example, the most important values are the tboundary,max and
twindow,min. The trigger pulse has to fit into this window frame.
The external capacitor must have a value between a minimum of 155 pF and a maximum of 63 nF.
Table 8-3. Setting Upper Window Using External Capacitor
SELECTED OPERATION MODE
WDT = external capacitor C(ext)
t
window,typ
+
ǒ
WINDOW FRAME
WDR = 0 V and WDR = VDD
Ǔ
C
(ext)
)1
15.55 pF
twindow,max = 1.25 × twindow,typ
twindow,min = 0.75 × twindow,typ
6.25 ms
(2)
8.5.3 Lower Boundary Calculation
The lower boundary can be calculated based on the values given in Section 7.7. Additionally, facts must be
considered to verify that the lower boundary is where it is expected. Because the internal oscillator of the window
watchdog is running free, any rising edge at the WDI pin is considered at the next internal clock cycle. This
happens regardless of the external source. Because the shift between internal and external clock is not known, it
is best to consider the worst-case condition for calculating this value.
Table 8-4. Setting Lower Boundary Using External Cap
SELECTED OPERATION MODE
LOWER BOUNDARY OF FRAME
tboundary,max = twindow,max / 23.5
WDR = 0 V
tboundary,typ = twindow,typ / 25.8
tboundary,min = twindow,min / 28.7
WDT = external capacitor C(ext)
tboundary,max = twindow,max / 51.6
WDR = VDD
tboundary,typ = twindow,typ / 64.5
tboundary,min = twindow,min / 92.7
8.5.4 Watchdog Software Considerations
To benefit from the window watchdog feature and help the watchdog timer monitor the software execution more
closely, TI recommends that the watchdog be set and reset at different points in the program rather than pulsing
the watchdog input periodically by using the prescaler of a microcontroller or DSP. Furthermore, the watchdog
trigger pulses must be set to different timings inside the window frame to release a defined reset, if the program
must hang in any subroutine. This allows the window watchdog to detect time-outs of the trigger pulse, as well
as pulses that distort the lower boundary.
8.5.5 Power-Up Considerations
Many microcontrollers use general-purpose input and output (GPIO) pins that can be programmed to be either
inputs or outputs. During power-up, these I/O pins are typically configured as inputs. If a GPIO pin is used to
drive the WDI input pin of the TPS3813xxx, then a pulldown resistor (shown as R2 in Figure 9-1) must be added
to keep the WDI pin from floating during power up.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS3813xxx is a voltage supervisor that incorporates a window-watchdog timer, allowing for comprehensive
supervision of microcontrollers and other similar devices. The TPS3813xxx can be operated from a VDD rail of 2
V to 6 V with a user-programmable watchdog time-out from 0.25 s to 2.5 s. The following sections describe how
to properly use this device, depending on the requirements of the final application.
9.2 Typical Application
A typical application example (see Figure 9-1) is used to describe the function of the watchdog in more detail. To
configure the window watchdog function, two pins are provided by the TPS3813xxx. These pins set the window
time-out and ratio. The window watchdog ratio is a fixed ratio, which determines the lower boundary of the
window frame. It can be configured in two different frame sizes.
VDD
0.1 F
0.1 F
VDD
R1
Position 1
Position 2
VDD
WDR
RESET
RESET
μC
TPS3813
Position 4
Position 5
Position 3
I/O
WDI
WDT
C(ext)
VDD
(A)
GND
GND
R2
VDD
Copyright © 2016, Texas Instruments Incorporated
A.
Use this pulldown resistor if a GPIO pin is used to drive the WDI input pin of the TPS3813xxx to keep the WDI pin from floating during
power up.
Figure 9-1. Application Example
9.2.1 Design Requirements
The TPS3813xxx RESET output can be used to drive the RESET pin of a microcontroller to initiate a reset
event. The RESET pin of the TPS3813xxx can be pulled high with a 1-MΩ resistor; the watchdog window
timing is controlled by the WDT and WDR pins, and is set depending on the reset requirement times of the
microprocessor.
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9.2.2 Detailed Design Procedure
If the window watchdog ratio pin (WDR) is set to VDD, Position 1 in Figure 9-1, then the lower window frame is
a value based on a ratio calculation of the overall window time-out size: For the watchdog time-out pin (WDT)
connected to GND, it is a ratio of 1:124.9, for WDT connected to VDD, it is a ratio of 1:127.7, and for an external
capacitor connected to WDT, it is a ratio of 1:64.5.
If the window watchdog ratio pin (WDR) is set to GND, Position 2, the lower window frame is a value based on
a ratio calculation of the overall window time-out size: For the watchdog time-out pin (WDT) connected to GND,
it is a ratio of 1:31.8, for WDT connected to VDD it is 1:32, and for an external capacitor connected to WDT it is
1:25.8.
The watchdog time-out can be set in two fixed timings of 0.25 seconds and 2.5 seconds for the window or can by
programmed by connecting a external capacitor with a low leakage current at WDT.
Example: If the watchdog time-out pin (WDT) is connected to VDD, the time-out is 2.5 seconds. If the window
watchdog ratio pin (WDR) is set in this configuration to a ratio of 1:127.7 by connecting the pin to VDD, the lower
boundary is 19.6 ms.
9.2.3 Application Curve
t W − Minimum Pulse Duration at V DD − ms
20
18
16
14
12
10
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
VDD − Threshold Overdrive Voltage − V
Figure 9-2. Minimum Pulse Duration at VDD vs VDD Threshold Overdrive Voltage
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10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range from 2 V to 6 V. An input
supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice
is to place a 0.1-µF capacitor between the VDD pin and the GND pin. This device has a 7-V absolute maximum
rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage transient
that can exceed 7 V, additional precautions must be taken.
In applications where the WDI input may experience a negative voltage while VDD is ramping from 0 V to 0.8 V,
the VDD slew rate in this range must be greater than 10 V/s. A negative voltage on the WDI input along with a
slew rate less than 10 V/s could result in a greatly reduced watchdog window time and reset output delay time.
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11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic bypass capacitor near the VDD pin.
11.2 Layout Example
Pullup
Voltage
RESET
Flag
TPS3813
WDI
Signal
1
6
2
4
3
4
CVDD
Figure 11-1. TPS3813xxx Layout Example
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS3813J25
Click here
Click here
Click here
Click here
Click here
TPS3813L30
Click here
Click here
Click here
Click here
Click here
TPS3813K33
Click here
Click here
Click here
Click here
Click here
TPS3813I50
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS3813I50DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFBI
Samples
TPS3813I50DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFBI
Samples
TPS3813J25DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCDI
Samples
TPS3813J25DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCDI
Samples
TPS3813K33DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFAI
Samples
TPS3813K33DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFAI
Samples
TPS3813K33DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFAI
Samples
TPS3813L30DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PEZI
Samples
TPS3813L30DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PEZI
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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