Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TPS53313
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
TPS53313 6-A Step-Down Regulator With Integrated Switcher
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4.5-V to 16-V Conversion Voltage Range
Adjustable Output Voltage Ranging from 0.6 V to
0.7 × VIN
Continuous 6-A Output Current
Supports All MLCC Output Capacitors
Selectable SKIP Mode or Forced CCM
Selectable Soft-Start Time (1 ms, 3 ms, or 6 ms)
Selectable 4-5 A, 6-A or 9-A Peak Current Limit
Optimized Efficiency at Light and Heavy Loads
Voltage Mode Control
Programmable Switching Frequency from 250 kHz
to 1.5 MHz
Synchronizes to External Clock
RDS(on) Sensing for Zero Crossing Detection and
Overcurrent Protection
Soft-Stop Output Discharge During Disable
Overcurrent, Overvoltage, and Undervoltage
Protection With Hiccup
Overtemperature Protection
Open-Drain, Power Good Indication
Internal Bootstrap Switch
4 mm × 4 mm, 24-Pin VQFN Package
POL Applications for 5-V
12-V Step-Down Rails
3 Description
TPS53313 provides a 5-V or 12-V synchronous buck
converter that integrates two N-Channel MOSFETs.
Due to low RDS(on) and TI proprietary SmoothPWM™
skip mode of operation, it optimizes the efficiency at
light-load condition without compromising the output
voltage ripple.
The TPS53313 features programmable (from 250
kHz to 1.5 MHz) switching frequency with selectable
skip mode or forced CCM mode operation. The
device provides prebiased startup, soft-stop,
integrated bootstrap switch, power good function, and
EN/input UVLO protection. It supports input voltages
from 4.5 V to 16 V and no extra bias voltage is
needed. The output voltage is adjustable from 0.6 V
up to 0.7 × VIN.
The TPS53313 is available in a 4 mm × 4 mm, 24-pin
VQFN package (Green RoHs compliant and Pb free)
and operates from –40°C to 85°C.
Device Information(1)
PART NUMBER
TPS53313
PACKAGE
VQFN (24)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
Output All MLCCs
VIN
VOUT
BP7
VIN
CBST
SW
VIN
VBST
BP3
AGND
EN
TPS53313
PG
PGOOD
EN
RT/SYNC
FB
MODE/SS
PowerPad
COMP
PGND
UDG-11254
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53313
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
6
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2011) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
2
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
TPS53313
www.ti.com
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
FB
COMP
MODE/SS
RT/SYNC
AGND
BP3
24
23
22
21
20
19
RGE Package
24-Pin VQFN
Top View
EN
1
18
BP7
PG
2
17
VBST
VIN
3
16
SW
VIN
4
15
SW
VIN
5
14
SW
VIN
6
13
SW
7
8
9
10
11
12
PGND
PGND
PGND
PGND
PGND
PGND
EP
Not to scale
Pin Functions
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
1
EN
I
Enable pin
2
PG
O
Power good output flag. Open drain output. Pull up to an external rail through a resistor.
3
VIN
P
Gate driver supply and power conversion voltage
4
VIN
P
Gate driver supply and power conversion voltage
5
VIN
P
Gate driver supply and power conversion voltage
6
VIN
P
Gate driver supply and power conversion voltage
7
PGND
P
Device power ground terminal
8
PGND
P
Device power ground terminal
9
PGND
P
Device power ground terminal
10
PGND
P
Device power ground terminal
11
PGND
P
Device power ground terminal
12
PGND
P
Device power ground terminal
13
SW
O
Output inductor connection to integrated power devices
14
SW
O
Output inductor connection to integrated power devices
15
SW
O
Output inductor connection to integrated power devices
16
SW
O
Output inductor connection to integrated power devices
17
VBST
P
Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW terminal.
18
BP7
P
Bias for internal circuitry and driver
19
BP3
P
Input bias supply for analog functions
20
AGND
G
Device analog ground terminal
21
RT/SYNC
I/O
Synchronized to external clock. Program the switching frequency by connecting with a resistor to GND.
(1)
B = Bidirectional, G = Ground, I = Input, O = Output, P = Supply
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
3
TPS53313
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
www.ti.com
Pin Functions (continued)
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
22
MODE/SS
I
Mode configuration pin. Connect with a resistor to GND sets different modes and soft-start time, parallel
a capacitor (or no capacitor) with the resistor changes the current limit threshold. Shorting MODE/SS pin
to supply inhibits the device; shorting MODE/SS pin to AGND is equivalent to 10-kΩ resistor setting is
not recommended (see Table 1 and Table 2 for resistor and capacitor settings).
23
COMP
O
Error amplifier compensation terminal. Type III compensation method is generally recommended for
stability.
24
FB
I
Voltage feedback pin. Use for OVP, UVP, and power good determination
4
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
TPS53313
www.ti.com
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
Input voltage
MIN
MAX
VIN
–0.3
20
VBST
–0.3
27
VBST to SW
–0.3
7
DC
–2
20
transient < 20 ns
–3
20
SW (bidirectional)
V
VVIN ≥ 17
–0.3
17
VVIN < 17
–0.3
VVIN + 0.1
FB, MODE/SS
–0.3
3.6
COMP, RT/SYNC, BP3
–0.3
3.6
BP7
–0.3
7
PGD
–0.3
17
–0.3
0.3
EN
Output voltage
UNIT
Ground pin (GND)
Output current
V
V
6
A
Operating temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the corresponding LL terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2)
VIN (main supply)
Input voltage
Output voltage
MIN
MAX
4.5
16
VBST
–0.1
22
VBST to SW
–0.1
6.5
dc
–1
18
transient < 20 ns
–2
18
EN
–0.1
VVIN + 0.1
FB, MODE/SS
–0.1
3.5
COMP, RT/SYNC, BP3
–0.1
3.5
BP7
–0.1
6.5
PGD
SW (bidirectional)
UNIT
V
V
–0.1
14
Ground pin (GND)
–0.1
0.1
V
TA
Ambient temperature
–40
85
°C
TJ
Junction temperature
–40
125
°C
(1)
(2)
Voltage values are with respect to the corresponding LL terminal.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
5
TPS53313
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
www.ti.com
6.4 Thermal Information
TPS53313
THERMAL METRIC (1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
44.1
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
35
°C/W
Junction-to-board thermal resistance
19
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
18.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
8.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range, VVIN = 12 V, PGND = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.23
4.4
UNIT
INPUT SUPPLY
VVIN
VIN supply voltage
Nominal input voltage range
VPOR
VIN POR threshold
Ramp up, EN = HIGH
VPOR(hys)
VIN POR hysteresis
ISTBY
Standby current
RBOOT
Bootstrap on-resistance
VVREF
Internal precision reference
voltage
TOLVREF
VREF tolerance
4.5
4
EN = LOW, VIN = 12 V
16
V
V
200
mV
58
µA
10
Ω
0.6
V
REFERENCE
–1%
1%
ERROR AMPLIFIER
UGBW (1)
Unity gain bandwidth
14
AOL (1)
Open loop gain
80
IFBINT
FB input leakage current
IEA(max)
SR
(1)
Sourced from FB pin
MHz
dB
50
nA
Output sinking and sourcing
current
5
mA
Slew rate
5
V/µs
ENABLE
RENPD (1)
Enable pulldown resistor
VENH
EN logic high
VVIN = 4.5 V
VENHYS
EN hysteresis
VVIN = 4.5 V
IEN
EN pin current
800
kΩ
1.8
V
0.6
VEN = 0 V
V
1
VEN = 3.3 V
3.3
5
VEN = 14 V
17.8
27.5
EN = High
0.65
µA
SOFT-START
tSS_1
Delay after EN asserts
tSS_2
Soft start ramp_up time
tPGDENDLY
(1)
6
PGD startup delay time
0 V ≤ VSS ≤ 0.6 V, 39-kΩ or no resistor to
MODE/SS pin
1
0 V ≤ VSS ≤ 0.6 V, 20-kΩ or 160-kΩ resistor to
MODE/SS pin
3
0 V ≤ VSS ≤ 0.6 V, 10-kΩ or 82-kΩ resistor to
MODE/SS pin
6
VSS = 0.6 V to PGD (SSOK) going high,
tSS = 1 ms
0.2
ms
ms
ms
Ensured by design. Not production tested.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
TPS53313
www.ti.com
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
Electrical Characteristics (continued)
over operating free-air temperature range, VVIN = 12 V, PGND = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RAMP
Ramp amplitude
4.5 V ≤ VVIN ≤ 14.4 V
VVIN/9
14.4 V ≤ VVIN ≤ 16 V
1.6
150
V
PWM
tMIN(off)
Minimum OFF time
fSW = 1 MHz
tMIN(on)
Minimum ON time
No load
DMAX
Maximum duty cycle
fSW = 1 MHz
ns
90
ns
80%
SWITCHING FREQUENCY
fSW
Switching frequency tolerance
fSW = 1 MHz, RT = 45.3 kΩ
–10%
10%
SOFT DISCHARGE
RSFTDIS
Soft-discharge transistor
resistance
EN = Low, VIN = 4.5 V, VOUT = 0.6 V
120
Ω
When IOUT exceeds this threshold for 4
consecutive cycles, 2.2-nF capacitor to
MODE/SS pin
4.5
A
When IOUT exceeds this threshold for 4
consecutive cycles, no capacitor to MODE/SS pin
6
A
When IOUT exceeds this threshold for 4
consecutive cycles, 10-nF capacitor to MODE/SS
pin
9
OVERCURRENT AND ZERO CROSSING
IOCPL
IOCPH
VZXOFF
Overcurrent limit on high-side
FET (peak)
One time overcurrent shut-off on
the low-side FET (peak)
Immediately shut down when sensed current
reach this value, 2.2-nF capacitor to MODE/SS
pin
4.5
A
Immediately shut down when sensed current
reach this value, no capacitor to MODE/SS pin
6
A
Immediately shut down when sensed current
reach this value, 10-nF capacitor to MODE/SS
pin
9
Zero crossing comparator internal
SW – PGND, SKIP mode
offset
–3
mV
POWER GOOD
VPGDL
Power good low threshold
Measured at the FB pin w/r/t VREF
80%
83%
86%
VPGDH
Power good high threshold
Measured at the FB pin w/r/t VREF
114%
117%
120%
VPG(hys)
Power good hysteresis
VIN(min_pg)
Minimum Vin voltage for valid PG
at startup.
Measured at VIN with 1-mA (or 2-mA) sink current
on PG pin at startup
VPG(pd)
Power good pull-down voltage
Pull down voltage with 4-mA sink current
0.2
0.4
V
IPG(leak)
Power good leakage current
Hi-Z leakage current, apply 3.3-V in off state
12
16.2
µA
2
1
V
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
TOVPDLY
Overvoltage protection delay time Time from FB out of +17% of VREF to OVP fault
TUVPDLY
Undervoltage protection delay
time
Time from FB out of –17% of VREF to UVP fault
2
µs
10
µs
THERMAL SHUTDOWN
THSD (1)
Thermal shutdown
Shutdown controller, attempt soft-stop
THSDHYST (1)
Thermal shutdown hysteresis
Controller restarts after temperature drops
130
140
150
40
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
°C
°C
7
TPS53313
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
www.ti.com
6.6 Typical Characteristics
16
100
Sourcing Current
Sinking Current
No Load
12
90
Efficiency (%)
Minimum Duty Cycle (%)
14
10
8
6
80
70
60
4
50
2
0
200
400
600
800
1000
1200
Switching Frequency (kHz)
1400
40
1600
0
1
90
90
80
80
Efficiency (%)
Efficiency (%)
100
70
60
TA = –40°C
TA = 25°C
TA = 85°C
VIN = 5 V
VOUT = 1.2 V
0
1
2
3
4
Load Current (A)
5
40
6
G002
TA = –40°C
TA = 25°C
TA = 85°C
VIN = 14 V
VOUT = 1.2 V
0
1
2
G002
3
4
Load Current (A)
5
6
G002
Figure 4. Efficiency, VIN = 14 V
1600
88
1400
87
PGOOD Lower Threshold (%)
Switching Frequency (kHz)
6
60
50
1200
1000
800
600
400
200
With Respect to VSEN
86
85
84
83
82
81
80
79
25
50
75
100 125 150 175
Timing Resistance (kΩ)
200
225
250
78
−40 −25 −10
G005
Figure 5. Switching Frequency
vs Timing Resistance (RT)
8
5
70
Figure 3. Efficiency, VIN = 5 V
0
3
4
Load Current (A)
Figure 2. Efficiency, VIN = 12 V
100
40
2
G001
Figure 1. Ensured Minimum Duty Ratio
50
TA = –40°C
TA = 25°C
TA = 85°C
VIN = 12 V
VOUT = 1.2 V
Submit Documentation Feedback
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G006
Figure 6. PGOOD Lower Threshold
vs Junction Temperature
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
TPS53313
www.ti.com
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
Typical Characteristics (continued)
2.0
119
With Respect to VSEN
1.5
118
MODE/SS Leakage (µA)
PGOOD Upper Threshold (%)
120
117
116
115
114
113
112
1.0
0.5
0.0
−0.5
−1.0
−1.5
111
110
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
−2.0
−40 −25 −10
110 125
G007
95
110 125
G008
Figure 8. MODE/SS Leakage Current
vs Junction Temperature
10
10
9
9
PGOOD Upper Hysteresis (%)
PGOOD Lower Hysteresis (%)
Figure 7. PGOOD Upper Threshold
vs Junction Temperature
5
20 35 50 65 80
Junction Temperature (°C)
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
0
−40 −25 −10
G009
Figure 9. PGOOD Lower Hysteresis
vs Junction Temperature
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G010
Figure 10. PGOOD Upper Hysteresis
vs Junction Temperature
340
160−kΩ Resistor to RT/SYNC Pin
Switching Frequency (kHz)
330
320
310
300
290
280
270
260
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G011
Figure 11. Switching Frequency vs Junction Temperature
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
9
TPS53313
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
www.ti.com
7 Detailed Description
7.1 Overview
The TPS53313 is a high-efficiency switching regulator with two integrated N-channel MOSFETs and is capable
of delivering up to 6 A of load current. The TPS53316 provides output voltage from 0.6 V up to 0.7 × VIN from
4.5-V to 16-V wide input voltage range. The output voltage accuracy is better than ±1% over load, line, and
temperature.
This device can operate in either forced continuous conduction mode (FCCM) or skip mode with selectable softstart time to fit various application needs. Skip mode operation provides reduced power loss and increases the
efficiency at light load. The unique, patented PWM modulator enables smooth light load to heavy load transition
while maintaining fast load transient.
7.2 Functional Block Diagram
BP3
BP7
VIN
TPS53313
LDO
LDO
VIN UVLO
0.6 V
VBST
0.6 V±17%
UV/OV
Threshold
Generation
+
FB
0.6 V+17%
+
UV
UV
OV
OV
Control
Logic
HDRV
PWM
E/A
+
COMP
+
0.6 V
Ramp
SW
+
XCON
Skip or FCCM
PWM
VOUT Discharge
SS
LDRV
PGND
Osc
Enable
Control
Mode/SS
RT/SYNC
EN
MODE/SS
OCP Logic
PG
AGND
UDG-11255
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Soft-Start Operation
The soft-start operation reduces the inrush current during the start-up time. A slow rising reference is generated
by the soft-start circuitry and sent to the input of the error amplifier. When the soft-start ramp voltage is less than
600 mV, the error amplifier uses this ramp voltage as the reference. When the ramp voltage reaches 600 mV, a
fixed 600-mV reference voltage is used for the error amplifier. The soft-start time has selectable values of 1 ms,
3 ms, and 6 ms.
10
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
TPS53313
www.ti.com
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
Feature Description (continued)
7.3.2 Power Good
The TPS53313 monitors the output voltage through the FB pin. If the FB voltage is within 117% and 83% of the
reference voltage, the power good signal remains high. If the FB voltage is outside of this range, the PG pin pin
is pulled low by the internal open drain output.
During start up, the power good signal has a 200-µs delay after the FB voltage falls into the power good range
limit when the soft-start time is set to 1 ms. There is also 10-µs delay during shut down.
7.3.3 UVLO Function
The TPS53313 provides UVLO protection for input voltage, VIN. If the input voltage is lower than UVLO
threshold voltage minus the hysteresis, the device shut off. When the voltage rises above the threshold voltage,
the device restarts. The typical UVLO rising threshold is 4.23 V. Hysteresis of 200 mV for input voltage is
provided to prevent glitch.
7.3.4 Overcurrent (OC) Protection
The TPS53313 provides peak current protection and continuously monitors the current flowing through high-side
and low-side MOSFETs. If the current through the high-side FET exceeds the current limit threshold, the highside FET turns off and the low-side FET turns on. An overcurrent (OC) counter starts to increment every
switching cycle to count the occurrence of the overcurrent events. The converter shuts down immediately when
the OC counter reaches 4. The OC counter resets if the detected current is less than 6 A (with 6-A OC setting)
after an OC event.
Another set of overcurrent circuitry monitors the current through low-side FET. If the current through the low-side
FET exceeds 6 A (with 6-A OC setting), the overcurrent protection is engaged and turns off both high-side and
low-side FETs immediately.
Therefore, the device is fully protected against overcurrent during both on-time and off-time. Also, the OC
threshold is selectable and can be set to 4.5 A, 6 A, or 9 A by connecting different capacitor in parallel with
MODE/SS pin. After OC events, the device stops switching and enters hiccup mode. A re-start is attempted after
a hiccup waiting time. If the fault condition is not cleared, hiccup mode operation may continue indefinitely
7.3.5 Overvoltage and Undervoltage Protection
The TPS53313 monitors the voltage divided feedback voltage to detect the overvoltage and undervoltage
conditions. When the feedback voltage is greater than 117% of the reference, overvoltage protection is triggered,
the high-side MOSFET turns off and the low-side MOSFET turns on. Then the output voltage drops and the FB
voltage reaches the undervoltage threshold. At that point the low-side MOSFET turns off and the device goes
into tri-state logic.
When the feedback voltage is lower than 83% of the reference voltage, the undervoltage protection counter
starts. If the feedback voltage remains lower than the undervoltage threshold voltage after 10 µs, the device
turns off both the high-side and low-side MOSFETs and then goes into tri-state logic.
After the undervoltage events, the device stops switching and enters hiccup mode. A restart is attempted after a
hiccup waiting time. If the fault condition is not cleared, hiccup mode operation may continue indefinitely.
7.3.6 Overtemperature Protection
The TPS53313 continuously monitors the die temperature. If the die temperature exceeds the threshold value
(140°C typical), the device shuts off. When the device is cooled to 40°C below the overtemperature threshold, it
restarts and returns to normal operation.
7.3.7 Output Discharge
When the EN pin is low, the TPS53313 discharges the output capacitors through an internal MOSFET switch
between SW and GND while the high-side and low-side MOSFETs are maintained in the OFF state. The typical
discharge switch on resistance is 120 Ω. This function is disabled when VVIN is less than 1 V.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
11
TPS53313
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
www.ti.com
Feature Description (continued)
7.3.8 Switching Frequency Setting and Synchronization
The clock frequency is programmed by the value of the resistor connected from the RT/SYNC pin to GND. The
switching frequency is programmable between 250 kHz and 1.5 MHz.
Also, TPS53313 is able to synchronize to external clock. The synchronization is fulfilled by connecting the
RT/SYNC pin to external clock source. If no external pulse is received from RT/SYNC pin, the device continues
to operate the internal clock.
7.4 Device Functional Modes
7.4.1 Operation Mode
The TPS53313 has 6 operation modes determined by the MODE/SS pin connection as listed in Table 1. The
current limit thresholds and associated capacitance selections are shown in Table 2.
Table 1. Operation Mode Selection
MODE/SS PIN
CONNECTION
OPERATION MODE
tSS SOFT-START
TIME (ms)
10 kΩ to GND
FCCM
6
20 kΩ to GND
FCCM
3
39 kΩ to GND
FCCM
1
82 kΩ to GND
Skip mode
6
160 kΩ to GND
Skip mode
3
Floating
Skip mode
1
Table 2. Capacitor Selection
MODE/SS PIN SETTING (nF)
CURRENT LIMIT THRESHOLD
(A)
No capacitor
6
2.2
4.5
10
9
In forced continuous conduction mode (FCCM), the high-side FET is ON during the on-time and low-side FET is
ON during the off-time. The switching is synchronized to the internal clock thus the switching frequency is fixed.
In this mode, the switching frequency remains constant over the entire load range which is suitable for
applications that need tight control of switching frequency.
In skip mode, the high-side FET is on during the on-time and low-side FET is on during the off-time until the
inductor current reaches zero. An internal zero-crossing comparator detects the zero crossing of inductor current
from positive to negative. When the inductor current reaches zero, the comparator sends a signal to the logic
control and turns off the low-side FET. The on-pulse in skip mode is designed to be 25% higher than CCM to
provide hysteresis to avoid chattering between CCM and skip mode.
Also, the overcurrent protection threshold can be set to 4.5 A, 6 A or 9 A by changing the capacitor that is in
parallel with MODE/SS pin. Specifically, a 6-A current limit threshold is set without an external capacitor, the 4.5
A current limit threshold is set with a 2.2-nF capacitor, and the 9-A current limit threshold is set when a 10-nF
capacitor is in parallel with MODE/SS pin.
7.4.2 Light Load Operation
In skip mode, when the load current is less than half of inductor ripple current, the inductor current reaches zero
by the end of OFF-Time. The light load control scheme then turns off the low-side MOSFET when inductor
current reaches zero. Since there is no negative inductor current, the energy delivered to the load per switching
cycle is increased compared to the normal PWM mode operation. The controller then reduces the switching
frequency to maintain the output voltage regulation. The switching loss is reduced and thus efficiency is
improved.
12
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
TPS53313
www.ti.com
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
In skip mode, when the load current decreases, the switching frequency also decreases continuously in
discontinuous conduction mode (DCM). When the load current is 0 A, the minimum switching frequency is
reached. It is also required that the difference between VVBST and VSW to be higher than 3.3 V to ensure the
supply for high-side gate driver.
IL(ripple)/2
Output Current
Internal Clock
PWM, FCCM
PWM, Skip Mode
No Zero-Crossing for two
PWM cycles, and the
device enters CCM
In Skip mode, the PWM sync to
internal clock after entering CCM
UDG-11279
Figure 12. TPS53313 Operation Modes in Light and Heavy Load Conditions
7.4.3 Forced Continuous Conduction Mode
When choosing FCCM, the TPS53313 is operating in continuous conduction mode in both light and heavy load
condition. In this mode, the switching frequency remains constant over the entire load range which is suitable for
applications need tight control of switching frequency at a cost of lower efficiency at light load.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
13
TPS53313
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS53313 device is a high-efficiency synchronous-buck converter. The device suits low output voltage
point-of-load applications with 6-A or lower output current in computing and similar digital consumer applications.
8.2 Typical Application
This design example describes a voltage-mode, 6-A synchronous buck converter with integrated MOSFETs. The
device provides a fixed 1.2-V output at up to 6-A from a 12-V input bus.
OPEN= ENABLE
2
1
J1
R1
22.0k
R2
51.0k
J2
C10
C11
C12
C13
C14
2
22uF
22uF
22uF
22uF
22uF
VOUT
2
1
EN
PG
4
RT/SYNC
PGND
AGND
PGND
BP3
14
13
1
MODE/SS
PGND
J5
GND
1.2V/6A
COMP
TPS53313RGE
PGND
SW
12
U1
PGND
R5
10.0k
C5
10nF
24
560pF
23
600kHz
22
80.6k
R3
21
20
19
BP7
11
10.0k
300
C8
C9
1.0uF
1.0uF
18
9
10
R8
C7
FB
VBST
GND
R4
5.60k
220pF
PGND
17
8
C6
PWPD
SW
7
VIN
6
VIN
25
3
R7
GND
16
22uF
5
C4
22uF
VIN
C3
22uF
SW
C2
1.0uF
15
C1
2
VIN
1
SW
VIN
8V - 14V
SKIP 6ms SS
R14
L1
1.0uH
R12
82.0k
GND
0
9A OC
C15 0.1uF
C16
R16
10nF
10.0
R17
TP11
CHB
1.00
C18
1.0nF
GND
TP12
CHA
GND
TP13
CONTROL LOOP
INJECTION & MEASURING
R18
0
Copyright © 2016, Texas Instruments Incorporated
Figure 13. Typical Application Schematic
14
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
TPS53313
www.ti.com
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
Typical Application (continued)
8.2.1 Design Requirements
This design example illustrates the design process and component selection for a single-output synchronous
buck converter using the TPS53313. The design example schematic of a is shown in Figure 13. The specification
of the converter is listed in Table 3.
Table 3. Design Example Converter Specifications
PARAMETER
VIN
Input voltage
VOUT
Output voltage
VRIPPLE
Output ripple
IOUT
Output current
fSW
Switching frequency
TEST CONDITION
MIN
TYP
MAX
UNIT
10.8
12
13.2
V
1.2
IOUT = 6 A
V
1% of VOUT
V
6
600
A
kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Output Inductor Selection
The inductance value should be determined to give the ripple current of approximately 20% to 40% of maximum
output current. The inductor ripple current is determined by Equation 1.
(V - VOUT )´ VOUT
1
IL(ripple) =
´ IN
L ´ fSW
VIN
(1)
The inductor also requires a low DCR to achieve good efficiency, as well as enough room above peak inductor
current before saturation.
8.2.2.2 Output Capacitor Selection
The output capacitor selection is determined by output ripple and transient requirement. When operating in CCM,
the output ripple has three components:
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL)
(2)
VRIPPLE(C) =
IL(ripple)
8 ´ COUT ´ fSW
(3)
VRIPPLE(ESR) = IL(ripple) ´ ESR
VRIPPLE(ESL)
(4)
V ´ ESL
= IN
L
(5)
When ceramic output capacitor is chosen, the ESL component is usually negligible. In the case when multiple
output capacitors are used, the total ESR and ESL should be the equivalent of the all output capacitors in
parallel.
When operating in DCM, the output ripple is dominated by the component determined by capacitance. It also
varies with load current and can be expressed as shown in Equation 6.
2
VRIPPLE(DCM) =
(a ´ IL(ripple) - IOUT )
2 ´ fSW ´ COUT ´ IL(ripple)
where
•
a=
α is the DCM on-time coefficient and can be expressed as shown in Equation 7.
(6)
tON(DCM)
tON(CCM)
(7)
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
15
TPS53313
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
www.ti.com
IL
VOUT
a x IL(ripple)
VRIPPLE
IOUT
T1
axT
UDG-11253
Figure 14. DCM Output Voltage Ripple
8.2.2.3 Input Capacitor Selection
The selection of input capacitor should be determined by the ripple current requirement. The ripple current
generated by the converter needs to be absorbed by the input capacitors as well as the input source. The RMS
ripple current from the converter can be expressed as shown in Equation 8.
IIN(ripple) = IOUT ´ D ´ (1 - D )
where
•
D is the duty cycle and can be expressed as shown in Equation 9.
(8)
V
D = OUT
VIN
(9)
To minimize the ripple current drawn from the input source, sufficient input decoupling capacitors should be
placed close to the device. The ceramic capacitor is recommended due to its low ESR and low ESL. The input
voltage ripple can be calculated as below when the total input capacitance is determined by Equation 10.
I
´D
VIN(ripple) = OUT
fSW ´ CIN
(10)
8.2.2.4 Output Voltage Setting Resistors Selection
The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Equation 11. R1 is
connected between VFB pin and the output, and R2 is connected between the VFB pin and GND.
Recommended value for R1 is from 1k to 5k. Determine R2 using Equation 11.
0.6
R2 =
´ R1
VOUT - 0.6
(11)
8.2.2.5 Compensation Design
The TPS53313 employs voltage mode control. To effectively compensate the power stage and ensure fast
transient response, Type III compensation is typically used.
1 + s ´ COUT ´ ESR
GCO = 4 ´
æ
ö
L
+ COUT ´ (ESR + DCR) ÷ + s2 ´ L ´ COUT
1+ s ´ ç
+
DCR
R
LOAD
è
ø
(12)
The output LC filter introduces a double pole which can be calculated as shown in Equation 13.
16
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
TPS53313
www.ti.com
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
fDP =
1
2 ´ p ´ L ´ COUT
(13)
The ESR zero of can be calculated as shown in Equation 14.
1
fESR =
2 ´ p ´ ESR ´ COUT
(14)
Figure 15 and Figure 16 shows the configuration of Type III compensation and typical pole and zero locations.
Equation 15 through Equation 17 describe the compensator transfer function and poles and zeros of the Type III
network.
(1 + s ´ C1´ (R1 + R3))(1 + s ´ R4 ´ C2 )
GEA =
C2 ´ C3 ö
(s ´ R1´ (C2 + C3))´ (1 + s ´ C1´ R3 )´ æç 1 + s ´ R4
C2
+ C3 ÷ø
è
(15)
1
fZ1 =
2 ´ p ´ R4 ´ C2
(16)
1
1
fZ2 =
@
2 ´ p ´ (R1 + R3 )´ C1 2 ´ p ´ R1´ C1
(17)
C3
C1
C2
R4
R3
COMP
VREF
R2
Gain (dB)
R1
+
UGD-11238
fZ1
fZ2
fP2
fP3
Frequency
UDG-11237
Figure 15. Type III Compensation
Network Schematic
Figure 16. Type III Compensation
Network Waveform
fP1 = 0
(18)
1
2 ´ p ´ R3 ´ C1
1
1
@
fP3 =
æ C2 ´ C3 ö 2 ´ p ´ R4 ´ C3
2 ´ p ´ R4 ´ ç
÷
è C2 + C3 ø
fP2 =
(19)
(20)
The two zeros can be placed near the double pole frequency to cancel the response from the double pole. One
pole can be used to cancel ESR zero, and the other non-zero pole can be placed at half switching frequency to
attenuate the high frequency noise and switching ripple. Suitable values can be selected to achieve a
compromise between high phase margin and fast response. A phase margin higher than 45° is required for
stable operation.
For DCM operation, a capacitor with a value between 100 pF and 220 pF is recommended for C3 when the
output capacitance is between 22 µF and 220 µF.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
17
TPS53313
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
www.ti.com
8.2.3 Application Curves
1.22
85
1.215
VOUT - Output Voltage - V
90
H - Efficiency - %
80
75
70
65
60
VIN = 12 V, fsw = 600 kHz, Skip Mode
55
VIN = 12 V, fsw = 1.00 MHz, Skip Mode
50
VIN = 12 V, fsw = 600 kHz, FCCM Mode
VIN = 12 V, fsw = 1.00 MHz, FCCM Mode
45
VIN = 12 V, fsw =600 kHz, Skip Mode
VIN = 12 V, fsw = 1.00 MHz, Skip Mode
1.21
VIN = 12 V, fsw = 600 kHz, FCCM Mode
1.205
VIN = 12 V, fsw = 1.00 MHz, FCCM Mode
1.2
1.195
1.19
1.185
40
1.18
0
1
2
3
4
5
6
0
1
2
3
4
ILOAD - Load Current - A
ILOAD - Load Current - A
Figure 17. Efficiency
Figure 18. Load Regulation
5
6
1.22
Skip Mode, fsw = 600 kHz, IOUT = 6 A
VOUT - Output Voltage - V
1.215
Skip Mode, fsw = 1.00 MHz, IOUT = 6 A
1.21
FCCM Mode, fsw = 600 kHz, IOUT = 6 A
FCCM Mode, fsw = 1.00 MHz, IOUT = 6 A
1.205
1.2
1.195
1.19
1.185
1.18
8
9
10
11
12
13
14
VIN - Input Voltage - V
12-V VIN, 1.2-V VOUT, fSW = 600 kHz
Figure 20. Output Load, 0-A to 3-A Transient
Under FCCM Mode
Figure 19. Line Regulation
12-V VIN, 1.2-V VOUT, fSW = 600 kHz
Figure 21. Output Load, 0-A to 3-A Transient
Under Skip Mode
18
12-V VIN, 1.2-V VOUT, 6-A IOUT, 1-ms SS
Figure 22. Start-Up Waveform
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
TPS53313
www.ti.com
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
12-V VIN, 1.2-V VOUT, 0-A IOUT, 1-ms SS
Figure 23. Pre-bias Start-Up Waveform
12-V VIN, 1.2-V VOUT, 0-A IOUT
Figure 24. Shut-Down Waveform
12-V VIN, 1.2-V VOUT, IOUT increases from 6 A to 7.8 A
Figure 25. Overcurrent Protection Waveform
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
19
TPS53313
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
www.ti.com
9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range from 4.5 V to 16 V. This input supply
must be well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise
performance, as is PCB layout and grounding scheme (see recommendations in Layout).
10 Layout
10.1 Layout Guidelines
Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout:
• Separate the power ground and analog ground planes. Connect them together at one location.
• Use 6 vias to connect the thermal pad to power ground.
• Place VIN, BP7 and BP3 decoupling capacitors as close to the device as possible.
• Use wide traces for VIN, PGND and SW. These nodes carry high-current and also serve as heat sinks.
• Place feedback and compensation components as close to the device as possible.
• Keep analog signals (FB, COMP) away from noisy signals (SW, VBST).
10.2 Layout Example
VOUT
SW
SW
SW
VBST
BP7
SW
SW
AGND Shape
BP3
PGND
AGND
PGND
RT/SYNC
PGND
MODE/SS
PGND
COMP
PGND
FB
PGND
VIN
VIN
VIN
VIN
PG
EN
PGND Shape
GND Via
VIN Shape
Trace under component
To BP7
Copyright © 2016, Texas Instruments Incorporated
Figure 26. TPS53313 Layout Example
20
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
TPS53313
www.ti.com
SLUSAS8A – DECEMBER 2011 – REVISED OCTOBER 2016
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
SmoothPWM, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53313
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS53313RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
53313
TPS53313RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
53313
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
