TPS5430-EP
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3-A WIDE-INPUT-RANGE STEP-DOWN SWIFT™ CONVERTER
FEATURES
1
• Wide Input Voltage Range: 5.5 V to 36 V
• Up to 3-A Continuous (4-A Peak) Output
Current
• High Efficiency up to 95% Enabled by 110-mΩ
Integrated MOSFET Switch
• Wide Output Voltage Range: Adjustable Down
to 1.22 V With 1.5% Initial Accuracy
• Internal Compensation Minimizes External
Parts Count
• Fixed 500-kHz Switching Frequency for Small
Filter Size
• Improved Line Regulation and Transient
Response by Input Voltage Feed Forward
• System Protected by Overcurrent Limiting,
Overvoltage Protection, and Thermal
Shutdown
• –55°C to 125°C Operating Junction
Temperature Range
• Available in Small Thermally Enhanced 8-Pin
SOIC PowerPAD™ Package
• For SWIFT™ Documentation, Application
Notes, and Design Software, See the TI
Website at www.ti.com/swift
2
DESCRIPTION
As a member of the SWIFT™ family of dc/dc
regulators, the TPS5430 is a high-output-current
pulse-width modulation (PWM) converter that
integrates a low-resistance high-side N-channel
MOSFET. Included on the substrate with the listed
features are a high-performance voltage error
amplifier that provides tight voltage regulation
accuracy under transient conditions, an undervoltage
lockout (UVLO) circuit to prevent start-up until the
input voltage reaches 5.5 V, an internally set
slow-start circuit to limit inrush currents, and a voltage
feed-forward circuit to improve the transient
response. Using the enable (ENA) pin, shutdown
supply current is reduced to 18 µA typically. Other
features include an active-high enable, overcurrent
limiting, overvoltage protection (OVP) and thermal
shutdown. To reduce design complexity and external
component count, the TPS5430 feedback loop is
internally compensated. The TPS5430 regulates a
wide variety of power sources including 24-V buses.
The TPS5430 device is available in a thermally
enhanced, easy-to-use 8-pin SOIC PowerPAD™
package. TI provides evaluation modules and the
SWIFT Designer software tool to aid in quickly
achieving high-performance power supply designs to
meet aggressive equipment development cycles.
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
APPLICATIONS
•
•
•
(1)
Industrial and Car Audio Power Supplies
Battery Chargers, High-Power LED Supplies
12-V/24-V Distributed Power Systems
Additional temperature ranges are available - contact factory
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD, SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS5430-EP
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Efficiency vs Output Current
Simplified Schematic
100
VIN
VOUT
PH
VIN
95
TPS5430
90
Efficiency − %
BOOT
NC
NC
ENA VSENSE
GND
85
80
75
70
VI = 12 V
VO = 5 V
fs = 500 kHz
o
TA = 25 C
65
60
55
50
0
0.5
1
1.5
2.5
3
2
IO − Output Current − A
3.5
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TJ
INPUT
VOLTAGE
OUTPUT
VOLTAGE
PACKAGE (2)
PART NUMBER
–55°C to 125°C
5.5 V to 36 V
Adjustable to 1.22 V
Thermally-enhanced SOIC (DDA)
TPS5430MDDAREP
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS (1)
(2)
over operating free-air temperature range (unless otherwise noted)
VIN
BOOT
PH (steady state)
VI
Input voltage range
ENA
–0.3 V to 40 V (3)
–0.3 V to 50 V
–0.6 V to 40 V (3)
–0.3 V to 7 V
BOOT-PH
10 V
VSENSE
–0.3 V to 3 V
PH (transient < 10 ns)
–1.2 V
IO
Source current
PH
Ilkg
Leakage current
PH
TJ
Operating virtual-junction temperature range
–55°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
(1)
(2)
(3)
2
Internally Limited
10 µA
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.
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DISSIPATION RATINGS (1)
(1)
(2)
(3)
(4)
(2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
8-pin DDA (2-layer board with solder) (3)
33°C/W
8-pin DDA (4-layer board with solder) (4)
26°C/W
Maximum power dissipation may be limited by overcurrent protection.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where
distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more
information.
Test board conditions:
a. 3 in × 3 in, two layers, thickness: 0.062 in
b. 2-oz copper traces located on the top and bottom of the PCB
c. Six thermal vias in the thermal pad area under the device package
Test board conditions:
a. 3 in × 3 in, four layers, thickness: 0.062 in
b. 2-oz copper traces located on the top and bottom of the PCB
c. 2-oz copper ground planes on the two internal layers
d. Six thermal vias in the thermal pad area under the device package
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
VIN
Input voltage
5.5
36
V
TJ
Operating junction temperature
–55
125
°C
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ELECTRICAL CHARACTERISTICS
TJ = –55°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3
4.4
mA
18
50
µA
Supply Voltage (VIN Pin)
IQ
Quiescent current
VSENSE = 2 V, Not switching,
PH pin open
Shutdown, ENA = 0 V
Undervoltage Lockout (UVLO)
Start threshold voltage, UVLO
5.3
V
Hysteresis voltage, UVLO
330
mV
Voltage Reference
Voltage reference accuracy
TJ = 25°C, IO = 0 A to 3 A
1.202
1.221
1.239
TJ = Full Temp Range, IO = 0 A to 3 A
1.196
1.221
1.245
400
500
600
kHz
150
200
ns
V
Oscillator
Internally set free-running frequency
Minimum controllable on time
Maximum duty cycle
87
89
%
Enable (ENA Pin)
Start threshold voltage, ENA
1.3
Stop threshold voltage, ENA
0.5
Hysteresis voltage, ENA
V
450
Internal slow-start time (0~100%)
5.4
V
mV
8
10
ms
Current Limit
Current limit
Current-limit hiccup time
4
5
8.5
A
13
16
21
ms
135
162
°C
14
°C
Thermal Shutdown
Thermal shutdown trip point
Thermal shutdown hysteresis
Output MOSFET
rDS(on)
4
High-side power MOSFET switch
VIN = 5.5 V
150
110
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230
mΩ
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PIN ASSIGNMENTS
DDA PACKAGE
(TOP VIEW)
BOOT
1
8
PH
NC
2
7
VIN
NC
3
6
GND
VSENSE
4
5
ENA
TERMINAL FUNCTIONS
TERMINAL
NAME
BOOT
NC
DESCRIPTION
NO.
1
2, 3
Boost capacitor for the high-side FET gate driver. Connect 0.01-µF low ESR capacitor from BOOT pin to PH pin.
Not connected internally
VSENSE
4
Feedback voltage for the regulator. Connect to output voltage divider.
ENA
5
On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.
GND
6
Ground. Connect to thermal pad.
VIN
7
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high-quality low-ESR ceramic
capacitor.
PH
8
Source of the high side power MOSFET. Connected to external inductor and diode.
PowerPAD
9
GND pin must be connected to the exposed pad for proper operation.
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TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
NON-SWITCHING QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
530
3.5
VI = 12 V
I Q−Quiescent Current −mA
f − Oscillator Frequency − kHz
520
510
500
490
480
3.25
3
2.75
470
460
−50
−25
0
25
50
75
100
2.5
−50
125
−25
50
75
100
Figure 2.
SHUTDOWN QUIESCENT CURRENT
vs
INPUT VOLTAGE
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
20
T J = 125°C
15
T J = 27°C
T J = –40°C
10
5
0
5
10
15
20
25
30
35
1.225
1.220
1.215
1.210
-50
40
-25
V I −Input V oltage −V
0
25
50
75
100
TJ - Junction Temperature - °C
Figure 3.
Figure 4.
ON RESISTANCE
vs
JUNCTION TEMPERATURE
INTERNAL SLOW START TIME
vs
JUNCTION TEMPERATURE
125
9
180
V I = 12 V
TSS − Internal Slow Start Time − ms
170
125
1.230
ENA = 0 V
VREF - Voltage Reference - V
−µ A
I SD −Shutdown Current
25
Figure 1.
25
160
150
140
130
120
110
r
DS(on) −On Resistance −mΩ
0
T J −Junction T emperature − °C
T − Junction Temperature − °C
100
8.5
8
7.5
90
80
−50
−25
0
25
50
75
100
T J −Junction Temperature − °C
125
7
−50
Figure 5.
6
−25
0
25
50
75
100
TJ − Junction Temperature − °C
125
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
MINIMUM CONTROLLABLE ON TIME
vs
JUNCTION TEMPERATURE
MINIMUM CONTROLLABLE DUTY RATIO
vs
JUNCTION TEMPERATURE
8
170
7.75
Minimum Duty Ratio - %
Minimum Controllable On Time − ns
180
160
150
140
7.50
7.25
130
120
−50
−25
0
25
50
75
100
TJ − Junction Temperature − °C
125
7
-50
Figure 7.
-25
50
0
25
75
100
TJ - Junction Temperature - °C
125
Figure 8.
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APPLICATION INFORMATION
FUNCTIONAL BLOCK DIAGRAM
VIN
VIN
1.221 V Bandgap
Reference
UVLO
VREF
SHDN
Slow Start
Boot
Regulator
BOOT
HICCUP
5 µA
ENABLE
ENA
SHDN
SHDN
VSENSE
Z1
Thermal
Protection
SHDN
NC
VIN
Ramp
Generator
NC
SHDN
VSENSE
HICCUP
PWM
Comparator
Overcurrent
Protection
Oscillator
OVP
Z2
Feed Forward
Gain = 25
SHDN
GND
POWERPAD
Error
Amplifier
SHDN
SHDN
Gate Drive
Control
112.5% VREF
Gate
Driver
SHDN
BOOT
PH
VOUT
DETAILED DESCRIPTION
Oscillator Frequency
The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500-kHz switching
frequency allows less output inductance for the same output ripple requirement resulting in a smaller output
inductor.
Voltage Reference
The voltage reference system produces a precision reference signal by scaling the output of a temperature
stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of
1.221 V at room temperature.
Enable (ENA) and Internal Slow Start
The ENA pin provides electrical on/off control of the regulator. Once ENA voltage exceeds the threshold voltage,
the regulator starts operation and the internal slow start begins to ramp. If ENA voltage is pulled below the
threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin to ground
or to any voltage less than 0.5 V disables the regulator and activates the shutdown mode. The quiescent current
of the TPS5430 in shutdown mode is typically 18 µA.
8
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ENA has an internal pullup current source, allowing the user to float the ENA pin. If an application requires
controlling ENA, use open-drain or open-collector output logic to interface with the pin. To limit the start-up inrush
current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its final value, linearly.
The internal slow start time is 8 ms typically.
Undervoltage Lockout (UVLO)
The TPS5430 incorporates a UVLO circuit to keep the device disabled when VIN (the input voltage) is below the
UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is
grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached,
the internal slow start is released and device start-up begins. The device operates until VIN falls below the UVLO
stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
Boost Capacitor (BOOT)
Connect a 0.01-µF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.
Output Feedback (VSENSE) and Internal Compensation
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, VSENSE voltage should be equal to the voltage
reference, 1.221 V.
The TPS5430 implements internal compensation to simplify the regulator design. Since the TPS5430 uses
voltage-mode control, a type-3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. See Internal Compensation Network in the Advanced
Information section for more details.
Voltage Feed Forward
The internal voltage feed forward provides a constant dc power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain, i.e,:
VIN
Feed Forward Gain +
Ramp
pk*pk
(1)
The typical feed-forward gain of the TPS5430 is 25.
Pulse-Width Modulation (PWM) Control
The regulator employs a fixed-frequency PWM control method. First, the feedback voltage (VSENSE pin voltage)
is compared to the constant voltage reference by the high-gain error amplifier and compensation network to
produce a error voltage. Then, the error voltage is compared to the ramp voltage by the PWM comparator. In this
way, the error voltage magnitude is converted to a pulse width, which is the duty cycle. Finally, the PWM output
is fed into the gate-drive circuit to control the on time of the high-side MOSFET.
Overcurrent Limiting
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The
drain-to-source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
ignores the overcurrent indicator for the leading-edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle current
limiting.
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Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen
when using cycle-by-cycle current limiting. A second mode of current limiting is used, i.e., hiccup mode
overcurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-side
MOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts under
control of the slow-start circuit.
Overvoltage Protection (OVP)
The TPS5430 has an OVP circuit to minimize voltage overshoot when recovering from output fault conditions.
The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of
112.5% × VREF. Once VSENSE voltage is higher than the threshold, the high-side MOSFET is forced off. When
VSENSE voltage drops lower than the threshold, the high-side MOSFET is enabled again.
Thermal Shutdown
The TPS5430 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow-start circuit automatically when the junction
temperature drops 14°C below the thermal shutdown trip point.
PCB Layout
Connect a low-ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN pin, and the ground pin. The best way to do this is to
extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass capacitor
as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7-µF ceramic with a
X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC, with an exposed area for connection
to the thermal pad. Use vias to connect this ground area to any internal ground planes. Use additional vias at the
ground side of the input and output filter capacitors as well. The GND pin should be tied to the PCB ground by
connecting it to the ground area under the device as shown in Figure 9.
The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is
the switching node, the inductor should be located very close to PH and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device to
minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as
shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by PH, LOUT, COUT, and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not
route this trace too close to the PH trace. Due to the size of the IC package and the device pin-out, the trace
may need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if a
trace under the output capacitor is not desired.
If using the grounding scheme shown in Figure 9, use a via connection to a different layer to route to the ENA
pin.
10
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PH
BOOT
CAPACITOR
OUTPUT
INDUCTOR
RESISTOR
DIVIDER
VOUT
BOOT
PH
NC
VIN
NC
GND
VSENSE
ENA
OUTPUT
FILTER
CAPACITOR
Route feedback
trace under output
filter capacitor or on
other layer
CATCH
DIODE
INPUT
INPUT
BYPASS
BULK
CAPACITOR FILTER
Vin
TOPSIDE GROUND AREA
VIA to Ground Plane
Signal VIA
Figure 9. Design Layout
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0.110
0.220
0.026
0.118
0.050
0.050
0.080
0.013 DIA 4 PL
0.040
0.098
All dimensions in inches
Figure 10. TPS5430 Land Pattern
Application Circuits
Figure 11 shows the schematic for a typical TPS5430 application. The TPS5430 can provide up to 3-A output
current at a nominal output voltage of 5 V. For proper thermal performance, the exposed thermal pad underneath
the device must be soldered down to the printed circuit board.
U1
TPS5430DDA
10.8 - 19.8 V
VIN
EN
C1
10 mF
7
5
2
3
6
VIN
C2
0.01 mF
L1
15 mH
5V
1
VOUT
BOOT
ENA
8
NC
PH
NC
4
D1
B340A
+
C3
220 mF
R1
10 kW
VSNS
GND
PwPd
9
R2
3.24 kW
Figure 11. Application Circuit, 12 V to 5 V
Design Procedure
The following design procedure can be used to select component values for the TPS5430. Alternately, the
SWIFT Designer Software may be used to generate a complete design. The SWIFT Designer Software uses an
iterative design procedure and accesses a comprehensive database of components when generating a design.
This section presents a simplified discussion of the design process.
12
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To begin the design process, a few parameters must be decided upon. The designer needs to know the
following:
• Input voltage range
• Output voltage
• Input ripple voltage
• Output ripple voltage
• Output current rating
• Operating frequency
Design Parameters
For this design example, use the following as the input parameters:
(1)
DESIGN PARAMETER (1)
EXAMPLE VALUE
Input voltage range
10.8 V to 19.8 V
Output voltage
5V
Input ripple voltage
300 mV
Output ripple voltage
30 mV
Output current rating
3A
Operating frequency
500 kHz
As an additional constraint, the design is set up to be small size and low component height.
Switching Frequency
The switching frequency for the TPS5430 is internally set to 500 kHz. It is not possible to adjust the switching
frequency.
Input Capacitors
The TPS5430 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
The recommended value for the decoupling capacitor, C1, is 10 µF. A high-quality ceramic type X5R or X7R is
required. For some applications, a smaller-value decoupling capacitor may be used, so long as the input voltage
and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,
including ripple.
This input ripple voltage can be approximated by Equation 2 :
DVIN +
I OUT(MAX)
C BULK
0.25
ƒsw
ǒ
) I OUT(MAX)
Ǔ
ESR MAX
(2)
Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CIN is the input capacitor value, and
ESRMAX is the maximum series resistance of the input capacitor.
The maximum RMS ripple current also needs to be checked. For worst-case conditions, this can be
approximated by Equation 3 :
I
OUT(MAX)
I
+
CIN
2
(3)
In this case, the input ripple voltage would be 156 mV and the RMS ripple current would be 1.5 A. The maximum
voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitor is
rated for 25 V and the ripple current capacity is greater than 3 A, providing ample margin. It is very important that
the maximum ratings for voltage and current are not exceeded under any circumstance.
Additionally some bulk capacitance may be needed, especially if the TPS5430 circuit is not located within
approximately 2 inches from the input voltage source. The value for this capacitor is not critical, but it also should
be rated to handle the maximum input voltage including ripple voltage and should filter the output so that input
ripple voltage is acceptable.
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Output Filter Components
Two components must be selected for the output filter, L1 and C2. Because the TPS5430 is an internally
compensated device, a limited range of filter component types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use Equation 4:
ǒ
V
V
* V
OUT(MAX)
IN(MAX)
OUT
L
+
MIN
V
K
I
F
IN(max)
IND
OUT
SW
Ǔ
(4)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
Three things need to be considered when determining the amount of ripple current in the inductor: the
peak-to-peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch
current and the amount of ripple current determines at what point the circuit becomes discontinuous. For designs
using the TPS5430, KIND of 0.2 to 0.3 yields good results. Low output ripple voltages can be obtained when
paired with the proper output capacitor, the peak switch current will be well below the current limit set point and
relatively low load currents can be sourced before discontinuous operation.
For this design example use KIND = 0.2 and the minimum inductor value is calculated to be 12.5 µH. The next
highest standard value is 15 µH, which is used in this design.
For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 5:
I
L(RMS)
+
Ǹ
I2
1
)
OUT(MAX) 12
ǒ
V
V
OUT
ǒVIN(MAX) * VOUTǓ
L
IN(MAX)
OUT
F
SW
0.8
Ǔ
2
(5)
and the peak inductor current can be determined with Equation 6:
V
I L(PK) + I
OUT(MAX)
)
OUT
1.6
ǒVIN(MAX) * VOUTǓ
V IN(MAX)
L
OUT
F
(6)
SW
For this design, the RMS inductor current is 3.003 A, and the peak inductor current is 3.31 A. The chosen
inductor is a Sumida CDRH104R-150 15 µH. It has a saturation current rating of 3.4 A and a RMS current rating
of 3.6 A, easily meeting these requirements. A lesser rated inductor could be used, however this device was
chosen because of its low profile component height. In general, inductor values for use with the TPS5430 are in
the range of 10 µH to 100 µH.
Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because, along with the inductor ripple current, it determines the amount of output ripple voltage. The actual
value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between
the desired closed-loop crossover frequency of the design and LC corner frequency of the output filter. Due to
the design of the internal compensation, it is desirable to keep the closed-loop crossover frequency in the range
3 kHz to 30 kHz, as this frequency range has adequate phase boost to allow for stable operation. For this design
example, it is assumed that the intended closed loop crossover frequency is between 2590 Hz and 24 kHz and
also below the ESR zero of the output capacitor. Under these conditions, the closed-loop crossover frequency is
related to the LC corner frequency as:
f CO +
14
f LC
2
85 VOUT
(7)
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And the desired output capacitor value for the output filter to:
1
C OUT +
3357 L OUT f CO V OUT
(8)
For a desired crossover of 18 kHz and a 15-µH inductor, the calculated value for the output capacitor is 220 µF.
The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESR is:
1
ESR MAX +
2p C OUT f CO
(9)
The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output
ripple voltage:
VPP (MAX) =
ESRMAX × VOUT ×
( VIN(MAX)
)
– VOUT
NC × VIN(MAX) × LOUT × FSW
(10)
Where:
ΔVPP is the desired peak-to-peak output ripple.
NC is the number of parallel output capacitors.
FSW is the switching frequency.
For this design example, a single 220-µF output capacitor is chosen for C3. The calculated RMS ripple current is
143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo
Poscap 10TPB220M, rated at 10 V with a maximum ESR of 40 mΩ and a ripple current rating of 3 A. An
additional small 0.1-µF ceramic bypass capacitor may also used, but is not included in this design.
The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero
when the ESR is at a minimum should not be too far above the internal compensation poles at 24 kHz and
54 kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus
one-half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 11:
ICOUT(RMS) + 1
Ǹ12
ȡ VOUT ǒVIN(MAX) * VOUTǓ ȣ
ȧVIN(MAX) LOUT FSW NCȧ
Ȣ
Ȥ
(11)
Where:
NC is the number of output capacitors in parallel.
FSW is the switching frequency.
Other capacitor types can be used with the TPS5430, depending on the needs of the application.
Output Voltage Setpoint
The output voltage of the TPS5430 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5 V using Equation 12:
R1 1.221
R2 +
V
* 1.221
OUT
(12)
For any TPS5430 design, start with an R1 value of 10 kΩ. R2 is then 3.24 kΩ.
Boot Capacitor
The boot capacitor should be 0.01 µF.
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Catch Diode
The TPS5430 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: reverse voltage must be higher than the maximum
voltage at the PH pin, which is VIN(MAX) + 0.5 V. Peak current must be greater than IOUT(MAX) plus one-half the
peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note
that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage
of 40 V, forward current of 3 A, and forward voltage drop of 0.5 V.
Additional Circuits
Figure 12 and Figure 13 show application circuits using wide input voltage ranges. The design parameters are
similar to those given for the design example, with a larger value output inductor and a lower closed loop
crossover frequency.
10-35 V
VIN
C1
4.7 mF
ENA
C4
4.7 mF
U1
TPS5430DDA
VIN
BOOT
ENA
NC
PH
NC
VSNS
GND
PwPd
C2
0.01 mF
L1
22 mH
5V
VOUT
D1
B340A
+
C3
220 mF
C3 = Sanyo POSCAP 10TP220M
R1
10 kW
R2
3.24 kW
Figure 12. 10-V to 35-V Input to 5-V Output Application Circuit
9-21 V
VIN
ENA
C1
U1
TPS5430DDA
VIN
BOOT
ENA
NC
PH
NC
VSNS
GND
PwPd
L1
C2
5V
VOUT
D1
B340A
+
C3
R1
C3 = Sanyo POSCAP 10TP220M
R2
Figure 13. 9-V to 21-V Input to 5-V Output Application Circuit
16
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Circuit Using Ceramic Output Filter Capacitors
Figure 14 shows an application circuit using all ceramic capacitors for the input and output filters, which
generates a 3.3-V output from a 10-V to 24-V input. The design procedure is similar to those given for the design
example, except for the selection of the output filter capacitor values and the design of the additional
compensation components required to stabilize the circuit.
U1
TPS5430DDA
VIN 10-24 V
VIN
C1
4.7 mF
EN
7
VIN
1
BOOT
5
ENA
2
8
PH
NC
3
4
NC
VSNS
6
GND PwPd
9
C2
0.01 mF
L1
15 mH
3.3 V
VOUT
D1
MRBS340
R1
10 kW
C7
0.1 mF
C4
150 pF
R3
549 W
C3
100 mF
R2
5.9 kW
C6
1500 pF
Figure 14. Ceramic Output Filter Capacitors Circuit
Output Filter Component Selection
Using Equation 11, the minimum inductor value is 12 µH. A value of 15 µH is chosen for this design.
When using ceramic output filter capacitors, the recommended LC resonant frequency should be no more than
7 kHz. Since the output inductor is already selected at 15 µH, this limits the minimum output capacitor value to:
1
CO (MIN) ≥
2
(2π × 7000) × LO
(13)
The minimum capacitor value is calculated to be 34 µF. For this circuit a larger value of capacitor yields better
transient response. A single 100-µF output capacitor is used for C3. It is important to note that the actual
capacitance of ceramic capacitors decreases with applied voltage. In this example, the output voltage is set to
3.3 V, minimizing this effect.
External Compensation Network
When using ceramic output capacitors, additional circuitry is required to stabilize the closed loop system. For this
circuit, the external components are R3, C4, C6, and C7. To determine the value of these components, first
calculate the LC resonant frequency of the output filter:
1
FLC =
2π √ LO × CO (EFF)
(14)
For this example, the effective resonant frequency is calculated as 4109 Hz.
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The network composed of R1, R2, R3, C5, C6, and C7 has two poles and two zeros that are used to tailor the
overall response of the feedback network to accommodate the use of the ceramic output capacitors. The pole
and zero locations are given by the following equations:
VO
Fp1 = 500000 ×
FLC
(15)
Fz1 = 0.7 × FLC
(16)
Fz2 = 2.5 x FLC
(17)
The final pole is located at a frequency too high to be of concern. The second zero, Fz2 as defined by
Equation 17 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower.
Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3-V output voltage as
calculated using Equation 12. For this design R1 = 10 kΩ and R2 = 5.90 kΩ. With Fp1 = 401 Hz, Fz1 = 2876 Hz,
and Fz2 = 10.3 kHz, the values of R3, C6, and C7 are determined using Equation 18, Equation 19, and
Equation 20:
1
C7 =
2π × Fp1 × (R1 || R2)
(18)
1
2π × Fz1 × C7
1
C6 =
2π × Fz2 × R1
R3 =
(19)
(20)
For this design, using the closest standard values, C7 is 0.1 µF, R3 is 549 Ω, and C6 is 1500 pF. C4 is added to
improve load regulation performance. It is effectively in parallel with C6 in the location of the second pole
frequency, so it should be small in relationship to C6. C4 should be less the 1/10 the value of C6. For this
example, 150 pF works well.
For additional information on external compensation of the TPS5430 or other wide-voltage-range SWIFT devices,
see Using TPS5410/20/30/31 With Aluminum/Ceramic Output Capacitors (literature number SLVA237).
ADVANCED INFORMATION
Output Voltage Limitations
Due to the internal design of the TPS5430, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
V OUTMAX + 0.87
ǒǒVINMIN * I OMAX
Ǔ
Ǔ ǒ
0.230 ) VD * I OMAX
Ǔ
RL * VD
(21)
Where
VINMIN is the minimum input voltage.
IOMAX is the maximum load current.
VD is the catch diode forward voltage.
RL is the output inductor series resistance.
This equation assumes maximum on resistance for the internal high-side FET.
18
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The lower limit is constrained by the minimum controllable on time, which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
V OUTMIN + 0.12
ǒǒVINMAX * I OMIN
Ǔ
Ǔ ǒ
0.110 ) VD * I OMIN
Ǔ
RL * VD
(22)
Where:
VINMAX is the maximum input voltage.
IOMIN is the minimum load current.
VD is the catch diode forward voltage.
RL is the output inductor series resistance.
This equation assumes nominal on resistance for the high-side FET and accounts for worst-case variation of
operating frequency set point. Any design operating near the operational limits of the device should be
carefully checked to ensure proper functionality.
Internal Compensation Network
The design equations given in the example circuit can be used to generate circuits using the TPS5430. These
designs are based on certain assumptions and will tend to always select output capacitors within a limited range
of ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of
the TPS5430. Equation 23 gives the nominal frequency response of the internal voltage-mode type-3
compensation network:
s
s
1)
1)
2p Fz1
2p Fz2
H(s) +
s
s
s
s
1)
1)
1)
2p Fp0
2p Fp1
2p Fp2
2p Fp3
(23)
ǒ
ǒ
Ǔ ǒ
Ǔ ǒ
Ǔ ǒ
Ǔ
Ǔ ǒ
Ǔ
Where:
Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 Hz
Fp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHz
Fp3 represents the non-ideal parasitics effect.
Using this information along with the desired output voltage, feed-forward gain, and output filter characteristics,
the closed-loop transfer function can be derived.
Thermal Calculations
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working at light loads in the discontinuous conduction mode.
Conduction loss: Pcon = IOUT2 × Rds(on) × VOUT/VIN
Switching loss: Psw = VIN × IOUT × 0.01
Quiescent current loss: Pq = VIN × 0.01
Total loss: Ptot = Pcon + Psw + Pq
Given TA ≥ Estimated junction temperature: TJ = TA + Rth × Ptot
Given TJMAX = 125°C ≥ Estimated maximum ambient temperature: TAMAX = TJMAX – Rth × Ptot
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PERFORMANCE GRAPHS
The performance graphs (Figure 15 through Figure 21) are applicable to the circuit in Figure 11, TA = 25°C (unless otherwise
specified).
0.3
100
VI = 10.8 V
95
0.2
VI = 12 V
Output Regulation - %
Efficiency - %
VI = 15 V
90
VI = 18 V
85
VI = 19.8 V
80
0.1
0
-0.1
-0.2
-0.3
75
0
0.5
1
1.5
2
2.5
IO - Output Current - A
3
3.5
Figure 15. Efficiency vs Output Current
0
0.5
1
2
1.5
2.5
3
IO - Output Current - A
Figure 16. Output Regulation vs Output Current
0.1
VIN = 100 mV/Div (AC Coupled)
0.08
0.06
Input Regulation - %
0.04
IO = 3 A
IO = 1.5 A
0.02
0
PH = 5 V/Div
-0.02
-0.04
IO = 0 A
-0.06
-0.08
-0.1
10.8
13.8
16.8
VI - Input Voltage - V
Figure 17. Input Regulation vs Input Voltage
20
t -Time - 500 ns/Div
19.8
Figure 18. Input Voltage Ripple and PH Node, IO = 3 A
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PERFORMANCE GRAPHS (continued)
The performance graphs (Figure 15 through Figure 21) are applicable to the circuit in Figure 11, TA = 25°C (unless otherwise
specified).
VOUT = 20 mV/Div (AC Coupled)
VOUT = 50 mV/Div (AC Coupled)
PH = 5 V/Div
IOUT = 1 A /Div
t - Time = 500 ns/Div
Figure 19. Output Voltage Ripple and PH Node, IO = 3 A
t - Time = 200 μs/Div
Figure 20. Transient Response, IO Step 0.75 A to 2.25 A
VIN = 5 V/Div
VOUT = 2 V/Div
t - Time = 2 ms/Div
Figure 21. Start-Up Waveform, VIN and VOUT
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS5430MDDAREP
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-55 to 125
5430EP
TPS5430MDDAREPG4
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-55 to 125
5430EP
V62/09625-01XE
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-55 to 125
5430EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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