TPS5450-EP
www.ti.com ....................................................................................................................................................................................................... SLVS935 – JULY 2009
5-A, WIDE INPUT RANGE, STEP-DOWN SWIFT™ CONVERTER
FEATURES
1
• Qualified for Automotive Applications
• Wide Input Voltage Range: 5.5 V to 36 V
• Up to 5-A Continuous (6-A Peak) Output
Current
• High Efficiency Greater than 90% Enabled by
110-mΩ Integrated MOSFET Switch
• Wide Output Voltage Range: Adjustable Down
to 1.22 V with 1.5% Initial Accuracy
• Internal Compensation Minimizes External
Parts Count
• Fixed 500-kHz Switching Frequency for Small
Filter Size
• 18-µA Shutdown Supply Current
• Improved Line Regulation and Transient
Response by Input Voltage Feed Forward
• System Protected by Overcurrent Limiting,
Overvoltage Protection, and Thermal
Shutdown
• Available in Small Thermally Enhanced 8-Pin
SOIC PowerPAD™ Package
• For SWIFT™ Documentation, Application
Reports and Design Software, See the TI
Website at www.ti.com/swift
2
APPLICATIONS
•
•
•
•
High-Density Point-of-Load Regulators
LCD Displays, Plasma Displays
Battery Chargers
12-V/24-V Distributed Power Systems
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
DESCRIPTION
As a member of the SWIFT™ family of DC/DC
regulators, the TPS5450 is a high-output-current
PWM converter that integrates a low-resistance
high-side N-channel MOSFET. Included on the
substrate with the listed features are a
high-performance voltage error amplifier that provides
tight voltage regulation accuracy under transient
conditions, an undervoltage-lockout circuit to prevent
start-up until the input voltage reaches 5.5 V, an
internally set slow-start circuit to limit inrush currents,
and a voltage feed-forward circuit to improve the
transient response. Using the ENA pin, shutdown
supply current is reduced to 18 µA typically. Other
features include an active-high enable, overcurrent
limiting, overvoltage protection, and thermal
shutdown. To reduce design complexity and external
component count, the TPS5450 feedback loop is
internally compensated.
The TPS5450 device is available in a thermally
enhanced, 8-pin SOIC PowerPAD™ package. TI
provides evaluation modules and software tools to aid
in achieving high-performance power supply designs
to meet aggressive equipment development cycles.
(1)
Additional temperature ranges are available - contact factory
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS5450-EP
SLVS935 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
Efficiency vs Output Current
Simplified Schematic
100
VIN
VIN
VOUT
PH
95
90
BOOT
Efficiency - %
NC
NC
ENA VSENSE
85
80
75
70
VI = 12 V,
VO = 5 V,
fs = 500 kHz,
TA = 25°C
65
GND
60
55
50
0
1
2
3
4
5
IO - Output Current - A
6
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–55°C to 125°C
(1)
(2)
Thermally Enhanced
SOIC – DDA
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TPS5450MDDAREP
5450EP
Reel of 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VIN
BOOT
PH (steady-state)
VI
Input voltage range
ENA
–0.3 V to 40 V (3)
–0.3 V to 50 V
–0.6 V to 40 V (3)
–0.3 V to 7 V
BOOT-PH
10 V
VSENSE
–0.3 V to 3 V
PH (transient < 10 ns)
–1.2 V
IO
Source current
PH
Ilkg
Leakage current
PH
TJ
Operating virtual-junction temperature range
–55°C to 150°C
Tstg
Storage temperature
–65°C to 150°C
(1)
(2)
(3)
2
Internally Limited
10 µA
Stresses beyond those listed under the absolute maximum ratings may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions beyond those indicated under the recommended
operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
TPS5450-EP
www.ti.com ....................................................................................................................................................................................................... SLVS935 – JULY 2009
DISSIPATION RATINGS (1)
(1)
(2)
(3)
(2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
8-Pin DDA (4-layer board with solder) (3)
30°C/W
Maximum power dissipation may be limited by overcurrent protection.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where
distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more
information.
Test board conditions:
a. 2 in x 1.85 in, 4 layers, 0.062-in (1,57-mm) thickness
b. 2-oz copper traces located on the top and bottom of the PCB
c. 2-oz copper ground planes on the two internal layers
d. Four thermal vias in the PowerPAD area under the device package
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
VI
Input voltage range
5.5
36
UNIT
V
TJ
Operating junction temperature
–55
125
°C
TYP
MAX
UNIT
3
4.4
mA
18
60
µA
ELECTRICAL CHARACTERISTICS
TJ = –55°C to 125°C, VIN = 5.5 V to 36 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SUPPLY VOLTAGE (VIN PIN)
IQ
Quiescent current
VSENSE = 2 V, Not switching, PH pin open
Shutdown, ENA = 0 V
UNDERVOLTAGE LOCK OUT (UVLO)
Start threshold voltage, UVLO
5.3
V
Hysteresis voltage, UVLO
330
mV
VOLTAGE REFERENCE
Voltage reference accuracy
TJ = 25°C
1.202
1.221
1.239
IO = 0 A – 5 A; TJ = Full Range
1.193
1.221
1.245
TJ = 25°C
400
500
600
TJ = Full Range
375
500
600
150
220
V
OSCILLATOR
Internally set free-running frequency
Minimum controllable on time
Maximum duty cycle
87
89
kHz
ns
%
ENABLE (ENA PIN)
Start threshold voltage, ENA
1.3
Stop threshold voltage, ENA
0.5
Hysteresis voltage, ENA
V
450
Internal slow-start time (0~100%)
V
5.4
8
TJ = 25°C
6.0
TJ = Full Range
4.4
TJ = 25°C
TJ = Full Range
mV
10
ms
7.5
9.0
A
7.5
11.7
13
16
20
13
16
22.5
135
162
°C
14
°C
CURRENT LIMIT
Current limit
Current limit hiccup time
ms
THERMAL SHUTDOWN
Thermal shutdown trip point
Thermal shutdown hysteresis
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
3
TPS5450-EP
SLVS935 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = –55°C to 125°C, VIN = 5.5 V to 36 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT MOSFET
rDS(on)
High-side power MOSFET switch
VIN = 5.5 V
150
110
mΩ
PIN ASSIGNMENTS
DDA PACKAGE
(TOP VIEW)
8
PH
7
VIN
3
6
GND
4
5
ENA
BOOT
1
NC
2
NC
VSENSE
PowerPAD
(Pin 9)
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
BOOT
1
NC
2, 3
DESCRIPTION
Boost capacitor for the high-side FET gate driver. Connect 0.01-µF low-ESR capacitor from BOOT pin to PH pin.
No internal connection
VSENSE
4
Feedback voltage for the regulator. Connect to output voltage divider.
ENA
5
On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.
GND
6
Ground. Connect to thermal pad.
VIN
7
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high-quality low-ESR ceramic
capacitor.
PH
8
Source of the high side power MOSFET. Connected to external inductor and diode.
PowerPAD
9
GND pin must be connected to the exposed pad for proper operation.
4
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
TPS5450-EP
www.ti.com ....................................................................................................................................................................................................... SLVS935 – JULY 2009
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
NON-SWITCHING QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
530
3.5
VI = 12 V
I Q−Quiescent Current −mA
f − Oscillator Frequency − kHz
520
510
500
490
480
3.25
3
2.75
470
460
−50
−25
0
25
50
75
100
2.5
−50
125
−25
50
75
100
Figure 2.
SHUTDOWN QUIESCENT CURRENT
vs
INPUT VOLTAGE
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
20
T J = 125°C
15
T J = 27°C
T J = –40°C
10
5
0
5
10
15
20
25
30
35
1.225
1.220
1.215
1.210
-50
40
-25
V I −Input V oltage −V
0
25
50
75
100
TJ - Junction Temperature - °C
Figure 3.
Figure 4.
ON RESISTANCE
vs
JUNCTION TEMPERATURE
INTERNAL SLOW START TIME
vs
JUNCTION TEMPERATURE
125
9
180
V I = 12 V
TSS − Internal Slow Start Time − ms
170
125
1.230
ENA = 0 V
VREF - Voltage Reference - V
−µ A
I SD −Shutdown Current
25
Figure 1.
25
160
150
140
130
120
110
r
DS(on) −On Resistance −mΩ
0
T J −Junction T emperature − °C
T − Junction Temperature − °C
100
8.5
8
7.5
90
80
−50
−25
0
25
50
75
100
T J −Junction Temperature − °C
125
7
−50
Figure 5.
−25
0
25
50
75
100
TJ − Junction Temperature − °C
125
Figure 6.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
5
TPS5450-EP
SLVS935 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
MINIMUM CONTROLLABLE ON TIME
vs
JUNCTION TEMPERATURE
MINIMUM CONTROLLABLE DUTY RATIO
vs
JUNCTION TEMPERATURE
8
170
7.75
Minimum Duty Ratio - %
Minimum Controllable On Time − ns
180
160
150
140
7.50
7.25
130
120
−50
−25
0
25
50
75
100
TJ − Junction Temperature − °C
125
7
-50
Figure 7.
6
-25
50
0
25
75
100
TJ - Junction Temperature - °C
125
Figure 8.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
TPS5450-EP
www.ti.com ....................................................................................................................................................................................................... SLVS935 – JULY 2009
APPLICATION INFORMATION
FUNCTIONAL BLOCK DIAGRAM
VIN
VIN
1.221 V Bandgap
Reference
UVLO
VREF
SHDN
Slow Start
Boot
Regulator
BOOT
HICCUP
5 µA
ENABLE
ENA
SHDN
SHDN
VSENSE
Z1
Thermal
Protection
SHDN
NC
VIN
Ramp
Generator
NC
SHDN
VSENSE
HICCUP
PWM
Comparator
Overcurrent
Protection
Oscillator
OVP
Z2
Feed Forward
Gain = 25
SHDN
GND
POWERPAD
Error
Amplifier
SHDN
SHDN
Gate Drive
Control
112.5% VREF
Gate
Driver
SHDN
BOOT
PH
VOUT
DETAILED DESCRIPTION
Oscillator Frequency
The internal free-running oscillator sets the PWM switching frequency at 500 kHz. The 500-kHz switching
frequency allows less output inductance for the same output ripple requirement resulting in a smaller output
inductor.
Voltage Reference
The voltage reference system produces a precision reference signal by scaling the output of a temperature
stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of
1.221 V at room temperature.
Enable (ENA) and Internal Slow Start
The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold
voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled
below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin
to ground or to any voltage less than 0.5 V disables the regulator and activates the shutdown mode. The
quiescent current of the TPS5450 in shutdown mode is 18 µA (typical).
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
7
TPS5450-EP
SLVS935 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application
requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit
the start-up inrush current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its
final value, linearly. The internal slow start time is 8 ms (typical).
Undervoltage Lockout (UVLO)
The TPS5450 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input
voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the
internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start
threshold voltage is reached, the internal slow start is released and device start-up begins. The device operates
until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
Boost Capacitor (BOOT)
Connect a 0.01-µF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.
Output Feedback (VSENSE) and Internal Compensation
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage
reference 1.221 V.
The TPS5450 implements internal compensation to simplify the regulator design. Because the TPS5450 uses
voltage-mode control, a type 3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. See the Internal Compensation Network section for more
details.
Voltage Feed Forward
The internal voltage feed forward provides a constant dc power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain:
VIN
Feed Forward Gain +
Ramp
pk*pk
(1)
The typical feed forward gain of TPS5450 is 25.
Pulse-Width-Modulation (PWM) Control
The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback
voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high-gain error amplifier and
compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by the
PWM comparator. In this way, the error-voltage magnitude is converted to a pulse width, which is the duty cycle.
Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET.
Overcurrent Limiting
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The
drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
ignores the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle current
limiting.
8
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
TPS5450-EP
www.ti.com ....................................................................................................................................................................................................... SLVS935 – JULY 2009
Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen
when using cycle-by-cycle current limiting. A second mode of current limiting is used, i.e. hiccup mode
overcurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-side
MOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts under
control of the slow start circuit.
Overvoltage Protection
The TPS5450 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from
output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage
and a threshold of 112.5% × VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side
MOSFET is forced off. When the VSENSE pin voltage drops lower than the threshold, the high-side MOSFET is
enabled again.
Thermal Shutdown
The TPS5450 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction
temperature drops 14°C below the thermal shutdown trip point.
PCB Layout
Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN pin, and the TPS5450 ground pin. The best way to do this
is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass
capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7 µF ceramic
with a X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC, with an exposed area for connection
to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the
ground side of the input and output filter capacitors as well. The GND pin should be tied to the PCB ground by
connecting it to the ground area under the device as shown below.
The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is
the switching node, the inductor should be located very close to the PH pin and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device to
minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as
shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings also may be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by the PH pin, Lout, Cout and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not
route this trace too close to the PH trace. Due to the size of the IC package and the device pin-out, the trace
may need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if a
trace under the output capacitor is not desired.
If using the grounding scheme shown in Figure 9, use a via connection to a different layer to route to the ENA
pin.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
9
TPS5450-EP
SLVS935 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
Feedback Trace
OUTPUT
INDUCTOR
BOOT
CAPACITOR
PH
BOOT
NC
INPUT
BYPASS
CAPACITOR
Vout
PH
Vin
VIN
EXPOSED
POWERPAD
AREA
RESISTOR
DIVIDER
NC
GND
VSENSE
ENA
OUTPUT
FILTER
CAPACITOR
CATCH
DIODE
TOPSIDE GROUND AREA
Route INPUT VOLTAGE
trace under the catch diode
and output capacitor
or on another layer
Signal VIA
Figure 9. Design Layout
Figure 10. TPS5450 Land Pattern
10
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
TPS5450-EP
www.ti.com ....................................................................................................................................................................................................... SLVS935 – JULY 2009
Application Circuits
Figure 11 shows the schematic for a typical TPS5450 application. The TPS5450 can provide up to 5-A output
current at a nominal output voltage of 5 V. For proper thermal performance, the exposed PowerPAD™
underneath the device must be soldered down to the printed-circuit board.
Figure 11. Application Circuit, 12-V to 5.0-V
Design Procedure
The following design procedure can be used to select component values for the TPS5450. Alternately, the
SWIFT™ Designer Software may be used to generate a complete design. The SWIFT™ Designer Software uses
an iterative design procedure and accesses a comprehensive database of components when generating a
design. This section presents a simplified discussion of the design process.
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
• Input voltage range
• Output voltage
• Input ripple voltage
• Output ripple voltage
• Output current rating
• Operating frequency
Design Parameters
For this design example, use the following as the input parameters:
(1)
DESIGN PARAMETER (1)
EXAMPLE VALUE
Input voltage range
10 V to 31 V
Output voltage
5V
Input ripple voltage
400 mV
Output ripple voltage
30 mV
Output current rating
5A
Operating frequency
500 kHz
As an additional constraint, the design is set up to be small size and low component height.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
11
TPS5450-EP
SLVS935 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
Switching Frequency
The switching frequency for the TPS5450 is internally set to 500 kHz. It is not possible to adjust the switching
frequency.
Input Capacitors
The TPS5450 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
The minimum recommended decoupling capacitance is 4.7 µF. A high-quality ceramic type X5R or X7R is
required. For some applications, a smaller value decoupling capacitor may be used, so long as the input voltage
and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,
including ripple.
This input ripple voltage can be approximated by Equation 2 :
DVIN +
I OUT(MAX)
C BULK
0.25
ƒsw
ǒ
) I OUT(MAX)
Ǔ
ESR MAX
(2)
Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CIN is the input capacitor value and
ESRMAX is the maximum series resistance of the input capacitor. For this design, the input capacitance consists
of two 4.7 µF capacitors, C1 and C4, in parallel. An additional high-frequency bypass capacitor, C5 is also used.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be
approximated by Equation 3 :
I
OUT(MAX)
I
+
CIN
2
(3)
In this case the input ripple voltage would be 281 mV and the RMS ripple current would be 2.5 A. The maximum
voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitor is
rated for 50 V, and the ripple current capacity is greater than 2.5 A each, providing ample margin. It is very
important that the maximum ratings for voltage and current are not exceeded under any circumstance.
Additionally some bulk capacitance may be needed, especially if the TPS5450 circuit is not located within about
2 inches from the input voltage source. The value for this capacitor is not critical but it also should be rated to
handle the maximum input voltage including ripple voltage and should filter the output so that input ripple voltage
is acceptable.
Output Filter Components
Two components need to be selected for the output filter, L1 and C2. Because the TPS5450 is an internally
compensated device, a limited range of filter component types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use Equation 4:
V
ǒ
Ǔ
V
* V
OUT(MAX)
IN(MAX)
OUT
L
+
MIN
V
K
I
F
IN(MAX)
IND
OUT
SW(MIN)
(4)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
Three things need to be considered when determining the amount of ripple current in the inductor: the
peak-to-peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch
current, and the amount of ripple current determines at what point the circuit becomes discontinuous. For
designs using the TPS5450, KIND of 0.2 to 0.3 yields good results. Low output ripple voltages can be obtained
when paired with the proper output capacitor, the peak switch current will be well below the current limit set point,
and relatively low load currents can be sourced before discontinuous operation.
For this design example use KIND = 0.2 and the minimum inductor value is calculated to be 10.4 µH. A higher
standard value is 15 µH, which is used in this design.
12
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
TPS5450-EP
www.ti.com ....................................................................................................................................................................................................... SLVS935 – JULY 2009
For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 5:
I
L(RMS)
+
Ǹ
1
I2
)
OUT(MAX) 12
ǒ
V
V
OUT
ǒVIN(MAX) * VOUTǓ
L
IN(MAX)
OUT
F
Ǔ
2
SW(MIN)
(5)
and the peak inductor current can be determined with Equation 6:
V
I L(PK) + I
OUT(MAX)
)
1.6
OUT
ǒVIN(MAX) * VOUTǓ
V IN(MAX)
L
OUT
F
SW(MIN)
(6)
For this design, the RMS inductor current is 5.004 A, and the peak inductor current is 5.34 A. The chosen
inductor is a Sumida CDRH1127/LD-150 15µH. It has a minimum rated current of 5.65 A for both saturation and
RMS current. In general, inductor values for use with the TPS5450 are in the range of 10 µH to 100 µH.
Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because, along with the inductor ripple current, it determines the amount of output ripple voltage. The actual
value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between
the desired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to
the design of the internal compensation, it is desirable to keep the closed loop crossover frequency in the range
3 kHz to 30 kHz, as this frequency range has adequate phase boost to allow for stable operation. For this design
example, it is assumed that the intended closed loop crossover frequency is between 2590 Hz and 24 kHz and
also below the ESR zero of the output capacitor. Under these conditions the closed loop crossover frequency is
related to the LC corner frequency by:
f CO +
f LC
2
85 VOUT
(7)
And the desired output capacitor value for the output filter to:
1
C OUT +
3357 L OUT f CO V OUT
(8)
For a desired crossover of 12 kHz and a 15-µH inductor, the calculated value for the output capacitor is 330 µF.
The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESR
should be:
1
ESR MAX +
2p C OUT f CO
(9)
The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output
ripple voltage:
VPP (MAX) =
ESRMAX x VOUT x
( VIN(MAX)
- VOUT
)
NC x VIN(MAX) x LOUT x FSW
(10)
Where:
ΔVPP is the desired peak-to-peak output ripple.
NC is the number of parallel output capacitors.
FSW is the switching frequency.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
13
TPS5450-EP
SLVS935 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
For this design example, a single 330-µF output capacitor is chosen for C3. The calculated RMS ripple current is
143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo
Poscap 10TPB330M, rated at 10 V with a maximum ESR of 35 mΩ and a ripple current rating of 3 A. An
additional small 0.1-µF ceramic bypass capacitor, C6 is also used in this design.
The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero
when the ESR is at a minimum should not be too far above the internal compensation poles at 24 kHz and
54 kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one
half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 11:
ICOUT(RMS) + 1
Ǹ12
ȡ VOUT ǒVIN(MAX) * VOUTǓ ȣ
ȧVIN(MAX) LOUT FSW NCȧ
Ȣ
Ȥ
(11)
Where:
NC is the number of output capacitors in parallel.
FSW is the switching frequency.
Other capacitor types can be used with the TPS5450, depending on the needs of the application.
Output Voltage Setpoint
The output voltage of the TPS5450 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5 V using Equation 12:
R1 1.221
R2 +
V
* 1.221
OUT
(12)
For any TPS5450 design, start with an R1 value of 10 kΩ. For an output voltage closest to but at least 5 V, R2 is
3.16 kΩ.
Boot Capacitor
The boot capacitor should be 0.01 µF.
Catch Diode
The TPS5450 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the
peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note
that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B540A is chosen, with a reverse voltage
of 40 V, forward current of 5 A, and a forward voltage drop of 0.5 V.
ADVANCED INFORMATION
Output Voltage Limitations
Due to the internal design of the TPS5450, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
V OUTMAX + 0.87
14
ǒǒVINMIN * I OMAX
Ǔ
Ǔ ǒ
0.230 ) VD * I OMAX
Submit Documentation Feedback
Ǔ
RL * VD
(13)
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
TPS5450-EP
www.ti.com ....................................................................................................................................................................................................... SLVS935 – JULY 2009
Where
VINMIN = minimum input voltage
IOMAX = maximum load current
VD = catch diode forward voltage.
RL= output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time, which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
V OUTMIN + 0.12
ǒǒVINMAX * I OMIN
Ǔ
Ǔ ǒ
0.110 ) VD * I OMIN
Ǔ
RL * VD
(14)
Where
VINMAX = maximum input voltage
IOMIN = minimum load current
VD = catch diode forward voltage.
RL= output inductor series resistance.
This equation assumes nominal on resistance for the high-side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be
carefully checked to ensure proper functionality.
Internal Compensation Network
The design equations given in the example circuit can be used to generate circuits using the TPS5450. These
designs are based on certain assumptions and will tend to always select output capacitors within a limited range
of ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of
the TPS5450. Equation 15 gives the nominal frequency response of the internal voltage-mode type III
compensation network:
s
s
1)
1)
2p Fz1
2p Fz2
H(s) +
s
s
s
s
1)
1)
1)
2p Fp0
2p Fp1
2p Fp2
2p Fp3
(15)
ǒ
ǒ
Ǔ ǒ
Ǔ ǒ
Ǔ ǒ
Ǔ
Ǔ ǒ
Ǔ
Where
Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 Hz
Fp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHz
Fp3 represents the non-ideal parasitics effect.
Using this information along with the desired output voltage, feed forward gain and output filter characteristics,
the closed loop transfer function can be derived.
Thermal Calculations
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working at light loads in the discontinuous conduction mode.
Conduction Loss: Pcon = IOUT2 x RDS(on) x VOUT/VIN
Switching Loss: Psw = VIN x IOUT x 0.01
Quiescent Current Loss: Pq = VIN x 0.01
Total Loss: Ptot = Pcon + Psw + Pq
Given TA => Estimated Junction Temperature: TJ = TA + Rth x Ptot
Given TJMAX = 125°C => Estimated Maximum Ambient Temperature: TAMAX = TJMAX – Rth x Ptot
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
15
TPS5450-EP
SLVS935 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
PERFORMANCE GRAPHS
The performance graphs (Figure 12 through Figure 18) are applicable to the circuit in Figure 11. Ta = 25 °C.
unless otherwise specified.
0.3
100
0.2
VI = 12 V
95
Output Regulation - %
Efficiency - %
VI = 15 V
90
VI = 24 V
85
VI = 28 V
80
0.1
0
-0.1
-0.2
75
0
1
2
3
4
IO - Output Current - A
5
6
Figure 12. Efficiency vs. Output Current
-0.3
0
0.5
1
1.5
2 2.5
3 3.5
IO - Output Current - A
4
4.5
5
Figure 13. Output Regulation % vs. Output Current
0.3
VI = 200 mV/Div (AC Coupled)
Output Regulation - %
0.2
IO = 0 A
0.1
IO = 5 A
0
PH = 10 V/Div
IO = 2.5 A
-0.1
-0.2
-0.3
10
13
16
19
22
25
VI - Input Voltage - V
28
Figure 14. Output Regulation % vs. Input Voltage
16
t - Time - 1 ms/Div
31
Figure 15. Input Voltage Ripple and PH Node, Io = 5 A.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
TPS5450-EP
www.ti.com ....................................................................................................................................................................................................... SLVS935 – JULY 2009
VOUT = 50 mV/div (AC Coupled, 20 MHz BWL)
VOUT = 50 mV/div (AC Coupled, 20 MHz BWL)
VPH = 10 V/div
IOUT = 1 A/div
t - Time = 1 ms/div
t - Time = 100 ms/div
Figure 16. Output Voltage Ripple and PH Node, Io = 5 A
Figure 17. Transient Response, Io Step 1.25 to 3.75 A.
TJ - Junction Temperature - °C
125
100
75
50
25
0
0.5
1
1.5
2
2.5
IC Power Dissipation - W
3
3.5
Figure 18. TPS5450 Power Dissipation vs Junction
Temperature.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS5450MDDAREP
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
5450EP
V62/90644-01XE
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
5450EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
