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TPS54428
SLVSB42D – NOVEMBER 2011 – REVISED JANUARY 2016
TPS54428 4.5-V to 18-V Input, 4-A Synchronous Step-Down Converter With Eco-Mode™
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Enables Fast Transient
Response
Low Output Ripple and Allows Ceramic Output
Capacitor
Wide VIN Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.76 V to 7.0 V
Highly Efficient Integrated FETs Optimized
for Lower Duty Cycle Applications
– 70 mΩ (High Side) and 53 mΩ (Low Side)
High Efficiency, Less Than 10 μA at Shutdown
High Initial Bandgap Reference Accuracy
Adjustable Soft Start
Pre-Biased Soft Start
650-kHz Switching Frequency (fSW)
Cycle By Cycle Over Current Limit
Auto-Skip Eco-mode™ for High Efficiency at Light
Load
2 Applications
•
Wide Range of Applications for Low Voltage
System
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminal
– Digital Set Top Box (STB)
The TPS54428 enables system designers to
complete the suite of various end-equipment power
bus regulators with a cost effective, low component
count, low standby current solution.
The main control loop for the TPS54428 uses the DCAP2™ mode control that provides a fast transient
response
with
no
external
compensation
components.
The adaptive on-time control supports seamless
transition between PWM mode at higher load
conditions and Eco-mode™ operation at light loads.
Eco-mode™ allows the TPS54428 to maintain high
efficiency during lighter load conditions.
The TPS54428 also has a proprietary circuit that
enables the device to adopt to both low equivalent
series resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device operates from 4.5-V to 18-V
VIN input.
The output voltage can be programmed between
0.76 V and 7.0 V.
The device also features an adjustable soft start time.
The TPS54428 is available in 8-pin DDA package
and 10-pin DRC packages, and is designed to
operate over the ambient temperature range of –40°C
to 85°C.
Device Information(1)
PART NUMBER
3 Description
TPS54428
The TPS54428 is an adaptive on-time D-CAP2™
mode synchronous buck converter.
PACKAGE
BODY SIZE (NOM)
SO PowerPAD (8)
4.90 mm × 3.90 mm
VSON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1.05-V Load Transient Response
.
TPS54428DDA
Vout(50mV/div)
Iout(2A/div)
100us/div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54428
SLVSB42D – NOVEMBER 2011 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Examples................................................... 16
10.3 Thermal Considerations ........................................ 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2015) to Revision D
•
Updated Figure 20................................................................................................................................................................ 16
Changes from Revision B (March 2013) to Revision C
•
Page
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision A (January 2012) to Revision B
Page
•
Changed the Description text to include the DRC package ................................................................................................... 1
•
Added Figure 21 ................................................................................................................................................................... 16
Changes from Original (November 2011) to Revision A
•
2
Page
Deleted TA = –20ºC to 85ºC from ELEC CHARA table, CURRENT LIMIT section, Test Conditions statement.................... 5
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SLVSB42D – NOVEMBER 2011 – REVISED JANUARY 2016
5 Pin Configuration and Functions
DDA Package with Thermal Pad
8-Pin SO PowerPAD
Top View
1
VIN
EN
DRC Package with Thermal Pad
10-Pin VSON
Top View
8
10 VIN
EN 1
VFB 2
2
VFB
VBST
7
VREG5 3
TPS54428
3
VREG5
SS 4
SW
6
GND
5
Exposed
Thermal
Die PAD
on
Underside
PGND
GND 5
9 VIN
8 VBST
7 SW
6 SW
PowerPAD
4
SS
Pin Functions
PIN
NAME
DESCRIPTION
DDA
DRC
EN
1
1
Enable input control. Active high.
VFB
2
2
Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5
3
3
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND.
VREG5 is not active when EN is low.
SS
4
4
Soft-start control. An external capacitor should be connected to GND.
GND
5
GND
Ground pin. Power ground return for switching circuit. Connect sensitive SS and
VFB returns to GND at a single point.
5
SW
6
6, 7
VBST
7
8
VIN
8
9, 10
Exposed Thermal
Pad
Exposed Thermal
Pad
Back side
Ground pin. Connect sensitive SS and VFB returns to GND at a single point.
Switch node connection between high-side NFET and low-side NFET.
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor
between VBST and SW pins. An internal diode is connected between VREG5 and
VBST.
Input voltage supply pin.
Thermal pad of the package. Must be soldered to achieve appropriate dissipation.
Must be connected to GND.
Back side
Thermal pad of the package. PGND power ground return of internal low-side FET.
Must be soldered to achieve appropriate dissiapation.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
MIN
MAX
UNIT
VIN, EN
–0.3
20
V
VBST
–0.3
26
V
VBST (10 ns transient)
–0.3
28
V
VBST (vs SW)
–0.3
6.5
V
VFB, SS
–0.3
6.5
V
SW
–2
20
V
SW (10 ns transient)
–3
22
V
VREG5
–0.3
6.5
V
GND
–0.3
0.3
V
Voltage from GND to thermal pad, Vdiff
–0.2
0.2
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
Output voltage
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
VALUE
UNIT
±2000
V
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
VI
Supply input voltage range
Input voltage range
MIN
MAX
UNIT
4.5
18
V
VBST
–0.1
24
V
VBST (10 ns transient)
-0.1
27
V
VBST(vs SW)
–0.1
5.7
V
SS
–0.1
5.7
V
EN
–0.1
18
V
VFB
–0.1
5.5
V
SW
–1.8
18
V
–3
21
V
GND
–0.1
0.1
V
–0.1
5.7
V
0
10
mA
SW (10 ns transient)
VO
Output voltage range
VREG5
IO
Output Current range
IVREG5
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
4
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6.4 Thermal Information
TPS54428
THERMAL METRIC
(1)
DDA (SO
POWERPAD)
DRC (VSON)
8 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
42.1
43.2
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
50.9
53.8
°C/W
RθJB
Junction-to-board thermal resistance
31.8
18.2
°C/W
ψJT
Junction-to-top characterization parameter
5
0.6
°C/W
ψJB
Junction-to-board characterization parameter
13.5
18.3
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
7.1
4.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN
Operating - non-switching supply current
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V
950
1400
μA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
3.0
10
μA
LOGIC THRESHOLD
VENH
EN high-level input voltage
EN
VENL
EN low-level input voltage
EN
REN
EN pin resistance to GND
VEN = 12 V
1.6
225
V
450
0.6
V
900
kΩ
mV
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, IO = 10 mA,
Eco-mode™ operation
VFBTH
IVFB
VFB threshold voltage
VFB input current
771
TA = 25°C, VO = 1.05 V, continuous mode
operation
757
765
773
TA = –40°C to 85°C , VO = 1.05V, continuous
mode operation (1)
751
765
779
0
±0.1
μA
5.5
5.7
V
25
mV
100
mV
VFB = 0.8 V, TA = 25°C
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 6.0 V < VIN < 18 V,
0 < IVREG5 < 5 mA
VLN5
Line regulation
6 V < VIN < 18 V, IVREG5 = 5 mA
VLD5
Load regulation
0 mA < IVREG5 < 5 mA
IVREG5
Output current
VIN = 6 V, VREG5 = 4.0 V, TA = 25°C
60
mA
RDS(on)h
High side switch resistance, DDA
25°C, VBST - SW = 5.5 V
70
mΩ
RDS(on)h
High side switch resistance, DRC
25°C, VBST - SW = 5.5 V
74
mΩ
RDS(on)l
Low side switch resistance
25°C
53
mΩ
5.2
MOSFET
CURRENT LIMIT
Iocl
(1)
Current limit
L out = 1.5 µH
(1)
4.6
5.3
6.8
A
Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN
TSDN
Shutdown temperature (1)
Thermal shutdown threshold
170
Hysteresis (1)
°C
35
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
150
tOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.7 V
260
310
ns
7.8
ns
SOFT START
ISSC
SS charge current
VSS = 0 V
4.2
6.0
ISSD
SS discharge current
VSS = 1 V
0.1
0.2
Wake up VREG5 voltage
3.45
3.75
4.05
Hysteresis VREG5 voltage
0.19
0.32
0.45
μA
mA
UVLO
UVLO
UVLO threshold
V
6.6 Typical Characteristics
VIN = 12 V, TA = 25°C (unless otherwise noted)
20
1200
Ivccsdn - Shutdown Current - mA
ICC - Supply Current - mA
1000
800
600
400
200
0
-50
0
50
100
TJ - Junction Temperature - °C
15
10
5
0
-50
150
Figure 1. VIN Current vs Junction Temperature
0
50
100
TJJunction Temperature - °C
150
Figure 2. VIN Shutdown Current vs Junction Temperature
50
1.1
VI = 18 V
45
40
VO - Output Voltage - V
EN Input Current - mA
1.075
35
30
25
20
15
VI = 18 V
1.05
VI = 12 V
VI = 5 V
1.025
10
5
1
0
0
5
10
EN Input Voltage - V
15
20
1
2
3
4
IO - Output Current - A
Figure 3. EN Current vs EN Voltage
6
0
Figure 4. 1.05-V Output Voltage vs Output Current
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Typical Characteristics (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
1.08
100
90
VO - Output Voltage - V
1.07
VO = 1.8 V
Efficiency - %
80
IO = 10 mA
1.06
VO = 2.5 V
VO = 3.3 V
70
60
IO = 1 A
1.05
50
1.04
0
5
10
VI - Input Voltage - V
15
40
0
20
1
Figure 5. 1.05-V Output Voltage vs VIN Voltage
5
Figure 6. Efficiency vs Output Current
100
900
850
90
VO = 3.3 V
fsw - Switching Frequency - kHz
80
VO = 2.5 V
70
Efficiency - %
4
2
3
IO - Output Current - A
VO = 1.8 V
60
50
40
30
20
800
VO = 5 V
VO = 3.3 V
VO = 2.5 V V = 1.8 V
O
750
700
650
VO = 1.5 V
600
VO = 1.2 V
VO = 1.05 V
550
500
450
10
0
0.001
0.01
IO - Output Current - A
400
0.1
5
0
Figure 7. Light Load Efficiency vs Output Current
10
VI - Input Voltage - V
15
20
Figure 8. Switching Frequency vs Input Voltage
800
0.78
0.775
600
VO = 1.05 V
VO = 1.8 V
VO = 3.3 V
0.77
500
Vfb - Voltage - V
fsw - Switching Frequency - kHz
700
400
300
0.765
0.76
200
0.755
100
0
0
1
2
IO - Output Current - A
3
4
Figure 9. Switching Frequency vs Output Current
0.75
-50
0
50
100
TJ - Junction Temperature - °C
150
Figure 10. VFB Voltage vs Junction Temperature
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7 Detailed Description
7.1 Overview
The TPS54428 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
7.2 Functional Block Diagram
VIN
EN
Logic
EN
1
VIN
8
VREG5
7
Control Logic
VBST
Ref
SS
1 shot
SW
VFB
VREG 5
SGND
VO
6
2
XCON
VREG5
Ceramic
Capacitor
3
SS
5
SW
4
Softstart
PGND
GND
ZC
PGND
SS
SW
SGND
PGND
VIN
UVLO
VREG 5
UVLO
REF
TSD
Protection
Logic
Ref
7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS54428 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.
8
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Feature Description (continued)
7.3.2 PWM Frequency and Adaptive On-Time Control
TPS54428 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54428 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
7.3.3 Auto-Skip Eco-Mode™ Control
The TPS54428 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1.
1
(VIN - VOUT ) ´ VOUT
IOUT(LL) =
´
2 ´ L ´ fSW
VIN
(1)
7.4 Device Functional Modes
7.4.1 Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 6-µA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
6-uA.
C6(nF) ´ Vref ´ 1.1 C6(nF) ´ 0.765 ´ 1.1
Tss(ms) =
=
6
Iss(m A)
(2)
The TPS54428 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-bycycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal
mode operation.
7.4.2 Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS54428 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
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Device Functional Modes (continued)
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current is higher than the over-current threshold also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output voltage to fall. When the over current condition is removed, the output
voltage returns to the regulated value. This protection is non-latching.
7.4.3 UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS54428 is shut off. This protection is non-latching.
7.4.4 Thermal Shutdown
TPS54428 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 170°C),
the device is shut off. This is non-latch protection.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54428 is designed to provide up to 4-A output current from an input voltage source of 4.5 V to 17 V. The
output voltage range is from 0.76 V to 6 V.
8.2 Typical Application
4.5 to 18 V
Δ
1
TPS54428DDA
1.05 V 4 A
8200 pF
Figure 11. Schematic Diagram for This Design Example
8.2.1 Design Requirements
To
•
•
•
•
•
begin the design process, you must know a few application parameters:
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
Table 1. Performance Specifications Summary
SPECIFICATIONS
TEST CONDITIONS
Input voltage range (VIN)
MIN
4.5
Output voltage (VOUT)
Operating frequency
VIN = 12 V, IOUT = 2 A
Output current range
Line regulation
TYP
MAX
12
18
V
1.05
V
650
kHz
0
IO = 2.5 A
UNIT
4
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± 0.33%
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Typical Application (continued)
Table 1. Performance Specifications Summary (continued)
SPECIFICATIONS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
+0.9/–
0.1%
Load regulation
VIN = 12 V
Overcurrent limit
VIN = 12 V, L = 1.5 µH
Output ripple voltage
VIN = 12 V, IOUT = 4A
15
Maximum efficiency
VIN = 5 V, IOUT= 0.7 A
88%
4.6
5.3
6.8
A
mVPP
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
æ R1 ö
VOUT = 0.765 ´ ç 1+
÷
è R2 ø
(3)
8.2.2.2 Output Filter Selection
The output filter used with the TPS54428 is an LC circuit. This LC filter has double pole at:
1
FP =
2p LOUT ´ COUT
(4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54428. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 2.
Table 2. Recommended Component Values
C4 (pF) (1)
Output Voltage (V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
C8 + C9 (µF)
1
6.81
22.1
1.5
22 - 68
1.05
8.25
22.1
1.5
22 - 68
1.2
12.7
22.1
1.5
22 - 68
1.5
21.5
22.1
1.5
22 - 68
1.8
30.1
22.1
5 - 22
2.2
22 - 68
2.5
49.9
22.1
5 - 22
2.2
22 - 68
3.3
73.2
22.1
5 - 22
2.2
22 - 68
5
124
22.1
5 - 22
3.3
22 - 68
6.5
165
22.1
5 - 22
3.3
22 - 68
(1)
Optional
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
fSW.
12
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Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
VIN(MAX) - VO UT
VO UT
I lP-P =
´
VIN(MA X)
LO ´ f SW
(5)
IlPEA K = IO +
IL O(RMS) =
IlP-P
2
IO2 +
(6)
1
IlP -P 2
12
(7)
For this design example, the calculated peak current is 4.51 A and the calculated RMS current is 4.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54428 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 8 to
determine the required RMS current rating for the output capacitor.
VOx ´ (VIN - VO UT )
ICO(RMS) =
12 ´ VIN ´ L O ´ f SW
(8)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.286A and each output capacitor is rated for 4A.
8.2.2.3 Input Capacitor Selection
The TPS54428 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10µF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor from pin 8 to ground is optional to provide additional frequency filtering. The capacitor voltage rating
needs to be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
8.2.2.5 VREG5 Capacitor Selection
A 1-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor
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8.2.3 Application Curves
EN (10 V/div)
Vout (50 mV/div)
VREG5 (5 V/div)
Iout (2 A/div)
Vout (0.5 V/div)
100 ms/div
1 ms/div
Figure 12. 1.05-V Load Transient Response
VO = 1.05 V
Figure 13. Start Up Waveform
VIN (50 mV/div)
Vo = 1.5 V
Vo (10 mV/div)
SW (5 V/div)
SW (5 V/div)
500 ns/div
Figure 15. Voltage Ripple vs Ripple at Input (IO = 4 A)
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Figure 14. Voltage Ripple vs Ripple at Output (IO = 4 A)
60
50
40
30
50
40
30
20
20
VIN = 12 V
VIN = 5.0 V
10
0
60
0
500
1000
1500
2000
2500
Output Current (mA)
3000
3500
VIN = 12 V
VIN = 5.0 V
10
4000
0
1
10
100
Figure 16. Efficiency
14
1000
Output Current (mA)
G000
G000
Figure 17. Light-Load Efficiency
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1
0.5
0.8
0.4
0.6
0.3
Output Voltage, OUTP (%)
Output Voltage, OUTP (%)
www.ti.com
0.4
0.2
0
−0.2
−0.4
−0.6
0.1
0
−0.1
−0.2
IOUT = 0 A
IOUT = 1 A
IOUT = 2 A
IOUT = 4 A
−0.3
VIN = 12 V
VIN = 5.0 V
−0.8
−1
0.2
0
500
−0.4
1000
1500
2000
2500
Output Current (mA)
3000
3500
4000
−0.5
4.5
6
7.5
9
10.5
12
Input Voltage (V)
13.5
15
16.5
G000
Figure 18. Load Regulation, VIN = 5 V and VIN = 12 V
18
G000
Figure 19. Line Regulation
9 Power Supply Recommendations
The TPS54428 is designed to operate from input supply voltage in the range of 4.5 V to 18 V.
Buck converters require the input voltage to be higher than the output voltage for proper operation. The
maximum recommended operating duty cycle is 65%. Using that criteria, the minimum recommended input
voltage is VO / 0.65.
10 Layout
10.1 Layout Guidelines
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected PGND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
12. Providing sufficient vias for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
15. The TPS54428 can supply relatively large current up to 4A. So heat dissipation may be a concern. The topside area adjacent to the TPS54428 should be filled with ground as much as possible to dissipate heat.
16. The bottom-side area directly below the IC should a dedicated ground area. It should be directly connected
to the thermal pad using vias as shown. The ground area should be as large as practical. Additional internal
layers can be dedicated as ground planes and connected to vias as well.
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10.2 Layout Examples
Additional
Thermal
Vias
TO ENABLE
CONTROL
VIN INPUT
BYPASS
CAPACITOR
VIN INPUT
BYPASS
CAPACITOR
VIN
FEEDBACK
RESISTORS
EN
VIN
VFB
VBST
VREG5
SW
BOOST
CAPACITOR
VOUT
BIAS
CAP
Connection to
POWER GROUND
on internal or
bottom layer
SS
EXPOSED
POWERPAD
AREA
SOFT
START
CAP
OUTPUT
INDUCTOR
PGND
Additional
Thermal
Vias
ANALOG
GROUND
TRACE
OUTPUT
FILTER
CAPACITOR
POWER GROUND
Figure 20. TPS54428 Layout for the DDA Package
VIN
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
EN
VIN
HIGH FREQUENCY
BYPASS
VIN CAPACITOR
VFB
VIN
VREG5
BIAS
CAP
SLOW
START
CAP
ANALOG
GROUND
TRACE
VIN
INPUT
BYPASS
CAPACITOR
VBST
SS
SW
GND
SW
BOOST
CAPACITOR
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
EXPOSED
THERMAL PAD
AREA
Connection to
POWER GROUND
on internal or
bottom layer
VOUT
POWER GROUND
VIA to Ground Plane
Figure 21. PCB Layout for the DRC Package
16
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10.3 Thermal Considerations
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external
heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heartsink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, SLMA002 and Application Brief,
PowerPAD™ Made Easy, SLMA004.
The exposed thermal pad dimensions for the DDA package are shown in Figure 22.
8
5
Exposed Thermal Pad
2,40
1,65
1
3,10
2,65
4
Figure 22. Thermal Pad Dimensions
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11 Device and Documentation Support
11.1 Documentation Support
Technical Brief, PowerPAD™ Thermally Enhanced Package, SLMA002
Application Brief, PowerPAD™ Made Easy, SLMA004.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
D-CAP2, E2E are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54428DDA
ACTIVE SO PowerPAD
DDA
8
75
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
54428
TPS54428DDAR
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
54428
TPS54428DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
54428
TPS54428DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
54428
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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