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TPS56528
SLVSBV3B – APRIL 2013 – REVISED NOVEMBER 2016
TPS56528 4.5-V to 18-V Input, 5-A Synchronous Step-Down Converter
With Advanced Eco-Mode™
1 Features
3 Description
•
The TPS56528 device is an adaptive on-time
D-CAP2™ mode synchronous buck converter. The
TPS56528 enables system designers to complete the
suite of various end-equipment power bus regulators
with a cost-effective, low component count, low
standby current solution. The main control loop for
the TPS56528 uses the D-CAP2™ mode control that
provides a fast transient response with no external
compensation components. The adaptive on-time
control supports seamless transition between PWM
mode at higher load conditions and advanced EcoMode™ operation at light loads. Advanced EcoMode™ allows the TPS56528 to maintain high
efficiency during lighter load conditions. The
TPS56528 also has a proprietary circuit that enables
the device to adopt to both low equivalent series
resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device operates from 4.5-V to 18-V
VIN input. The output voltage can be programmed
between 0.6 V and 7 V. The device also features a
fixed 1-ms soft-start time and power good output. The
TPS56528 is available in the 8-pin SO PowerPAD™
package, and designed to operate from –40°C to
85°C.
1
•
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Enables Fast Transient
Response
Low Output Ripple and Allows Ceramic Output
Capacitor
Wide VIN Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.6 V to 7 V
Highly Efficient Integrated FETs Optimized
for Lower Duty Cycle Applications
–68 mΩ (High-Side) and 37 mΩ (Low-Side)
High Efficiency, Less Than 10 µA at Shutdown
High Initial Band-Gap Reference Accuracy
Prebiased Soft Start
650-kHz Switching Frequency (fSW)
Cycle-By-Cycle Overcurrent Limit
Advanced Auto-Skip Eco-Mode™ for High
Efficiency at Light Load
Power Good Output
Fixed Soft Start: 1 ms
2 Applications
•
Wide Range of Applications for Low Voltage
Systems
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminals
– Digital Set-Top Boxes (STB)
Simplified Schematic
TPS56528
Device Information(1)
PART NUMBER
TPS56528
PACKAGE
SO PowerPAD (8)
BODY SIZE (NOM)
4.89 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Transient Response
Vout( 50mV/div)
Iout( 2A/div)
Copyright © 2016, Texas Instruments Incorporated
100us/div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS56528
SLVSBV3B – APRIL 2013 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
10.3 Thermal Information .............................................. 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2013) to Revision B
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Original (April 2013) to Revision A
•
2
Page
Page
Changed the device From: Product Preview To: Production ................................................................................................. 1
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5 Pin Configuration and Functions
DDA Package
8-Pin SO PowerPAD
Top View
EN
1
VFB
2
8
VIN
7
VBST
PowerPAD
VREG5
3
6
SW
PG
4
5
GND
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
EN
I
Enable input control. EN is active high and must be pulled up to enable the device.
2
VFB
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
3
VREG5
O
5.5-V power supply output. A capacitor (0.47 µF typical) must be connected to GND. VREG5 is not
active when EN is low.
4
PG
O
Open-drain power good output.
5
GND
—
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to
GND at a single point.
6
SW
O
Switch node connection between high-side NFET and low-side NFET.
7
VBST
O
Supply input for the high-side FET gate drive circuit. Connect 0.1-µF capacitor between VBST and
SW pins. An internal diode is connected between VREG5 and VBST.
8
VIN
I
Input voltage supply pin.
—
PowerPAD
—
Thermal pad of the package. This pad must be soldered to achieve appropriate dissipation and
must be connected to GND.
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SLVSBV3B – APRIL 2013 – REVISED NOVEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
Output voltage
MIN
MAX
VIN and EN
–0.3
20
VBST
–0.3
26
VBST (10-ns-transient)
–0.3
28
VBST (vs SW)
–0.3
6.5
VFB and PG
–0.3
6.5
SW
–2
20
SW (10-ns-transient)
–3
22
VREG5
–0.3
6.5
GND
–0.3
0.3
Voltage from GND to thermal pad, Vdiff
–0.2
0.2
Operating junction temperature, TJ
–40
150
Storage temperature, Tstg
–55
150
(1)
UNIT
V
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
UNIT
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
VI
MIN
MAX
4.5
18
VBST
–0.1
24
VBST (10-ns-transient)
–0.1
27
VBST(vs SW)
–0.1
6
PG
–0.1
5.7
EN
–0.1
18
VFB
–0.1
5.5
SW
–1.8
18
Supply input voltage
Input voltage
SW (10-ns-transient)
GND
–3
21
–0.1
0.1
–0.1
5.7
UNIT
V
V
VO
Output voltage (VREG5)
IO
Output current (IVREG5)
0
5
mA
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
4
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V
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6.4 Thermal Information
TPS56528
THERMAL METRIC (1)
DDA (SO PowerPAD)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
44.4
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
51.6
°C/W
RθJB
Junction-to-board thermal resistance
27.8
°C/W
ψJT
Junction-to-top characterization parameter
8.7
°C/W
ψJB
Junction-to-board characterization parameter
27.7
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
5.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
I(VIN)
Operating non-switching supply current
VIN current, TA = 25°C, EN = 5 V,
V(FB) = 0.7 V
170
350
μA
I(VINSDN)
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
3.8
10
µA
LOGIC THRESHOLD
V(EN)
R(EN)
EN high-level input voltage
EN
EN low-level input voltage
EN
EN pin resistance to GND
VEN = 12 V
1.6
180
V
350
0.6
V
700
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, IO = 10 mA, advanced
Eco-Mode operation
V(FBTH)
I(VFB)
V(FB) threshold voltage
V(FB) input current
606
mV
TA = 25°C, VO = 1.05 V, continuous mode
operation
593
600
607
mV
TA = -40 to 85°C, VO = 1.05 V, continuous
mode operation (1)
588
600
612
mV
0
±0.15
µA
V(FB) = 0.7 V, TA = 25°C
SW DISCHARGE
I(DISCHG)
SW discharge current
EN = 0 V, SW = 1 V, TA = 25°C
1
1.5
5.5
mA
V(REG5) OUTPUT
V(VREG5)
VREG5 output voltage
TA = 25°C, 6.0 V < VIN < 18 V,
0 < I(VREG5) < 5 mA
5.2
I(VREG5)
Output current
VIN = 6 V, V(REG5) = 4 V, TA = 25°C
20
High-side switch resistance
25°C, V(BST) - SW = 5.5 V
68
mΩ
Low-side switch resistance
25°C
37
mΩ
5.7
V
mA
MOSFET
RDS(on)
CURRENT LIMIT
I(ocl)
Current limit
LOUT = 1.5 µH (1)
5.5
6.2
7.8
A
THERMAL SHUTDOWN
T(SDN)
Thermal shutdown threshold
Shutdown temperature
Hysteresis
(1)
165
(1)
°C
35
POWER GOOD
V(THPG)
PG threshold
IPG
PG sink current
(1)
VFB rising (good)
85%
VFB falling (Fault)
PG = 0.5 V
90%
95%
85%
2
4
mA
Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP threshold
OVP Detect (L>H)
125%
VUVP
Output UVP threshold
UVP detect (H>L)
65%
UVLO
UVLO
UVLO threshold
Wake-up VREG5 voltage
3.45
3.75
4.05
Hysteresis VREG5 voltage
0.13
0.32
0.48
V
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
ON-TIME TIMER CONTROL
tON
On-time
VIN = 12 V, VO = 1.05 V
150
tOFF(MIN)
Minimum off-time
TA = 25°C, VFB = 0.5 V
260
310
ns
ns
1
1.3
ms
SOFT START
tSS
Soft-start time
Internal soft-start time
0.7
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
tUVPDEL
Output UVP delay
to hiccup state
tUVPEN
Output UVP enable delay
Relative to soft-start time
6
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7
×1.7
µs
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SLVSBV3B – APRIL 2013 – REVISED NOVEMBER 2016
6.7 Typical Characteristics
VIN = 12 V and TA = 25°C (unless otherwise noted)
IVCCSDN - Shutdown Supply Current (uA)
400
ICC - Supply Current (uA)
350
300
250
200
150
100
VIN = 12 V
VO = 1.2 V
50
0
±50
0
50
100
20
15
10
5
EN = 0 V
0
±50
150
Tj Junction Temperature (ƒC)
0
50
100
150
TJ - Junction Temperature -ƒC
C004
Figure 1. VIN Supply Current vs Junction Temperature
C001
Figure 2. VIN Shutdown Current vs Junction Temperature
1.100
60
VIN = 18 V
VOUT - Output Voltage (V)
EN Input Current (uA)
50
40
30
20
1.075
1.050
1.025
V
VIN=5V
IN = 5 V
V
VIN=12V
IN = 12 V
V
VIN=18V
IN = 18 V
10
0
1.000
0
5
10
15
20
EN Input Voltage (V)
0.0
Figure 3. EN Current vs EN Voltage
fSW - Switching Frequency (kHz)
VOUT - Output Voltage (V)
1.075
1.050
1.025
IIOUT
10mA
10mA
OUT = =
IIOUT
1A1A
OUT = =
5
10
15
5.0
C010
VVo=1.05V
O = 1.05 V
VVo=1.2V
O = 1.2 V
VVo=1.5V
O = 1.5 V
VVo=1.8V
O = 1.8 V
VVo=2.5V
O = 2.5 V
VVo=3.3V
O = 3.3 V
VVo=5V
O= 5 V
850
800
750
700
650
600
550
500
450
IO = 1A
0.0
5.0
10.0
15.0
20.0
VIN - Input Voltage (V)
C007
Figure 5. 1.05-V Output Voltage vs Input Voltage
4.0
400
20
VIN - Input Voltage (V)
3.0
Figure 4. 1.05-V Output Voltage vs Output Current
900
0
2.0
IOUT - Output Current (A)
1.100
1.000
1.0
C014
C011
Figure 6. Switching Frequency vs Input Voltage
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Typical Characteristics (continued)
VIN = 12 V and TA = 25°C (unless otherwise noted)
0.615
700
0.610
600
500
VFB Voltage - V
fSW - Switching Frequency (kHz)
800
400
300
200
VVIN=5V
O = 1.05 V
VVIN=12V
O = 1.8 V
VVIN=18V
O = 3.3 V
100
0
0
1
2
3
4
0.605
0.600
0.595
0.590
5
IOUT - Output Current (A)
C012
Iout = 1 A
0.585
-50
0
50
100
TJ - Junction Temperature - ƒC
150
C015
Figure 8. VFB Voltage vs Junction Temperature
Figure 7. Switching Frequency vs Output Current
6.00
5.00
Output Current (A)
4.00
VO = 1.0 to 4.5V
3.00
VO = 5V
2.00
VO = 6V
1.00
VO = 7V
0.00
0
20
40
60
80
100
Ambient Temperature (°C)
Figure 9. Output Current vs Ambient Temperature
8
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7 Detailed Description
7.1 Overview
The TPS5652 is a 5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of lowESR output capacitors including ceramic and special polymer types. And also PG output can be used for
sequence operation.
7.2 Functional Block Diagram
EN
1
EN
Logic
EN
VIN
VIN
+
8
OV
-
+25%
VREG5
Control Logic
+
REF
7
VBST
+ PWM
SS
1 shot
VFB
6
-
2
VO
SW
XCON
ON
VREG5
Ceramic
Capacitor
VREG5
AGND
3
5
Softstart
+
ZC
-
SS
PGND
+
OCP
-
PG
4
+
REF
-
-10%
GND
SW
PGND
PGND
SW
OCL
VIN
OV
EN
VREG5
UVLO
UVLO
Protection
Logic
TSD
REF
REF
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7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS56528 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the
requirement for ESR-induced output ripple from D-CAP2™ mode control.
7.3.2 PWM Frequency and Adaptive On-Time Control
TPS56528 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS56528 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
7.3.3 Soft Start and Prebiased Soft Start
The TPS56528 has an internal 1-ms soft start. When the EN pin becomes high, internal soft-start function begins
ramping up the reference voltage to the PWM comparator.
The TPS56528 contains a unique circuit to prevent current from being pulled from the output during start-up if the
output is prebiased. When the soft start commands a voltage higher than the prebias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low-side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-bycycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the prebias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from prebiased start-up to normal
mode operation.
7.3.4 Power Good
The power good function is activated after soft start has finished. The power good function becomes active after
1.7 × soft-start time. When the output voltage becomes within –10% of the target value, internal comparators
detect power good state and the power good signal becomes high. The power good output, PG is an open-drain
output. If the feedback voltage goes under 15% of the target value, the power good signal becomes low.
7.3.5 Output Discharge Control
TPS56528 discharges the output through the SW pin when EN is low, or the controller is turned off by the
protection functions (UVP, UVLO and thermal shutdown). The internal regular low-side MOSFET is not turned on
during the output discharge operation to avoid the possibility of causing negative voltage at the output.
7.3.6 Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current, Iout. The TPS56528 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
10
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Feature Description (continued)
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of overcurrent protection. The peak current is the average
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current
minus one half of the peak-to-peak inductor current. Because the valley current is used to detect the overcurrent
threshold, the load current is higher than the overcurrent threshold. Also, when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This protection is non-latching. When the VFB voltage becomes lower than 65% of the target voltage,
the UVP comparator detects it. After 7 µs detecting the UVP voltage, device shut downs and restarts after hiccup
time.
When the overcurrent condition is removed, the output voltage returns to the regulated value.
7.3.7 UVLO Protection
Undervoltage lockout protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS56528 is shut off. This protection is non-latching.
7.3.8 Thermal Shutdown
TPS56528 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
7.4 Device Functional Modes
7.4.1 Advanced Auto-Skip Eco-Mode™ Control
The TPS56528 is designed with advanced auto-skip Eco-Mode™ to increase higher light load efficiency. As the
output current decreases from heavy load condition, the inductor current is also reduced. If the output current is
reduced enough, the inductor current ripple valley reaches the zero level, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying low-side MOSFET is turned off when
its zero inductor current is detected. As the load current further decreases the converter run into discontinuous
conduction mode. The on-time is kept approximately the same as is in continuous conduction mode. The off-time
increases as it takes more time to discharge the output capacitor to the level of the reference voltage with
smaller load current. The transition point to the light load operation IOUT(LL) current can be calculated in
Equation 1.
(VIN - VOUT )×VOUT
1
×
I OUT ( LL ) =
2 × L × fsw
VIN
(1)
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TPS56528
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS56528 is a 4.5-V to 18-V input step-down DC-DC converter with an output voltage adjustable from 0.6 V
to 7 V and capable of output currents up to 5 A.
8.2 Typical Application
U1
TPS56528DDA
Copyright © 2016, Texas Instruments Incorporated
Figure 10. Typical Application Schematic
8.2.1 Design Requirements
Table 1 lists the design parameters for this application example.
Table 1. Design Parameters
12
PARAMETER
VALUE
Input voltage range, VIN
4.5 to 18 V
Output voltage, VOUT
1.05 V
Output current, IOUT
5A
Switching Frequency
650 KHz
Output voltage ripple, VOUT ripple
< 20 mV
Input voltage ripple, VIN ripple
< 100 mV
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1%
tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at light loads, consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.
R1 ö
æ
VOUT = 0.60 ´ ç 1 +
÷
è R2 ø
(2)
8.2.2.2 Output Filter Selection
The output filter used with the TPS56528 is an LC circuit. This LC filter has double pole in Equation 3.
1
FP =
2p LOUT ´ COUT
(3)
At low frequencies, the overall loop gain is set by the output setpoint resistor divider network and the internal
gain of the TPS56528. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided by the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement, use the
values recommended in Table 2.
Table 2. Recommended Component Values
(1)
C4 (pF) (1)
OUTPUT
VOLTAGE
(V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
MIN
TYP
MAX
MIN
TYP
MAX
C7 + C8
(µF)
1
33.2
49.9
5
33
100
1
1.5
4.7
20 to 68
1.05
37.4
49.9
5
33
100
1
1.5
4.7
20 to 68
1.2
49.9
49.9
5
22
47
1
1.5
4.7
20 to 68
1.5
75.0
49.9
5
15
33
1
1.5
4.7
20 to 68
1.8
100
49.9
5
10
22
1
1.5
4.7
20 to 68
2.5
158
49.9
5
10
22
1.5
2.2
4.7
20 to 68
3.3
226
49.9
2
5
15
1.5
2.2
4.7
20 to 68
5
365
49.9
2
5
10
2.2
3.3
4.7
20 to 68
6.5
487
49.9
2
2
10
2.2
3.3
4.7
20 to 68
Optional
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed-forward
capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using Equation 4,
Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
fSW.
Ensure the chosen inductor is rated for the peak current of Equation 5 and the RMS current of Equation 6.
VIN(MAX) - VOUT
VOUT
I lP -P =
´
VIN(MAX)
LO ´ ¦ SW
I lPEAK
Il
= IO + P -P
2
(4)
(5)
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ILO(RMS) = IO2 +
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1
I lP -P2
12
(6)
For this design example, the calculated peak current is 5.51 A and the calculated RMS current is 5.01 A.
The inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating
of 11 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS56528 is intended for use
with ceramic or other low-ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
I
Co(RMS)
=
VOUT x (VIN - VOUT )
12 x VIN x LO x fSW
(7)
For this design, two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.284 A and each output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS56528 requires an input decoupling capacitor and a bulk capacitor is required depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 8 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating requires greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends using a ceramic capacitor.
8.2.2.5 VREG5 Capacitor Selection
A 0.47-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. TI
recommends using a ceramic capacitor.
8.2.3 Application Curves
EN( 10V/div)
Vout( 50mV/div)
VREG5( 5V/div)
Vout( 0.5V/div)
Iout( 2A/div)
PG( 5V/div)
100us/div
400us/div
Figure 11. 1.05-V, Load Transient Response
14
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Figure 12. Start-Up Waveform
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100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
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70
60
V
Vo=1.8V
O = 1.8 V
V
Vo
= 5.0
5 VV
O=
V
Vo=3.3V
O = 3.3 V
50
40
0.0
1.0
2.0
3.0
4.0
IOUT - Output Current (A)
70
60
5.0
40
0.001
0.01
IOUT - Output Current (A)
C008
Figure 13. Efficiency vs Output Current
Vo=1.05V
V
Vo=1.8V
O = 1.8 V
V
Vo
= 5.0
5 VV
O=
V
Vo=3.3V
O = 3.3 V
50
SW( 5V/div)
C009
Figure 14. Light Load Efficiency vs Output Current
Vo=1.05V
Vo( 10mV/div)
0.1
VIN( 50mV/div)
SW( 5V/div)
400ns/div
400ns/div
(IO = 5 A)
(IO = 5 A)
Figure 15. Voltage Ripple at Output
Figure 16. Voltage Ripple at Input
9 Power Supply Recommendations
The device is designed to operate from an input-voltage supply range between 4.5 V and 18 V. This input supply
must be well regulated. If the input supply is placed more than a few inches from the converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value
of 100 µF is a typical choice.
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10 Layout
10.1 Layout Guidelines
1. The TPS56528 can supply large load currents up to 5 A, so heat dissipation may be a concern. The top-side
area adjacent to the TPS56528 must be filled with ground as much as possible to dissipate heat.
2. The bottom side area directly below the IC must a dedicated ground area. It must be directed connected to
the thermal pad of the device using vias as shown. The ground area must be as large as practical. Additional
internal layers can be dedicated as ground planes and connected to vias as well.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections must be brought from the output to the
feedback pin of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN and PGND broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor must be placed near the device, and connected to PGND.
11. Output capacitor must be connected to a broad pattern of the PGND.
12. Voltage feedback loop must be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB pin must be tied to SGND.
14. Providing sufficient via is preferable for VIN, SW, and PGND connection.
15. PCB pattern for VIN, SW, and PGND must be as broad as possible.
16. VIN capacitor must be placed as near as possible to the device.
10.2 Layout Example
VIN
VIN
INPUT
BYPASS
CAPACITOR
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
TO ENABLE
CONTROL
FEEDBACK
RESISTORS
POWER
GOOD
PULL UP
BIAS
CAP
EN
VIN
VFB
VBST
VREG5
SW
PG
GND
TO POWER
GOOD
MONITOR
BOOST
CAPACITOR
OUTPUT
INDUCTOR
EXPOSED
THERMAL PAD
AREA
VOUT
OUTPUT
FILTER
CAPACITOR
ANALOG
GROUND
TRACE
POWER GROUND
VIA to Ground Plane
Figure 17. PCB Layout
16
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10.3 Thermal Information
This 8-pin SO PowerPAD package incorporates an exposed thermal pad that is designed to be directly to an
external heat sink. The thermal pad must be soldered directly to the printed-circuit board (PCB). After soldering,
the PCB can be used as a heat sink. In addition, through the use of thermal vias, the thermal pad can be
attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively,
can be attached to a special heat sink structure designed into the PCB. This design optimizes the heat transfer
from the integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see PowerPAD™ Thermally Enhanced Package (SLMA002) and PowerPAD™ Made Easy (SLMA004).
The exposed thermal pad dimensions for this package are shown in Figure 18.
Figure 18. Thermal Pad Dimensions (Top View)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package (SLMA002)
• PowerPAD™ Made Easy (SLMA004)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
D-CAP2, Eco-Mode, PowerPAD, E2E are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS56528DDA
ACTIVE SO PowerPAD
DDA
8
75
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
56528
TPS56528DDAR
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
56528
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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