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TPS54560-Q1
SLVSBZ0A – SEPTEMBER 2013 – REVISED DECEMBER 2014
TPS54560-Q1 4.5-V to 60-V Input, 5-A, Step-Down DC-DC Converter With Eco-Mode™
1 Features
3 Description
•
•
The TPS54560-Q1 is a 60-V, 5-A, step-down
regulator with an integrated high side MOSFET. The
device survives load dump pulses up to 65 V per ISO
7637. Current mode control provides simple external
compensation and flexible component selection. A
low-ripple, pulse-skip mode reduces the no load
supply current to 146 μA. Shutdown supply current is
reduced to 2 μA when the enable pin is pulled low.
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H1C
– Device CDM ESD Classification Level C3B
High Efficiency at Light Loads With PulseSkipping Eco-Mode™
92-mΩ High-Side MOSFET
146-μA Operating Quiescent Current and 2-µA
Shutdown Current
100-kHz to 2.5-MHz Adjustable Switching
Frequency
Synchronizes to External Clock
Low Dropout at Light Loads with Integrated BOOT
Recharge FET
Adjustable UVLO Voltage and Hysteresis
0.8-V 1% Internal Voltage Reference
8-Pin HSOIC with PowerPAD™ Package
–40°C to 150°C TJOperating Range
Supported by WEBENCH® Software Tool
•
•
•
A wide adjustable frequency range allows either
efficiency or external component size to be optimized.
Output current is limited cycle-by-cycle. Frequency
foldback and thermal shutdown protects internal and
external components during an overload condition.
The TPS54560-Q1 is available in an 8-pin thermally
enhanced HSOIC PowerPAD package.
Device Information(1)
PART NUMBER
PACKAGE
TPS54560-Q1
BODY SIZE (NOM)
SO PowerPAD (8)
3.90 mm x 4.89 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
Undervoltage lockout is internally set at 4.3 V but can
be increased using an external resistor divider at the
enable pin. The output voltage start-up ramp is
internally controlled to provide a controlled start-up
and eliminate overshoot.
Vehicle Accessories: GPS (See SLVA412),
Entertainment, ADAS, eCall
USB Dedicated Charging Ports and Battery
Chargers (See SLVA464)
Industrial Automation and Motor Control
12-V, 24-V and 48-V Industrial, Automotive and
Communications Power Systems
Simplified Schematic
VIN
Efficiency vs Load Current
100
VIN
BOOT
90
80
TPS54560-Q1
SW
COMP
70
VOUT
Efficiency (%)
EN
60
50
40
30
RT/CLK
FB
GND
20
VSeries1
IN = 12 V
VSeries2
IN = 36 V
VSeries4
IN = 60 V
10
0
0
0.5
1
1.5
2
2.5
3
3.5
IO - Output Current (A)
4
4.5
5
5.5
C024
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54560-Q1
SLVSBZ0A – SEPTEMBER 2013 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 21
8
Applications and Implementation ...................... 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 23
9 Power Supply Recommendations...................... 33
10 Layout................................................................... 34
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Power Dissipation .................................................
Safe Operating Area .............................................
34
34
34
35
11 Device and Documentation Support ................. 37
11.1
11.2
11.3
11.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
12 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
Changes from Original (September 2013) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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SLVSBZ0A – SEPTEMBER 2013 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
DDA Package
8-Pin HSOIC
Top View
8
SW
7
GND
3
6
COMP
4
5
FB
BOOT
1
VIN
2
EN
RT/CLK
Thermal
Pad
9
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BOOT
1
O
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high-side MOSFET, the output is switched off until the capacitor is
refreshed.
VIN
2
I
Input supply voltage with 4.5 V to 60 V operating range.
EN
3
I
Enable pin, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
RT/CLK
4
I
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper
threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is
disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal
amplifier is re-enabled and the operating mode returns to resistor frequency programming.
FB
5
I
Inverting input of the transconductance (gm) error amplifier.
COMP
6
O
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
GND
7
–
Ground
SW
8
I
The source of the internal high-side power MOSFET and switching node of the converter.
Thermal
Pad
9
–
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
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TPS54560-Q1
SLVSBZ0A – SEPTEMBER 2013 – REVISED DECEMBER 2014
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
–0.3
65
EN
–0.3
8.4
BOOT
Input voltage
73
FB
–0.3
COMP
–0.3
3
RT/CLK
–0.3
3.6
V
3
BOOT-SW
Output voltage
UNIT
8
SW
–0.6
65
–2
65
Operating junction temperature
–40
150
°C
Storage temperature, Tstg
–65
150
°C
SW, 10-ns Transient
(1)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Operating Input Voltage on (VIN pin)
4.5
60
UNIT
V
Operating junction temperature, TJ
–40
150
°C
6.4 Thermal Information
TPS54560-Q1
THERMAL METRIC (1) (2)
DDA
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
42.0
RθJC(top)
Junction-to-case (top) thermal resistance
45.8
RθJB
Junction-to-board thermal resistance
23.4
ψJT
Junction-to-top characterization parameter
5.9
ψJB
Junction-to-board characterization parameter
23.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.6
(1)
(2)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Test boards conditions:
(a) 3 inches x 3 inches, 2 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground plane, bottom layer
(d) 6 thermal vias (13mil) located under the device package
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6.5
SLVSBZ0A – SEPTEMBER 2013 – REVISED DECEMBER 2014
Electrical Characteristics
TJ = –40°C to 150°C, VIN = 4.5 to 60V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
60
V
4.3
4.48
V
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal undervoltage lockout threshold
4.5
Rising
4.1
Internal undervoltage lockout threshold
hysteresis
325
mV
Shutdown supply current
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 60 V
2.25
4.5
Operating: nonswitching supply current
FB = 0.9 V, TA = 25°C
146
175
1.2
1.3
μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling
–4.6
Enable threshold –50 mV
Hysteresis current
Enable to COMP active
1.1
Enable threshold +50 mV
–0.58
–1.2
-1.8
–2.2
–3.4
-4.5
VIN = 12 V, TA = 25°C
V
μA
μA
540
µs
INTERNAL SOFT-START TIME
Soft-Start Time
fSW = 500 kHz, 10% to 90%
2.1
ms
Soft-Start Time
fSW = 2.5 MHz, 10% to 90%
0.42
ms
VOLTAGE REFERENCE
Voltage reference
0.792
0.8
0.808
92
190
V
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
mΩ
ERROR AMPLIFIER
Input current
Error amplifier transconductance (gM)
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
Error amplifier transconductance (gM) during
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
soft-start
Error amplifier dc gain
VFB = 0.8 V
Min unity gain bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100-mV overdrive
COMP to SW current transconductance
50
nA
350
μMhos
77
μMhos
10,000
V/V
2500
kHz
±30
μA
17
A/V
CURRENT LIMIT
Current limit threshold
All VIN and temperatures, Open-Loop (1)
6.3
7.5
8.8
All temperatures, VIN = 12 V, Open-Loop (1)
6.3
7.5
8.3
7.1
7.5
7.9
VIN = 12 V, TA = 25°C, Open-Loop
(1)
Current limit threshold delay
A
60
ns
176
°C
12
°C
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode
fSW
Switching frequency
100
RT = 200 kΩ
Switching frequency range using CLK mode
450
160
Minimum CLK input pulse width
kHz
550
kHz
2300
kHz
15
RT/CLK high threshold
1.55
RT/CLK low threshold
(1)
2500
500
0.5
ns
2
V
1.2
V
RT/CLK falling edge to SW rising edge
delay
Measured at 500 kHz with RT resistor in series
55
ns
PLL lock in time
Measured at 500 kHz
78
μs
Open-loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
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SLVSBZ0A – SEPTEMBER 2013 – REVISED DECEMBER 2014
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6.6 Typical Characteristics
0.814
VFB - Voltage Referance ( V)
RDSON - On-State Resistance (
)
0.25
0.2
0.15
0.1
0.05
BOOT-SW = 3 V
0.809
0.804
0.799
0.794
0.789
BOOT-SW = 6 V
0
0.784
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (C)
8.5
8.5
High Side Switch Current (A)
9
7.5
7
6.5
50
75
100
125
150
C026
±40
C
Series1
25
C
Series2
150
C
Series4
8
7.5
7
6.5
6
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (C)
150
0
10
20
540
450
FSW - Switching Frequency (kHz)
500
520
510
500
490
480
470
460
450
40
50
60
C028
Figure 4. Switch Current Limit vs Input Voltage
550
530
30
VI - Input Voltage (V)
C027
Figure 3. Switch Current Limit vs Junction Temperature
FS - Switching Frequency (kHz)
25
Figure 2. Voltage Reference vs Junction Temperature
9
8
0
TJ - Junction Temperature (C)
6
400
350
300
250
200
150
100
50
0
±50
±25
0
25
50
75
100
TJ - Junction Temperature (C)
125
150
200
300
400
500
600
700
RT/CLK - Resistance (k
)
C029
Figure 5. Switching Frequency vs Junction Temperature
6
±25
C025
Figure 1. On Resistance vs Junction Temperature
High Side Switch Current (A)
±50
150
800
900
1000
C030
Figure 6. Switching Frequency vs RT/CLK Resistance Low
Frequency Range
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Typical Characteristics (continued)
500
2300
450
2100
1900
400
gm (µA/V)
FSW - Switching Frequency (kHz)
2500
1700
1500
1300
300
1100
900
250
700
500
200
0
50
100
150
±50
200
RT/CLK - Resistance (k
)
EN - Threshold (V)
100
gm (µA/V)
80
70
60
50
40
30
20
±25
0
25
50
75
100
125
TJ - Junction Temperature (C)
25
50
75
100
125
150
C032
Figure 8. EA Transconductance vs Junction Temperature
110
90
0
TJ - Junction Temperature (C)
120
±50
±25
C031
Figure 7. Switching Frequency vs RT/CLK Resistance High
Frequency Range
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.19
1.18
1.17
1.16
1.15
±50
150
±25
0
25
50
75
100
125
TJ - Junction Temperature (C)
C033
150
C034
Figure 9. EA Transconductance During Soft-Start vs
Junction Temperature
Figure 10. EN Pin Voltage vs Junction Temperature
±3.5
±0.5
±3.7
±0.7
±3.9
±0.9
±4.1
±1.1
±4.3
±1.3
IEN (µA)
IEN (uA)
350
±4.5
±4.7
±1.5
±1.7
±4.9
±1.9
±5.1
±2.1
±5.3
±2.3
±5.5
±2.5
±50
±25
0
25
50
75
100
TJ - Junction Temperature (C)
125
150
±50
Figure 11. EN Pin Current vs Junction Temperature
±25
0
25
50
75
100
TJ - Junction Temperature (C)
C035
125
150
C036
Figure 12. EN Pin Current vs Junction Temperature
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Typical Characteristics (continued)
100
% of Nominal Switching Frequency
±2.5
±2.7
IEN - Hysteresis (µA)
±2.9
±3.1
±3.3
±3.5
±3.7
±3.9
±4.1
±4.3
VSENSE
Rising
Series4
75
50
25
0
±4.5
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (C)
0.0
150
0.3
3
3
2.5
2.5
2
2
1.5
0.4
0.5
0.6
0.7
0.8
C038
Figure 14. Switching Frequency vs VSENSE
IVIN (µA)
IVIN (µA)
0.2
VSENSE (V)
1.5
1
1
0.5
0.5
0
0
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (C)
150
0
10
190
190
170
170
IVIN (µA)
210
130
40
50
60
C040
150
130
110
110
90
90
70
30
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
210
150
20
VIN - Input Voltage (V)
C039
Figure 15. Shutdown Supply Current vs Junction
Temperature
IVIN (µA)
0.1
C037
Figure 13. EN Pin Current Hysteresis vs Junction
Temperature
70
±50
±25
0
25
50
75
100
TJ - Junction Temperature (C)
125
150
0
10
20
30
40
VIN - Input Voltage (V)
C041
Figure 17. VIN Supply Current vs Junction Temperature
8
Series2
VSENSE
Falling
50
60
C042
Figure 18. VIN Supply Current vs Input Voltage
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Typical Characteristics (continued)
2.6
2.5
2.4
4.3
2.3
4.2
2.2
4.1
2.1
4.0
2.0
3.9
1.9
3.8
3.7
1.8
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (C)
±50
150
0
5.5
8
5.4
7
5.3
6
5.2
VIN (V)
5.6
75
100
125
150
C044
Start
Stop
5.1
4
5
3
4.9
2
4.8
1
4.7
0
4.6
Dropout
Voltage
Dropout
Voltage
2500
2300
2100
1900
1700
1500
1300
1100
900
700
500
300
100
0
0.05
0.1
0.15
0.2
0.25
0.3
Output Current (A)
C045
Figure 21. Soft-Start Time vs Switching Frequency
50
Figure 20. Input Voltage UVLO vs Junction Temperature
9
5
25
TJ - Junction Temperature (C)
10
Switching Frequency (kHz)
±25
C043
Figure 19. BOOT-SW UVLO vs Junction Temperature
Soft-Start Time (ms)
UVLO Start Switching
UVLO Stop Switching
4.4
VIN (V)
VI - BOOT-PH (V)
4.5
BOOT-PH UVLO Falling
BOOT-PH UVLO Rising
0.35
0.4
0.45
0.5
C046
Figure 22. 5 V Start and Stop Voltage (see Low Dropout
Operation and Bootstrap Voltage (BOOT))
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7 Detailed Description
7.1 Overview
The TPS54560-Q1 is a 60-V, 5-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET.
The device implements constant frequency, current mode control which reduces output capacitance and
simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows
either efficiency or size optimization when selecting the output filter components. The switching frequency is
adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked loop
(PLL) connected to the RT/CLK pin that will synchronize the power switch turn on to a falling edge of an external
clock signal.
The TPS54560-Q1 has a default input start-up voltage of approximately 4.3 V. The EN pin can be used to adjust
the input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up current
source enables operation when the EN pin is floating. The operating current is 146 μA under no load condition
(not switching). When the device is disabled, the supply current is 2 μA.
The integrated 92-mΩ, high-side MOSFET supports high efficiency power supply designs capable of delivering 5
amperes of continuous current to a load. The gate drive bias voltage for the integrated high-side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54560-Q1 reduces the external
component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a
UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a preset
threshold. An automatic BOOT capacitor recharge circuit allows the TPS54560-Q1 to operate at high duty cycles
approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the
application. The minimum output voltage is the internal 0.8-V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP
comparator is activated, the high-side MOSFET is turned off and remains off until the output voltage is less than
106% of the desired output voltage.
The TPS54560-Q1 includes an internal soft-start circuit that slows the output rise time during start-up to reduce
in-rush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the
overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal
regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent
fault conditions to help maintain control of the inductor current.
10
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7.2 Functional Block Diagram
EN
VIN
Shutdown
OV
Thermal
Shutdown
UVLO
Enable
Comparator
Logic
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
Error
Amplifier
Current
Sense
PWM
Comparator
FB
BOOT
Logic
Shutdown
6
Slope
Compensation
SW
COMP
Frequency
Foldback
Reference
DAC for
Soft- Start
Maximum
Clamp
GND
Oscillator
with PLL
POWERPAD
RT/ CLK
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54560-Q1 uses fixed frequency, peak current mode control with adjustable switching frequency. The
output voltage is compared through external resistors connected to the FB pin to an internal voltage reference by
an error amplifier. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier
output at the COMP pin controls the high-side power switch current. When the high-side MOSFET switch current
reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will
increase and decrease as the output current increases and decreases. The device implements current limiting by
clamping the COMP pin voltage to a maximum level. The pulse-skipping Eco-Mode is implemented with a
minimum voltage clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54560-Q1 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
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Feature Description (continued)
7.3.3 Pulse Skip Eco-Mode
The TPS54560-Q1 operates in a pulse-skipping Eco-Mode at light load currents to improve efficiency by
reducing switching and gate drive losses. If the output voltage is within regulation and the peak switch current at
the end of any switching cycle is below the pulse-skipping current threshold, the device enters Eco-Mode. The
pulse-skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of
600 mV.
When in Eco-Mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited. Since
the device is not switching, the output voltage begins to decay. The voltage control loop responds to the falling
output voltage by increasing the COMP pin voltage. The high-side MOSFET is enabled and switching resumes
when the error amplifier lifts COMP above the pulse-skipping threshold. The output voltage recovers to the
regulated value, and COMP eventually falls below the Eco-Mode pulse-skipping threshold at which time the
device again enters Eco-Mode. The internal PLL remains operational when in Eco-Mode. When operating at light
load currents in Eco-Mode, the switching transitions occur synchronously with the external clock signal.
During Eco-Mode operation, the TPS54560-Q1 senses and controls peak switch current, not the average load
current. Therefore the load current at which the device enters Eco-Mode is dependent on the output inductor
value. The circuit in Figure 36 enters Eco-Mode at about 25.3 mA output current. As the load current approaches
zero, the device enters a pulse-skip mode during which it draws only 146 μA input quiescent current.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54560-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT
capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or
higher is recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54560-Q1
will operate at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the voltage
from BOOT to SW drops below 2.1 V, the high-side MOSFET is turned off and an integrated low-side MOSFET
pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at high
output voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V.
Since the gate drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout
is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-side diode
voltage and the printed circuit board resistance.
The start and stop voltage for a typical 5-V output application is shown in Figure 22 where the VIN voltage is
plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output within
1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where
switching stops.
During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor is
being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time
required to recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cycle
PWM control.
At heavy loads, the minimum input voltage must be increased to insure a monotonic startup. Equation 1 can be
used to calculate the minimum input voltage for this condition.
VOUT(max) = D(max) x (VIN(min) - IOUT(max) x RDS(on) + VF) - VF + IOUT(max) x RL R
(1)
Where:
Dmax ≥ 0.9
IB2SW = 100 µA
VF = Forward Drop of the Catch Diode
TSW = 1 / Fsw
12
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Feature Description (continued)
VB2SW = VBOOT + VF
VBOOT = (1.41 x VIN - 0.554 - VF / TSW - 1.847 x 103 x IB2SW) / (1.41 + 1 / Tsw)
RDS(on) = 1 / (-0.3 x VB2SW2 + 3.577 x VB2SW - 4.246)
7.3.5 Error Amplifier
The TPS54560-Q1 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start
operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal softstart voltage.
The frequency compensation components (capacitor, series resistor and capacitor) are connected between the
error amplifier output COMP pin and GND pin.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8-V, ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB pin. It is recommended to use 1% tolerance or better divider resistors.
Select the low-side resistor RLS for the desired divider current and use Equation 2 to calculate RHS. To improve
efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator
will be more susceptible to noise and voltage errors from the FB input current may become noticeable.
æ Vout - 0.8V ö
RHS = RLS ´ ç
÷
0.8 V
è
ø
(2)
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54560-Q1 is enabled when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the
enable threshold of 1.2 V. The TPS54560-Q1 is disabled when the VIN pin voltage falls below 4 V or when the
EN pin voltage is below 1.2 V. The EN pin has an internal pull-up current source, I1, of 1.2 μA that enables
operation of the TPS54560-Q1 when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 23 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 μA of hysteresis current, IHYS, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3.4
μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use
Equation 3 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate RUVLO2 for
the desired VIN start voltage.
In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high
input voltages (that is, from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute
maximum voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using
the EN resistors, the EN pin is clamped internally with a 5.8 V zener diode that will sink up to 150 μA.
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Feature Description (continued)
VIN
TPS54560-Q1
i1
VIN
ihys
RUVLO1
RUVLO1
EN
EN
10 kW
Node
VEN
RUVLO2
RUVLO2
Figure 23. Adjustable Undervoltage Lockout
(UVLO)
5.8 V
Figure 24. Internal EN Clamp
- VSTOP
V
RUVLO1 = START
IHYS
(3)
VENA
RUVLO2 =
VSTART - VENA
+ I1
RUVLO1
(4)
7.3.8 Internal Soft-Start
The TPS54560-Q1 has an internal digital soft-start that ramps the reference voltage from zero volts to its final
value in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 5
1024
tSS (ms) =
fSW (kHz)
(5)
If the EN pin is pulled below the stop threshold of 1.2 V, switching stops and the internal soft-start resets. The
soft-start also resets in thermal shutdown.
7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
The switching frequency of the TPS54560-Q1 is adjustable over a wide range from 100 kHz to 2500 kHz by
placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must
have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 6 or Equation 7 or the curves in Figure 5 and Figure 6. To reduce the solution size one
would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency,
maximum input voltage and minimum controllable on time should be considered. The minimum controllable on
time is typically 135 ns which limits the maximum operating frequency in applications with high input to output
step down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. A more
detailed discussion of the maximum switching frequency is provided in the next section.
92417
RT (kW) =
f sw (kHz)0.991
(6)
f sw (kHz) =
14
101756
RT (kW)1.008
(7)
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Feature Description (continued)
7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
The TPS54560-Q1 implements peak current mode control in which the COMP pin voltage controls the peak
current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage
are compared each cycle. When the peak switch current intersects the COMP control voltage, the high-side
switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases
switch current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets
the peak switch current limit. The TPS54560-Q1 provides an accurate current limit threshold with a typical
current limit delay of 60 ns. With smaller inductor values, the delay will result in a higher peak inductor current.
The relationship between the inductor value and the peak inductor current is shown in Figure 25.
Inductor Current (A)
Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = VIN/L x tCLdelay
tCLdelay
tON
Figure 25. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the
TPS54560-Q1 implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB
pin voltage falls from 0.8 V to 0 V. The TPS54560-Q1 uses a digital frequency foldback to enable
synchronization to an external clock during normal start-up and fault conditions. During short-circuit events, the
inductor current can exceed the peak current limit because of the high input voltage and the minimum
controllable on time. When the output voltage is forced low by the shorted load, the inductor current decreases
slowly during the switch off time. The frequency foldback effectively increases the off time by increasing the
period of the switching cycle providing more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. Equation 9 calculates the maximum switching frequency at which
the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating frequency
should not exceed the calculated value.
Equation 8 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.
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Feature Description (continued)
æ I ´R + V
dc
OUT + Vd
´ç O
ç VIN - IO ´ RDS(on ) + Vd
è
ö
÷
÷
ø
(8)
fDIV æç ICL ´ Rdc + VOUT(sc ) + Vd
´
tON ç VIN - ICL ´ RDS(on ) + Vd
è
ö
÷
÷
ø
(9)
fSW (max skip ) =
fSW(shift) =
1
tON
IO
Output current
ICL
Current limit
Rdc
inductor resistance
VIN
maximum input voltage
VOUT
output voltage
VOUTSC
output voltage during short
Vd
diode voltage drop
RDS(on)
switch on resistance
tON
controllable on time
ƒDIV
frequency divide equals (1, 2, 4, or 8)
7.3.11 Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 26. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 1.7 V and
have a pulse-width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising
edge of the SW will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit
should be designed such that the default frequency set resistor is connected from the RT/CLK pin to ground
when the synchronization signal is off. When using a low impedance signal source, the frequency set resistor is
connected in parallel with an ac coupling capacitor to a termination resistor (e.g., 50 Ω) as shown in Figure 26.
The two resistors in series provide the default frequency setting resistance when the signal source is turned off.
The sum of the resistance should set the switching frequency close to the external CLK frequency. It is
recommended to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin.
The first time the RT/CLK is pulled above the PLL threshold the TPS54560-Q1 switches from the RT resistor
free-running frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and
the RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During
the transition from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz
and then increase or decrease to the resistor programmed frequency when the 0.5 V bias voltage is reapplied to
the RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 volts. The device
implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and
fault conditions. Figure 27, Figure 28 and Figure 29 show the device synchronized to an external system clock in
continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
SPACER
16
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Feature Description (continued)
TPS54560-Q1
TPS54560-Q1
RT/CLK
RT/CLK
PLL
PLL
RT
Hi-Z
Clock
Source
Clock
Source
RT
Figure 26. Synchronizing to a System Clock
SW
SW
EXT
EXT
IL
IL
Figure 27. Plot of Synchronizing in CCM
Figure 28. Plot of Synchronizing in DCM
SW
EXT
IL
Figure 29. Plot of Synchronizing in Eco-Mode
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Feature Description (continued)
7.3.12 Overvoltage Protection
The TPS54560-Q1 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients in designs with low output capacitance.
For example, when the power supply output is overloaded the error amplifier compares the actual output voltage
to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak
current limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier
output transitions to the normal operating level. In some applications, the power supply output voltage can
increase faster than the response of the error amplifier output resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB pin
voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, the high-side MOSFET is immediately disabled to minimize
output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the
internal voltage reference, the high-side MOSFET resumes normal operation.
7.3.13 Thermal Shutdown
The TPS54560-Q1 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the die temperature falls below 164°C, the device reinitiates the power-up sequence controlled
by the internal soft-start circuitry.
7.3.14 Small Signal Model for Loop Response
Figure 30 shows an equivalent model for the TPS54560-Q1 control loop which can be simulated to check the
frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA
of 350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Ro
and capacitor Co model the open-loop gain and frequency response of the amplifier. The 1-mV AC voltage
source between the nodes A and B effectively breaks the control loop for the frequency response measurements.
Plotting C/A provides the small signal response of the frequency compensation. Plotting A/B provides the small
signal response of the overall loop. The dynamic loop response can be evaluated by replacing RL with a current
source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is
only valid for continuous conduction mode (CCM) operation.
SW
VO
Power Stage
gmps 17 A/V
a
b
R1
RESR
RL
COMP
c
0.8 V
CO
R3
C2
RO
FB
COUT
gmea
350 mA/V
R2
C1
Figure 30. Small Signal Model for Loop Response
18
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Feature Description (continued)
7.3.15 Simple Small Signal Model for Peak Current Mode Control
Figure 31 describes a simple small signal model that can be used to design the frequency compensation. The
TPS54560-Q1 power stage can be approximated by a voltage-controlled current source (duty cycle modulator)
supplying current to the output capacitor and load resistor. The control to output transfer function is shown in
Equation 10 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in
switch current and the change in COMP pin voltage (node C in Figure 30) is the power stage transconductance,
gmPS. The gmPS for the TPS54560-Q1 is 17 A/V. The low-frequency gain of the power stage is the product of the
transconductance and the load resistance as shown in Equation 11.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 12). The combined effect is highlighted by the dashed line in the right half of
Figure 31. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same with varying load conditions. The type of output capacitor chosen determines
whether the ESR zero has a profound effect on the frequency compensation design. Using high-ESR aluminum
electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the
overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 13).
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 31. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
æ
s ö
ç1 +
÷
2p ´ fZ ø
VOUT
è
= Adc ´
VC
æ
s ö
ç1 +
÷
2p ´ fP ø
è
(10)
Adc = gmps ´ RL
(11)
1
fP =
COUT ´ RL ´ 2p
(12)
1
fZ =
COUT ´ RESR ´ 2p
(13)
7.3.16 Small Signal Model for Frequency Compensation
The TPS54560-Q1 uses a transconductance amplifier for the error amplifier and supports three of the commonlyused frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in
Figure 32. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low-ESR
output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or
tantalum capacitors. Equation 14 and Equation 15 relate the frequency response of the amplifier to the small
signal model in Figure 32. The open-loop gain and bandwidth are modeled using the RO and CO shown in
Figure 32. See the application section for a design example using a Type 2A network with a low ESR output
capacitor.
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Feature Description (continued)
Equation 14 through Equation 23 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power supply requirements.
VO
R1
FB
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C2
C1
R3
C2
C1
Figure 32. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 33. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol(V/V)
gmea
gmea
=
2p ´ BW (Hz)
Ro =
CO
(14)
(15)
æ
ö
s
ç1 +
÷
2
p
´
f
Z1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2p ´ fP1 ø è
2p ´ fP2 ø
è
A0 = gmea
A1 = gmea
20
R2
´ Ro ´
R1 + R2
R2
´ Ro| | R3 ´
R1 + R2
(16)
(17)
(18)
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Feature Description (continued)
P1 =
Z1 =
P2 =
1
2p ´ Ro ´ C1
(19)
1
2p ´ R3 ´ C1
(20)
1
2p ´ R3 | | RO ´ (C2 + CO )
type 2a
(21)
1
P2 =
type 2b
2p ´ R3 | | RO ´ CO
P2 =
2p ´ R O
(22)
1
type 1
´ (C2 + C O )
(23)
7.4 Device Functional Modes
7.4.1 Operation With VI = 4.5 V (Minimum VDD)
TI recommends operating the TPS54561-Q1 device with input voltages above 4.5 V. The typical V DD UVLO
threshold is 4.3 V, and the device may operate at input voltages down to the UVLO voltage. At input voltages
below the actual UVLO voltage, the device does not switch. If an external resistor divider pulls the EN pin up to V
DD or EN pin is floating, when V DD passes the UVLO threshold the device becomes active. Switching begins,
and the soft-start sequence initiates. The TPS54561-Q1 device starts at the soft-start time determined by the
external capacitance on the SS/TR pin
7.4.2 Operation With EN Control
The enable threshold voltage is 1.2 V typical. With EN held below that voltage, the device shuts down and
switching stops even if V DD is above its UVLO threshold. The IC quiescent current decreases in this state. After
increasing the EN pin voltage above the threshold while V DD is above its UVLO threshold, the device becomes
active. Switching resumes and the soft-start sequence begins. The TPS54561-Q1 device starts at the soft-start
time determined by the external capacitance at the SS/TR pin.
7.4.3 Alternative Power-Supply Topologies
7.4.3.1 Inverting Power Supply
One use of the TPS54561-Q1 is to convert a positive input voltage to a negative output voltage. Ideal
applications are amplifiers requiring a negative power supply. For a more-detailed example, see Create an
Inverting Power Supply From a Step-Down Regulator, application report SLVA317.
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Device Functional Modes (continued)
VIN
+
Cin
Cboot
Lo
BOOT
VIN
Cd
GND
SW
R1
+
GND
TPS54560-Q1
Co
R2
FB
VOUT
EN
COMP
Rcomp
RT/CLK
Czero
RT
Cpole
Figure 34. TPS54560-Q1 Inverting Power Supply from SLVA317 Application Note
7.4.3.2 Split-Rail Power Supply
Another use of the TPS54561-Q1 device is to convert a positive input voltage to a split-rail positive- and
negative-output voltage by using a coupled inductor. Ideal applications are amplifiers requiring a split-rail
positive- and negative-voltage power supply. For a more-detailed example, see Creating a Split-Rail Power
Supply With a Wide Input Voltage Buck Regulator, application report SLVA369.
VOPOS
+
VIN
Copos
+
Cin
Cboot
BOOT
VIN
GND
SW
Lo
Cd
R1
GND
+
Coneg
R2
TPS54560-Q1
VONEG
FB
EN
COMP
Rcomp
RT/CLK
RT
Czero
Cpole
Figure 35. TPS54560-Q1 Split Rail Power Supply based on the SLVA369 Application Note
22
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54560-Q1 device is a 60-V, 5-A, step-down regulator with an integrated high-side MOSFET. This device
typically converts a higher DC voltage to a lower DC voltage with a maximum available output current of 5 A.
Example applications are: 12-V, 24-V and 48-V industrial, automotive and communication power systems. The
WEBENCH software uses an iterative design procedure and accesses a comprehensive database of
components when generating a design.
8.2 Typical Application
L1
7.2uH
5V, 5A VOUT
C4 0.1uF
U1
TPS54560-Q1 (DDA)
7V to 60V
2
3
C10
2.2uF
C3
2.2uF
C1
2.2uF
C2
2.2uF
R1
442k
4
SW
BOOT
VIN
GND
EN
COMP
RT/CLK
PWRPD
1
VIN
FB
C6
C7
C9
47uF
47uF
47uF
R5
53.6k
7
6
5
FB
FB
R4
16.9k
9
R2
90.9k
8
D1
B560C
R3
243k
C8
R6
10.2k
47pF
C5
4700pF
Figure 36. 5 V Output TPS54560-Q1 Design Example
8.2.1 Design Requirements
A few parameters must be known in order to start the design process. These requirements are typically
determined at the system level. Calculations can be done with the aid of WEBENCH or the excel spreadsheet
(SLVC452) located on the product page. This example is designed to the following known parameters:
PARAMETER
UNIT
Output Voltage
5V
Transient Response 1.25 A to 3.75 A load step
ΔVOUT = 4 %
Maximum Output Current
5A
Input Voltage
12 V nom. 7 V to 60 V
Output Voltage Ripple
0.5% of VOUT
Start Input Voltage (rising VIN)
6.5 V
Stop Input Voltage (falling VIN)
5V
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8.2.2 Detailed Design Procedure
Use the following design procedure to select component values for the TPS54560-Q1 device.
8.2.2.1 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible since this produces the smallest solution size. High switching frequency allows for
lower value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage and the frequency foldback protection.
Equation 8 and Equation 9 should be used to calculate the upper limit of the switching frequency for the
regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values
results in pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54560-Q1. For this example, the output voltage is 5 V
and the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 708 kHz to avoid
pulse skipping from Equation 8. To ensure overcurrent runaway is not a concern during short circuits use
Equation 9 to determine the maximum switching frequency for frequency foldback protection. With a maximum
input voltage of 60 V, assuming a diode voltage of 0.7 V, inductor resistance of 11 mΩ, switch resistance of 92
mΩ, a current limit value of 6 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 855
kHz.
For this design, a lower switching frequency of 400 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 6 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 36. For 400 kHz operation, the closest
standard value resistor is 243 kΩ.
1
æ 5 A x 11 mW + 5 V + 0.7 V ö
´ ç
fSW(max skip) =
÷ = 708 kHz
135ns
è 60 V - 5 A x 92 mW + 0.7 V ø
(24)
8
æ 6 A x 11 mW + 0.1 V + 0.7 V ö
´ ç
÷ = 855 kHz
135 ns
è 60 V - 6 A x 92 mW + 0.7 V ø
92417
RT (kW) =
= 244 kW
400 (kHz)0.991
fSW(shift) =
(25)
(26)
8.2.2.2 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 27.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to
or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer,
however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple
current. This provides sufficienct ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the inductor value is calculated to be 7.6 μH. The nearest standard value
is 7.2 μH. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. The
RMS and peak inductor current can be found from Equation 29 and Equation 30. For this design, the RMS
inductor current is 5 A and the peak inductor current is 5.8 A. The chosen inductor is a WE 7447798720, which
has a saturation current rating of 7.9 A and an RMS current rating of 6 A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
24
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The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54560-Q1 which is nominally 7.5 A.
VIN(max ) - VOUT
VOUT
60 V - 5 V
5V
´
=
´
= 7.6 mH
LO(min ) =
IOUT ´ KIND
VIN(max ) ´ fSW
5 A x 0.3
60 V ´ 400 kHz
(27)
spacer
IRIPPLE =
VOUT ´ (VIN(max ) - VOUT )
VIN(max ) ´ LO ´ fSW
=
5 V x (60 V - 5 V)
= 1.591 A
60 V x 7.2 mH x 400 kHz
(28)
spacer
(
æ
1 ç VOUT ´ VIN(max ) - VOUT
2
IL(rms ) = (IOUT ) +
´
12 çç
VIN(max ) ´ LO ´ fSW
è
)÷ö
2
÷ =
÷
ø
2
(5 A )
2
æ
5 V ´ (60 V - 5 V ) ö
1
+
´ ç
÷ =5A
ç 60 V ´ 7.2 mH ´ 400 kHz ÷
12
è
ø
(29)
spacer
IL(peak ) = IOUT +
IRIPPLE
1.591 A
= 5A +
= 5.797 A
2
2
(30)
8.2.2.3 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
Equation 31 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw
is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 1.25 A to 3.75 A. Therefore,
ΔIOUT is 3.75 A - 1.25 A = 2.5 A and ΔVOUT = 0.04 × 5 = 0.2 V. Using these numbers gives a minimum
capacitance of 62.5 μF. This value does not take the ESR of the output capacitor into account in the output
voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic
and tantalum capacitors have higher ESR that must be included in load step calculations.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in Figure 37. The excess energy absorbed in the output capacitor will increase the voltage on the
capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods.
Equation 32 calculates the minimum capacitance required to keep the output voltage overshoot to a desired
value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under
light load, Vf is the peak output voltage, and Vi is the initial voltage. For this example, the worst case load step
will be from 3.75 A to 1.25 A. The output voltage increases during this load transition and the stated maximum in
our specification is 4 % of the output voltage. This makes Vf = 1.04 × 5 = 5.2. Vi is the initial capacitor voltage
which is the nominal output voltage of 5 V. Using these numbers in Equation 32 yields a minimum capacitance of
44.1 μF.
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Equation 33 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 33 yields 19.9 μF.
Equation 34 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 34 indicates the ESR should be less than 15.7 mΩ.
The most stringent criteria for the output capacitor is 62.5 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, 3 x
47 μF, 10 V ceramic capacitors with 5 mΩ of ESR will be used. The derated capacitance is 87.4 µF, well above
the minimum required capacitance of 62.5 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 35 can be used to calculate the RMS ripple current that the output capacitor must support. For
this example, Equation 35 yields 459 mA.
2 ´ DIOUT
2 ´ 2.5 A
COUT >
=
= 62.5 mF
fSW ´ DVOUT 400 kHz x 0.2 V
(31)
((I ) - (I ) ) = 7.2 mH x (3.75 A - 1.25 A ) = 44.1 mF
x
(5.2 V - 5 V )
((V ) - (V ) )
2
OH
COUT > LO
2
2
2
OL
2
f
2
2
2
I
1
1
1
1
´
=
= 19.9 mF
x
8 ´ fSW æ VORIPPLE ö 8 x 400 kHz
æ 25 mV ö
ç 1.591 A ÷
ç
÷
è
ø
è IRIPPLE ø
V
25 mV
RESR < ORIPPLE =
= 15.7 mW
IRIPPLE
1.591 A
(32)
COUT >
ICOUT(rms) =
(
VOUT ´ VIN(max ) - VOUT
)=
12 ´ VIN(max ) ´ LO ´ fSW
5V ´
(60 V
- 5 V)
12 ´ 60 V ´ 7.2 mH ´ 400 kHz
(33)
(34)
= 459 mA
(35)
8.2.2.4 Catch Diode
The TPS54560-Q1 requires an external catch diode between the SW pin and GND. The selected diode must
have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be
greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due
to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
60 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54560-Q1.
For the example design, the B560C-13-F Schottky diode is selected for its lower forward voltage and good
thermal characteristics compared to smaller devices. The typical forward voltage of the B560C-13-F is 0.70 volts
at 5 A.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 36 is
used to calculate the total power dissipation, including conduction losses and ac losses of the diode.
The B560C-13-F diode has a junction capacitance of 300 pF. Using Equation 36, the total loss in the diode at the
maximum input voltage is 3.43 Watts.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
26
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PD =
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(V
IN(max ) - VOUT
)´ I
OUT
+
VIN(max )
(60 V
2
´ Vf d
- 5 V ) ´ 5 A x 0.7 V
+
60 V
C j ´ fSW ´ (VIN + Vf d)
=
2
300 pF x 400 kHz x (60 V + 0.7 V)2
= 3.43 W
2
(36)
8.2.2.5 Input Capacitor
The TPS54560-Q1 requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF
of effective capacitance. Some applications will benefit from additional bulk capacitance. The effective
capacitance includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor
must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater
than the maximum input current ripple of the TPS54560-Q1. The input ripple current can be calculated using
Equation 37.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 60 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V or 100 V. For this example, four 2.2 μF, 100 V capacitors in parallel are used. Table 1 shows several
choices of high voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 38. Using the design example values, IOUT = 5 A, CIN = 8.8 μF, ƒsw = 400 kHz, yields
an input voltage ripple of 355 mV and a rms input ripple current of 2.26 A.
ICI(rms ) = IOUT x
VOUT
x
VIN(min )
(V
IN(min ) - VOUT
VIN(min )
) = 5A
5V
´
7V
(7 V
- 5 V)
7V
= 2.26 A
(37)
I
´ 0.25
5 A ´ 0.25
DVIN = OUT
=
= 355 mV
CIN ´ fSW
8.8 mF ´ 400 kHz
(38)
Table 1. Capacitor Types
VENDOR
VALUE (μF)
1 to 2.2
Murata
1 to 4.7
1
1 to 2.2
1 to 1.8
Vishay
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
TDK
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
AVX
1
1 to 4.7
1 to 2.2
EIA Size
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE
DIALECTRIC
100 V
COMMENTS
GRM32 series
50 V
100 V
GRM31 series
50 V
50 V
100 V
VJ X7R series
50 V
100 V
100 V
50 V
100 V
50 V
X7R
C series C4532
C series C3225
50 V
100 V
50 V
X7R dielectric series
100 V
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8.2.2.6 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic
capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10 V or higher
voltage rating.
8.2.2.7 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54560-Q1. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the supply should turn on
and start switching once the input voltage increases above 6.5 V (UVLO start). After the regulator starts
switching, it should continue to do so until the input voltage falls below 5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between VIN and
ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values necessary. For the
example application, a 442 kΩ between VIN and EN (RUVLO1) and a 90.9 kΩ between EN and ground (RUVLO2) are
required to produce the 6.5 V and 5 V start and stop voltages.
(39)
VENA
1.2 V
=
= 90.9 kW
RUVLO2 =
VSTART - VENA
6.5 V - 1.2 V
+
m
1.2
A
+ I1
442 kW
RUVLO1
(40)
8.2.2.8 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 2, R5 is calculated as 53.5 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Due to the input
current of the FB pin, the current flowing through the feedback network should be greater than 1 μA to maintain
the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher
resistor values decreases quiescent current and improves efficiency at low output currents but may also
introduce noise immunity problems.
V
- 0.8 V
æ 5 V - 0.8 V ö
= 10.2 kW x ç
RHS = RLS x OUT
÷ = 53.5 kW
0.8 V
0.8 V
è
ø
(41)
8.2.2.9 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 42 and
Equation 43. For COUT, use a derated value of 87.4 μF. Use equations Equation 44 and Equation 45 to estimate
a starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 1821 Hz and ƒz(mod) is 1100
kHz. Equation 43 is the geometric mean of the modulator pole and the ESR zero and Equation 45 is the mean of
modulator pole and half of the switching frequency. Equation 44 yields 44.6 kHz and Equation 45 gives 19.1 kHz.
Use the geometric mean value of Equation 44 and Equation 45 for an initial crossover frequency. For this
example, after lab measurement, the crossover frequency target was increased to 30 kHz for an improved
transient response.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT(max )
5A
fP(mod) =
=
= 1821 Hz
2 ´ p ´ VOUT ´ COUT 2 ´ p ´ 5 V ´ 87.4 mF
(42)
f Z(mod) =
28
1
1
=
= 1100 kHz
2 ´ p ´ RESR ´ COUT
2 ´ p ´ 1.67 mW ´ 87.4 mF
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(43)
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fco1 =
fp(mod) x f z(mod) =
fco2 =
fp(mod) x
fSW
2
=
1821 Hz x 1100 kHz
1821 Hz x
400 kHz
2
= 44.6 kHz
(44)
= 19.1 kHz
(45)
To determine the compensation resistor, R4, use Equation 46. Assume the power stage transconductance,
gmps, is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5
V, 0.8 V and 350 μA/V, respectively. R4 is calculated to be 16.8 kΩ and a standard value of 16.9 kΩ is selected.
Use Equation 47 to set the compensation zero to the modulator pole frequency. Equation 47 yields 5172 pF for
compensating capacitor C5. 4700 pF is used for this design.
ö
VOUT
æ 2 ´ p ´ fco ´ COUT ö æ
ö
5V
æ 2 ´ p ´ 29.2 kHz ´ 87.4 mF ö æ
R4 = ç
xç
÷ = ç
÷ x ç
÷ = 16.8 kW
÷
gmps
17 A / V
è
ø è 0.8 V x 350 mA / V ø
è
ø è VREF x gmea ø
(46)
C5 =
1
1
=
= 5172 pF
2 ´ p ´ R4 x fp(mod)
2 ´ p ´ 16.9 kW x 1821 Hz
(47)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 48 and Equation 49 for C8 to set the
compensation pole. The selected value of C8 is 47 pF for this design example.
C
x RESR
87.4 mF x 1.67 mW
=
= 8.64 pF
C8 = OUT
R4
16.9 kW
(48)
1
1
C8 =
=
= 47.1 pF
R4 x f sw x p
16.9 kW x 400 kHz x p
(49)
8.2.2.10 Discontinuous Conduction Mode and Eco-Mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 408 mA. The power supply enters Eco-Mode when the output current is lower than 25.3 mA. The
input current draw is 257 μA with no load.
8.2.3 Application Curves
1 A/div
10 V/div
Measurements are taken with standard EVM using a 12V input, 5V output, and 5A load unless otherwise noted.
VIN
10 mV/div
200 mV/div
IOUT
VOUT ±5V offset
Time = 100 Ps/div
Figure 37. Load Transient
VOUT ±5V offset
Time = 4 ms/div
Figure 38. Line Transient (8 V to 40 V)
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2 V/div
EN
4 V/div
4 V/div
VIN
VIN
1 V/div
5 V/div
5 V/div
Measurements are taken with standard EVM using a 12V input, 5V output, and 5A load unless otherwise noted.
VOUT
EN
VOUT
Time = 2 ms/div
Time = 2 ms/div
Figure 40. Start-up With EN
Figure 39. Start-up With VIN
10 V/div
500 mA/div
IL
SW
IL
10 mV/div
10 mV/div
1 A/div
10 V/div
SW
VOUT ± AC Coupled
VOUT ± AC Coupled
Time = 4 Ps/div
Time = 4 Ps/div
Figure 42. Output Ripple DCM
Figure 41. Output Ripple CCM
10 V/div
1 m\A/div
IL
200 mV/div
10 V/div
IL
10 mV/div
200 mA/div
SW
SW
VOUT ± AC Coupled
VIN ± AC Coupled
Time = 1 ms/div
Time = 4 Ps/div
Figure 43. Output Ripple PSM
30
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Figure 44. Input Ripple CCM
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Measurements are taken with standard EVM using a 12V input, 5V output, and 5A load unless otherwise noted.
10 V/div
2 V/div
SW
SW
IL
VOUT
20 mV/div
10 mV/div
200 mA/div
500 mA/div
IL
VIN ± AC Coupled
Time = 4 Ps/div
Time = 40 Ps/div
Figure 45. Input Ripple DCM
Figure 46. Low Dropout Operation
IOUT = 1 A
EN Floating
2 V/div
2 V/div
IOUT = 100 mA
EN Floating
VIN
VIN
VOUT
VOUT
Time = 40 ms/div
Figure 48. Low Dropout Operation
Time = 40 ms/div
Figure 47. Low Dropout Operation
100
100
90
95
80
70
Efficiency (%)
Efficiency (%)
90
85
80
75
60
50
40
30
70
20
VIN =Series4
7V
VIN =36V
36 V
65
60
0
0.5
1
1.5
2
VIN =12V
12 V
VIN =24V
24 V
VIN =48V
48 V
VIN =60V
60 V
2.5
3
3.5
4
IO - Output Current (A)
4.5
10
5
0
0.001
0.00
C024
Figure 49. Efficiency vs Load Current
VIN =7V
7V
VIN =36V
36 V
0.01
VIN =12V
12 V
VIN = 48V
48 V
24VV
VIN = 24
VIN = 60
60VV
0.10
IO - Output Current (A)
Product Folder Links: TPS54560-Q1
C024
Figure 50. Light Load Efficiency
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Measurements are taken with standard EVM using a 12V input, 5V output, and 5A load unless otherwise noted.
100
100
95
90
80
70
Efficiency (%)
85
80
75
60
50
VIN = 6V
6V
VIN =12V
12 V
VIN =24v
24 V
VIN =36v
36 V
VIN =48V
48 V
VIN =60V
60 V
40
30
70
20
VIN =6V
6V
VIN =36V
36 V
65
60
0
0.5
1
1.5
2
2.5
VIN =12V
12 V
VIN =24V
24 V
VIN =48V
48 V
VIN =60V
60 V
3
3.5
4
4.5
IO - Output Current (A)
10
0
0.001
0.00
5
0.01
Figure 51. Efficiency vs Load Current
1.00
C024
Figure 52. Light Load Efficiency
60
100
Gain (dB)
85
80
75
VIN 18in
= 18 V
VINSeries1
= 24 V
VINSeries3
= 36 V
VINSeries6
= 48 V
VINSeries8
= 60 V
70
65
60
0.5
1
1.5
2
2.5
3
3.5
4
4.5
IO - Output Current (A)
120
30
90
20
60
10
30
0
0
±10
±30
±20
±60
±30
±90
VIN = 12 V
VOUT = 5 V
IOUT = 5 A
±40
±50
±120
±150
±60
±180
10
0
150
Phase
40
90
180
Gain
50
95
Efficiency (%)
0.10
IO - Output Current (A)
C024
Phase ()
Efficiency (%)
90
100
1k
5
10k
100k
1M
Frequency (Hz)
C024
C001
Figure 54. Overall Loop Frequency Response
Figure 53. Efficiency vs Output Current
0.6
0.3
Output Voltage Normalized (%)
Output Voltage Normalized (%)
0.5
0.4
0.3
0.2
0.1
±0.0
±0.1
±0.2
±0.3
±0.4
0.2
0.1
0.0
±0.1
±0.2
±0.5
±0.6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IO - Output Current (A)
5.0
±0.3
5
10
15
20
25
30
35
40
45
50
VI - Input Voltage (V)
C024
Figure 55. Regulation vs Load Current
32
4.5
55
60
C024
Figure 56. Regulation vs Input Voltage
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9 Power Supply Recommendations
The design of the device is for operation from an input voltage supply range between 4.5 V and 60 V. Good
regulation of this input supply is essential. If the input supply is more distant than a few inches from the
TPS54560-Q1 converter, the circuit may require additional bulk capacitance besides the ceramic bypass
capacitors. An electrolytic capacitor with a value of 100 μF is a typical choice. Furthermore, if the supply voltage
in the application is likely to reach negative voltage (for example, reverse battery) a forward diode must be
placed at the input of the supply.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR
ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by
the bypass capacitor connections, the VIN pin, and the A node of the catch diode. See Figure 57 for a PCB
layout example. The GND pin should be tied directly to the power pad under the IC and the power pad.
The power pad should be connected to internal PCB ground planes using multiple vias directly under the IC. The
SW pin should be routed to the cathode of the catch diode and to the output inductor. Since the SW connection
is the switching node, the catch diode and output inductor should be located close to the SW pins, and the area
of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top
side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT
resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional
external components can be placed approximately as shown. It may be possible to obtain acceptable
performance with alternate PCB layouts, however this layout has been shown to produce good results and is
meant as a guideline.
10.2 Layout Example
Vout
Output
Capacitor
Topside
Ground
Area
Input
Bypass
Capacitor
Vin
UVLO
Adjust
Resistors
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
BOOT
Catch
Diode
SW
VIN
GND
EN
COMP
RT / CLK
FB
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 57. PCB Layout Example
10.3 Power Dissipation
The following formulas show how to estimate the TPS54560-Q1 power dissipation under continuous conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuous
conduction mode (DCM).
34
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Power Dissipation (continued)
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and
supply current (PQ). Example calculations are shown with the 12 V typical input voltage of the design example.
æV
ö
5V
2
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷ = 5 A 2 ´ 92 mW ´
= 0.958 W
12 V
è VIN ø
(50)
spacer
PSW = VIN ´ fSW ´ IOUT ´ trise = 12 V ´ 400 kHz ´ 5 A ´ 4.9 ns = 0.118 W
(51)
spacer
PGD = VIN ´ QG ´ fSW = 12 V ´ 3nC ´ 400 kHz = 0.014 W
(52)
spacer
PQ = VIN ´ IQ = 12 V ´ 146 mA = 0.0018 W
(53)
Where:
IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
fsw is the switching frequency (Hz).
trise is the SW pin voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current
Therefore,
PTOT = PCOND + PSW + PGD + PQ = 0.958 W + 0.118 W + 0.014 W + 0.0018 W = 1.092 W
(54)
For given TA,
TJ = TA + RTH ´ PTOT
(55)
For given TJMAX = 150°C
TA (max ) = TJ(max ) - RTH ´ PTOT
(56)
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
RTH is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and PCB trace resistance impacting the overall efficiency of the regulator.
10.4 Safe Operating Area
The safe operating area (SOA) of the device is shown in Figure 58, through Figure 61 for 3.3 V, 5 V and 12 V
outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions at
which the internal components are at or below the manufacturer’s maximum operating temperatures. Derating
limits apply to devices soldered directly to a double-sided PCB with 2 oz. copper, similar to the EVM. Careful
attention must be paid to the other components chosen for the design, especially the catch diode.
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90
90
80
80
70
70
60
60
TA (C)
TA (C)
Safe Operating Area (continued)
50
6V
12 V
24 V
36 V
48 V
60 V
40
30
20
0.0
0.5
50
8V
12 V
24 V
36 V
48 V
60 V
40
30
20
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
IOUT (Amps)
5.0
0.0
0.5
1.0
80
80
70
70
60
60
TA (C)
TA (C)
90
50
18 V
24 V
36 V
48 V
60 V
20
0.0
0.5
1.0
3.0
3.5
4.0
4.5
5.0
C048
50
400 LFM
40
200 LFM
100 LFM
30
Nat Conv
20
1.5
2.0
2.5
3.0
3.5
IOUT (Amps)
4.0
4.5
5.0
0.0
0.5
C048
Figure 60. 12-V Outputs
36
2.5
Figure 59. 5-V Outputs
90
30
2.0
IOUT (Amps)
Figure 58. 3.3-V Outputs
40
1.5
C047
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IOUT (Amps)
4.5
5.0
C048
Figure 61. Air Flow Conditions
VIN = 36 V, VO = 12 V
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
• Create an Inverting Power Supply from a Step-Down Regulator, SLVA317
• Create a Split-Rail Power Supply with a Wide Input Voltage Buck Regulator, SLVA369
11.2 Trademarks
Eco-Mode, PowerPAD are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54560QDDAQ1
NRND
SO PowerPAD
DDA
8
75
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
54560Q
TPS54560QDDARQ1
NRND
SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
54560Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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