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TPS7B4254-Q1
SLVSDI1B – APRIL 2016 – REVISED JUNE 2016
TPS7B4254-Q1 150-mA 40-V Voltage-Tracking LDO With 4-mV Tracking Tolerance
1 Features
3 Description
•
•
For automotive off-board sensors and low-current offboard modules, the power supply is through a long
cable from the main board. In such cases, protection
is required in the power devices for the off-board
loads to prevent the onboard components from
damage during a short to GND or short to battery
caused by a broken cable. Off-board sensors require
a power supply as consistent as that for onboard
components to secure high accuracy of data
acquisition.
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C6
–40-V to 45-V Wide Input-Voltage Range
(Maximum)
Output-Voltage Adjust Range: 2 V to 40 V
150-mA Output Current Capability
Very Low Output-Tracking Tolerance, ±4 mV
160-mV Low-Dropout Voltage When IOUT =
100 mA
Low Quiescent Current (I(Q)):
– < 4 µA When ADJ = LOW
– 60 µA Typical at Light Load
Extremely Wide ESR Range
– 10-µF to 500-µF Ceramic Output Capacitor
– ESR Range from 1 mΩ to 20 Ω
Reverse Polarity Protection
Current-Limit and Thermal-Shutdown Protection
Output Short-Circuit-Proof to Ground and Supply
Inductive Clamp at OUT Pin
8-Pin SO PowerPAD™ Package With Exposed
Thermal Pad
The TPS7B4254-Q1 device is designed for
automotive applications with a 45-V load dump. The
device can either be used as one tracking lowdropout (LDO) regulator or as a voltage tracker to
build one closed power loop for off-board sensors
with an onboard main supply. The output of the
device is accurately regulated by a reference voltage
at the ADJ pin.
To provide an accurate power supply to the off-board
modules, the device offers a 4-mV ultralow tracking
tolerance between the ADJ and FB pins across
temperature. The back-to-back PMOS topology
eliminates the need for an external diode under a
reverse-polarity condition. The TPS7B4254-Q1
device also includes thermal shutdown, inductive
clamp, overload, and short-to-battery protection to
prevent damage to onboard components during
extreme conditions.
Device Information(1)
PART NUMBER
PACKAGE
2 Applications
TPS7B4254-Q1
•
•
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Off-Board Sensor Supply
High-Precision Voltage Tracking
Power Switch for Off-Board Load
SO PowerPAD (8)
BODY SIZE (NOM)
4.89 mm × 3.90 mm
Typical Application Schematic
Automotive
Battery
IN
DC-DC or
LDO
OUT
CIN
COU T
TPS7B4254-Q1
ADJ
Off-Board
Sensor
FB
GND
MCU
ADC
Main Board
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7B4254-Q1
SLVSDI1B – APRIL 2016 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Applications ................................................ 14
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Revision A (May 2016) to Revision B
•
Changed MIN values for VADJ, VFB, and VOUT in the Recommended Operating Conditions table ........................................ 4
Changes from Original (April 2016) to Revision A
•
2
Page
Page
Changed data sheet from PRODUCT PREVIEW to PRODUCTION DATA .......................................................................... 1
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SLVSDI1B – APRIL 2016 – REVISED JUNE 2016
5 Pin Configuration and Functions
DDA Package
8-Pin HSOP With Exposed Thermal Pad
Top View
OUT
1
NC
2
8
IN
7
NC
6
GND
5
ADJ
Thermal
GND
3
FB
4
Pad
NC – No internal connection
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
ADJ
5
I
Connect the reference to this pin. A low signal disables the device and a high signal enables
the device. The reference voltage can be connected directly or by a voltage divider for lower
output voltages. To compensate for line influences, connect a capacitor close to the device
pin.
FB
4
I
This pin is the feedback pin, which can connect to the external resistor divider to select the
output voltage.
3, 6
G
Ground reference
IN
8
I
This pin is the device supply. To compensate for line influences, connect a capacitor close to
the device pin.
NC
2, 7
NC
1
O
Block to GND with a capacitor close to the device pins with respect to the capacitance and
ESR requirements listed in the Output Capacitor section.
—
Connect the thermal pad to the GND pin or leave it floating.
GND
OUT
Exposed thermal pad
(1)
Not internally connected.
I = input, O = output, G = ground, NC = no internal connection
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
IN (2)
Unregulated input voltage
MIN
MAX
UNIT
–40
45
V
–1
45
V
(2) (3)
Regulated output voltage
OUT
Voltage difference between the input
and output
IN – OUT
–40
45
V
Reference voltage
ADJ (2)
–0.3
45
V
Feedback input voltage for the tracker
FB (2)
–1
45
V
Reference voltage minus the input
voltage
ADJ – IN (4)
18
V
Operating junction temperature, TJ
–40
150
ºC
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND pin.
An internal diode is connected between the OUT and GND pins with 600-mA dc current capability for inductive clamp protection.
When the (ADJ – IN) voltage is higher than 18 V, the (ADJ – OUT) voltage should be maintained lower than 18 V, otherwise the device
can be damaged.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC
Q100-002 (1)
All pins except NC
±4000
NC pins
±2000
Charged-device model (CDM), per AEC Q100-011
(1)
UNIT
V
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
UNIT
VIN
Unregulated input voltage
4
40
V
VADJ
Reference input voltage
2
18
V
VFB
Feedback input voltage for the tracker
2
18
V
VOUT
Regulated output voltage
2
40
V
COUT
Output capacitor requirements (3)
10
500
µF
0.001
20
Ω
–40
150
ºC
Output ESR requirements (4)
TJ
(1)
(2)
(3)
(4)
4
Operating junction temperature
Within the functional range the device operates as described in the circuit description. The electrical characteristics are specified within
the conditions given in the related Electrical Characteristics table.
VIN > VADJ + VDROPOUT
The minimum output capacitance requirement is applicable for a worst-case capacitance tolerance of 30%. When a resistor divider is
connected between the OUT and FB pins (the output voltage is higher than reference voltage), a 47-nF feedforward capacitor is
required to be connected between the OUT and FB pins for loop stability, and the ESR range of the output capacitor is required to be
from 0.001 to 10 Ω.
Relevant ESR value at f = 10 kHz
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6.4 Thermal Information
TPS7B4254-Q1
THERMAL METRIC (1)
DDA (HSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
45.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.1
°C/W
RθJB
Junction-to-board thermal resistance
27
°C/W
ψJT
Junction-to-top characterization parameter
8.2
°C/W
ψJB
Junction-to-board characterization parameter
26.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VIN = 13.5 V, VADJ ≥ 2 V, TJ = –40ºC to 150ºC, over operating ambient temperature range (unless otherwise noted)
PARAMETER
VIN(UVLO)
IN undervoltage detection
MAX
UNIT
VIN rising
TEST CONDITIONS
3.65
V
VIN falling
2.8
V
ΔVOUT
Output voltage tracking accuracy (1)
IOUT = 100 μA to 150 mA, VIN = 4 to
40 V
VADJ < VIN – 1 V
2 V < VADJ < 18 V
ΔVOUT(ΔIO)
Load regulation, steady-state
ΔVOUT(ΔVI)
MIN
TYP
–4
4
mV
IOUT = 0.1 to 150 mA, VADJ= 5 V
4
mV
Line regulation, steady-state
IOUT = 10 mA, VIN = 6 to 40 V, VADJ
=5V
4
mV
PSRR
Power-supply ripple rejection
frip = 100 Hz, Vrip = 0.5 VPP, COUT =
10 μF, IOUT = 100 mA
VDROPOUT
Dropout voltage (VDROPOUT = VIN –
VOUT)
IOUT = 100 mA, VIN = VADJ ≥ 4 V (2)
IOUT(LIM)
Output current limitation
VADJ = 5 V, OUT short to GND
IR(IN)
Reverse current at IN
VIN = 0 V, VOUT = 40 V, VADJ = 5 V
–2
IR(–IN)
Reverse current at negative IN
VIN = –40 V, VOUT = 0 V, VADJ = 5 V
–10
TSD
Thermal shutdown temperature
TSD_hys
Thermal shutdown hysteresis
70
151
Current consumption
160
260
mV
450
520
mA
0
µA
µA
175
ºC
15
4 V ≤ VIN ≤ 40 V, VADJ = 0 V
IQ
dB
ºC
2
4
µA
4 V ≤ VIN ≤ 40 V, VADJ = 5 V, IOUT <
100 µA
60
100
µA
4 V ≤ VIN ≤ 40 V, VADJ = 5 V, IOUT <
150 mA
210
260
µA
70
140
µA
5.5
µA
V
IQ(DROPOUT Current consumption in dropout
region
)
VIN = VADJ = 5 V, IOUT = 100 μA
IADJ
Reference input current
VADJ = VFB = 5 V
VADJ(LOW)
Reference low signal valid
VOUT = 0 V
0
0.7
VADJ(HIGH)
Reference high signal valid
|VOUT – VADJ| < 4 mV
2
18
V
IFB
FB bias current
VADJ = VFB = 5 V
0.5
µA
(1)
(2)
The tracking accuracy is specified when the FB pin is directly connected to the OUT pin which means VADJ = VOUT, external resistor
divider variance is not included.
Measured when the output voltage, VOUT, has dropped 10 mV from the nominal value.
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6.6 Typical Characteristics
4
4
IOUT = 0.1 mA
IOUT = 70 mA
IOUT = 150 mA
2
2
1
1
0
-1
0
-1
-2
-2
-3
-3
-4
-40
IOUT = 10 mA
IOUT = 100 mA
3
'Vo (mV)
Accuracy (mV)
3
-4
-20
0
20
40
60
Temp (qC)
80
100
120
0
5
10
V
20
'Vin (V)
25
30
35
40
D002
V
Figure 1. Tracking Accuracy vs Ambient Temperature
Figure 2. Line Regulation
400
4
Ta = 25 qC
Ta = 125 qC
3
-40 C
25 C
125 C
350
Dropout Voltage (mV)
2
'VO (mV)
15
D001
1
0
-1
-2
300
250
200
150
100
50
-3
0
-4
0
25
50
75
IOUT (mA)
100
125
0
150
25
50
D003
V
75
IOUT (mA)
100
125
150
D004
VIN = VADJ = 4 V
Figure 3. Load Regulation
Figure 4. Dropout Voltage vs Output Current
400
500
350
490
470
250
IO (mA)
Dropout Voltage (mV)
480
300
200
150
460
450
440
430
100
420
50
410
0
-40
-25
-10
VIN = VADJ = 4 V
5
20 35 50 65
Temperature (qC)
80
95
110 125
-25
-10
D005
IOUT = 100 mA
5
20 35 50 65
Temperature (qC)
80
95
110 125
D006
V
Figure 5. Dropout Voltage vs Ambient Temperature
6
400
-40
Figure 6. Current Limit (IOUT(LIM)) vs Ambient Temperature
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Typical Characteristics (continued)
250
4
-40 qC
25 qC
125 qC
3.5
200
3
IQ (uA)
IQ (uA)
2.5
2
150
100
1.5
1
50
0.5
0
-40
0
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
0
110 125
25
V
Figure 7. Shutdown Current vs Ambient Temperature
150
D008
IOUT = 1 mA
IOUT = 10 mA
IOUT = 100 mA
450
400
350
300
300
IQ (uA)
IQ (uA)
IOUT = 300 mA
IOUT = 0.1 mA
250
250
200
200
150
150
100
100
50
50
0
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
0
5
10
D009
V
15
20
VIN (V)
25
30
35
40
D010
VADJ = 5 V
Figure 9. Quiescent Current vs Ambient Temperature
Figure 10. Quiescent Current vs Input Voltage
120
Power-Supply Rejection Ratio (dB)
140
Power-Supply Rejection Ratio (dB)
125
Figure 8. Quiescent Current vs Output Current
350
120
100
80
60
40
20
0
10
100
500
400
0
-40
75
IOUT (mA)
V
500
450
50
D007
100
COUT = 10 µF
VIN = 14 V
1k
10k
100k
Frequency (Hz)
IOUT = 1 mA
VADJ = 5 V
1M
10M
100M
100
80
60
40
20
0
10
100
D011
TA = 25°C
COUT = 10 µF
VIN = 14 V
Figure 11. PSRR
1k
10k
100k
Frequency (Hz)
IOUT = 100 mA
VADJ = 5 V
1M
10M
100M
D012
TA = 25°C
Figure 12. PSSR
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500
500
400
400
Load Capacitance (µF)
Load Capacitance (µF)
Typical Characteristics (continued)
300
Stable Region
200
100
300
Stable Region
200
100
10
0.001
5
10
ESR of COUT (W)
15
20
10
0.001
2.5
D013
VFB = VOUT
5
ESR of COUT (W)
7.5
10
D014
VFB < VOUT
Figure 13. ESR Stability vs Load Capacitance
Figure 14. ESR Stability vs Load Capacitance
Load Capacitance (µF)
500
VOUT (1 V/div)
400
300
VIN (10 V/div)
Stable Region
200
VOUT(AC) (50 mV/div)
100
IOUT (10 mA/div)
10
0.001
0.5
1
1.5
2
ESR of COUT (W)
2.5
3
D015
V
V
VIN = 6 to 40 V
IOUT = 10 mA
Figure 15. ESR Stability vs Load Capacitance (Multiple
Output Capacitors in parallel)
VADJ = 5 V
40 µs/div
COUT = 10 µF
Figure 16. 6-V to 40-V Line Transient
VIN (10 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
VIN (10 V/div)
VOUT(AC) (50 mV/div)
VOUT(AC) (50 mV/div)
IOUT (10 mA/div)
IOUT (100 mA/div)
VIN = 40 to 6 V
IOUT = 10 mA
VADJ = 5 V
40 µs/div
COUT = 10 µF
Figure 17. 40-V to 6-V Line Transient
8
VIN = 6 to 40 V
IOUT = 100 mA
VADJ = 5 V
40 µs/div
COUT = 10 µF
Figure 18. 6-V to 40-V Line Transient
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Typical Characteristics (continued)
VIN (10 V/div)
VIN (5 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
VOUT(AC) (100 mV/div)
VOUT(AC) (50 mV/div)
IOUT (100 mA/div)
IOUT (50 mA/div)
VIN = 40 to 6 V
IOUT = 100 mA
VADJ = 5 V
40 µs/div
COUT = 10 µF
Figure 19. 40-V to 6-V Line Transient
VIN = 14 V
VADJ = 5 V
IOUT = 10 mA to 100 mA
COUT = 10 µF
100 µs/div
Figure 20. 10-V to 100-mA Load Transient
VIN (5 V/div)
VOUT (1 V/div)
VOUT(AC) (100 mV/div)
IOUT (50 mA/div)
VIN = 14 V
VADJ = 5 V
IOUT = 100 mA to 10 mA
COUT = 10 µF
100 µs/div
Figure 21. 100-mA to 10-mA Load Transient
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7 Detailed Description
7.1 Overview
The TPS7B4254-Q1 device is a monolithic integrated low-dropout voltage tracker with an ultralow tracking
tolerance. Key protection circuits are integrated in the device, including output current limitation, reverse polarity
protection, inductive load clamp, output short-to-battery protection, and thermal shutdown in case of an
overtemperature event.
7.2 Functional Block Diagram
VBAT
OUT
IN
Load
Reverse
Current
Protection
Internal
Supply
Current
Limit
UVLO
Thermal
Shutdown
VREF
–
+
Logic
Control
FB
ADJ
GND
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7.3 Feature Description
7.3.1 Short-Circuit and Overcurrent Protection
The TPS7B4254-Q1 device features integrated fault protection, which makes the device ideal for automotive
applications. To keep the device in a safe area of operation during certain fault conditions, internal current-limit
protection is used to limit the maximum output current. This protection protects the device from excessive power
dissipation. For example, during a short-circuit condition on the output, the current through the pass element is
limited to IOUT(LIM) to protect the device from excessive power dissipation.
7.3.2 Integrated Inductive Clamp Protection
During output turnoff, the cable inductance continues to source the current from the output of the device. The
device integrates an inductive clamp at the OUT pin to help to dissipate the inductive energy stored in the cable.
An internal diode is connected between the OUT and GND pins with a dc-current capability of 600 mA for
inductive clamp protection.
7.3.3 OUT Short-to-Battery and Reverse-Polarity Protection
The TPS7B4254-Q1 device can withstand a short to battery on the output, as shown in Figure 22. Therefore, no
damage to the device occurs.
10
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Feature Description (continued)
OUT
IN
Automotive Battery
14 V (Typical)
Load
10 µF
TPS7B4254-Q1
FB
ADJ
5V
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 22. OUT Short to Battery, VIN = VBAT
A short to the battery can also occur when the device is powered by an isolated supply at lower voltage, as
shown in Figure 23. In this case, the TPS7B4254-Q1 supply-input voltage is set to 7 V when a short to battery
(14 V typical) occurs on the OUT pin, which operates at 5 V. The internal back-to-back PMOS remains on for
1 ms, during which the input voltage of the TPS7B4254-Q1 device charges up to the battery voltage. A diode
connected between the output of the dc-dc converter and the input of the TPS7B4254-Q1 device is required in
case the other loads connected behind the dc-dc converter cannot withstand the voltage of an automotive
battery. To achieve a lower dropout voltage, TI recommends using a Schottky diode. This diode can be
eliminated if the output of the dc-dc converter and the loads connected behind it withstand automotive battery
voltage.
The internal back-to-back PMOS is switched to OFF when reverse polarity or a short to battery occurs for 1 ms.
After that, the reverse current that flows out through the IN pin is less than 10 μA. Meanwhile, a special ESD
structure implemented at the input ensures the device can withstand –40 V.
Short to Battery
Automotive Battery
14 V (Typical)
7V
IN
OUT
Load
DC-DC
10 µF
Other
Loads
TPS7B4254-Q1
FB
ADJ
5V
GND
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Figure 23. OUT Short to Battery, VIN < VBAT
In most cases, the output of the TPS7B4254-Q1 device is shorted to the battery through an automotive cable.
The parasitic inductance on the cable results in LC oscillation at the output of the TPS7B4254-Q1 device when
the short to battery occurs. The peak voltage at the output of the TPS7B4254-Q1 device must be lower than the
absolute-maximum voltage rating (45 V) during LC oscillation.
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Feature Description (continued)
7.3.4 Undervoltage Shutdown
The device has an internally fixed undervoltage-shutdown threshold. Undervoltage shutdown activates when the
input voltage on IN drops below UVLO. This activation ensures the regulator is not latched into an unknown state
during a low input-supply voltage. If the input voltage has a negative transient that drops below the UVLO
threshold and then recovers, the regulator shuts down and then powers up with a standard power-up sequence
when the input voltage is above the required level.
7.3.5 Thermal Protection
The device incorporates a thermal shutdown (TSD) circuit as a protection from overheating. During continuous
normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature
exceeds the TSD trip point, the output turns off. When the junction temperature decreases to 15°C (typical) lower
than the TSD trip point, the output turns on.
NOTE
The purpose of the internal protection circuitry of the TPS7B4254-Q1 device is to protect
against overload conditions and is not intended as a replacement for proper heat-sinking.
Continuously running the device into thermal shutdown degrades device reliability.
7.3.6 Regulated Output (OUT)
The OUT pin is the regulated output based on the required voltage. The output has current limitation. During
initial power up, the regulator has an incorporated soft-start feature to control the initial current through the pass
element.
7.3.7 Adjustable Output Voltage (FB and ADJ)
7.3.7.1 OUT Voltage Equal to the Reference Voltage
With the reference voltage applied directly at the ADJ pin and the FB pin connected to the OUT pin, the voltage
at the OUT pin equals to the reference voltage at the ADJ pin, as shown in Figure 24.
VOUT = VADJ
(1)
VBAT
OUT
IN
Load
10µF
TPS7B4254-Q1
VREF
ADJ
FB
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 24. OUT Voltage Equal to the Reference Voltage
7.3.7.2 OUT Voltage Higher Than Reference Voltage
By using an external resistor divider connected between the OUT and FB pins, an output voltage higher than
reference voltage can be generated as shown in Figure 25. Use Equation 2 to calculate the value of the output
voltage. The recommended range for R1 and R2 is from 10 kΩ to 100 kΩ.
R1 ö
æ
VOUT = VADJ ´ ç 1 +
R2 ÷ø
è
(2)
12
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Feature Description (continued)
IN
VBAT
OUT
Load
10µF
47nF
TPS7B4254-Q1
R1
FB
R2
ADJ
VREF
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 25. OUT Voltage Higher Than the Reference Voltage
7.3.7.3 Output Voltage Lower Than Reference Voltage
By using an external resistor divider connected at the ADJ pin, an output voltage lower than reference voltage
can be generated as shown in Figure 26. Use Equation 3 to calculate the output voltage. The recommended
value for both R1 and R2 is less than 100 kΩ.
R2
VOUT = VREF ´
(3)
R1 + R2
IN
VBAT
OUT
Load
10 μF
TPS7B4254-Q1
VREF
R1
ADJ
FB
R2
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 26. OUT Voltage Lower Than the Reference Voltage
7.4 Device Functional Modes
7.4.1 Operation With VIN < 4 V
The maximum UVLO voltage is 3.65 V, and the device generally operates at an input voltage above 4 V. The
device can also operate at a lower input voltage; no minimum UVLO voltage is specified. At an input voltage
below the actual UVLO voltage, the device does not operate.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7B4254-Q1 device is a 150-mA low-dropout tracking regulator with ultralow tracking tolerance. The
PSpice transient model is available for download on the product folder and can be used to evaluate the basic
function of the device.
8.2 Typical Applications
8.2.1 Application With Output Voltage Equal to the Reference Voltage
Figure 27 shows a typical application circuit for the TPS7B4254-Q1 device. Different values of external
components can be used, depending on the end application. An application may require a larger output capacitor
during fast load steps to prevent a large drop on the output voltage. TI recommends using a low-ESR ceramic
capacitor with a dielectric of type X5R or X7R.
IN
VBAT
1μF
to
22μF
OUT
10 μF
0.1 μF
Load
TPS7B4254-Q1
FB
ADJ
VREF
0.1 μF
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Output Voltage Equals the Reference Voltage
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the design parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
4 V to 40 V
Output voltage
2 V to 40 V
ADJ voltage
2 V to 18 V
Output capacitor
10 µF to 500 µF
Output capacitor ESR range
0.001 Ω to 20 Ω
8.2.1.2 Detailed Design Procedure
To
•
•
•
•
14
begin the design process, determine the following:
Input voltage range
Output voltage
Reference voltage
Output current
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Current limit
8.2.1.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 10 μF with a 0.1 µF ceramic bypass capacitor in parallel. The
voltage rating must be greater than the maximum input voltage.
8.2.1.2.2 Output Capacitor
To ensure the stability of the TPS7B4254-Q1 device, the device requires an output capacitor with a value in the
range from 10 μF to 500 μF and with an ESR range from 0.001 Ω to 20 Ω when the FB pin is directly connected
to the OUT pin. TI recommends selecting a ceramic capacitor with low ESR to improve the load transient
response.
To achieve an output voltage higher than the reference voltage, a resistor divider is connected between the OUT
pin and the FB pin. In this case, a 47-nF feedforward capacitor must be connected between the OUT and FB
pins for loop stability. The ESR of the output capacitor must be from 0.001 Ω to 10 Ω.
When multiple capacitors (two or more) are connected in parallel at the OUT pin, the ESR range of each output
capacitor must be from 0.001 Ω to 3 Ω for loop stability.
In case the FB pin is shorted to ground, the TPS7B4254-Q1 device functions as a power switch with no need for
the output capacitor.
8.2.1.3 Application Curve
VOUT (1 V/div)
VIN (10 V/div)
VOUT(AC) (50 mV/div)
IOUT (100 mA/div)
Figure 28. 6-V to 40-V Line Transient
8.2.2 High-Accuracy LDO
With an accurate voltage rail, the TPS7B4254-Q1 device can be used as an LDO with ultrahigh-accuracy output
voltage by configuring the device as shown in Figure 29.
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IN
VBAT
OUT
Load
1 μF
to
22μ F
0.1 μF
10 μF
TPS7B4254-Q1
Accurate Reference Rail
For Example: REF5050A-Q1
VREF
ADJ
FB
0.1 μF
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 29. High-Accuracy LDO Application
For example, assume the reference voltage is a 5-V rail with 0.1% accuracy. Because the tracking accuracy
between the ADJ and OUT pins is specified below 4 mV across temperature, the output accuracy of the
TPS7B4254-Q1 device can be calculated with Equation 4.
V
´ 0.1% + 4 mV
5 ´ 0.1% + 0.004
Accuracy of VOUT = ADJ
´ 100 % =
´ 100 % = 0.18 %
VOUT
5
(4)
16
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9 Power Supply Recommendations
The device is designed to operate with an input voltage supply from 4 V to 40 V. This input supply must be well
regulated. If the input supply is more than a few inches away from the TPS7B4254-Q1 device, TI recommends
adding an electrolytic capacitor with a value of 10 μF and a ceramic bypass capacitor at the input.
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10 Layout
10.1 Layout Guidelines
For the layout of the TPS7B4254-Q1 device, place the input and output capacitors close to the devices as shown
in the Functional Block Diagram. To enhance the thermal performance, TI recommends surrounding the device
with some vias. Minimize equivalent series inductance (ESL) and ESR to maximize performance and ensure
stability. Place every capacitor as close as possible to the device and on the same side of the PCB as the
regulator.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces for the path between the output capacitor and the OUT pins
because vias can negatively impact system performance and even cause instability.
10.2 Layout Example
OUT
VOUT
IN
7
2
Thermal
Pad
GND
VIN
8
1
GND
3
6
4
5
FB
ADJ
ADJ
Figure 30. TPS7B4254-Q1 Layout Example
18
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS7B4254QDDARQ1
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
4254
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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