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TPS5430-Q1
SLVS751D – NOVEMBER 2007 – REVISED JULY 2015
TPS5430-Q1 3-A Wide-Input-Range Step-Down Converter
1 Features
3 Description
•
•
•
•
The TPS5430-Q1 is a high output current PWM
converter that integrates a low-resistance high side
N-channel MOSFET. Included on the substrate with
the listed features are a high-performance voltage
error amplifier that provides tight voltage regulation
accuracy under transient conditions, an undervoltage
lockout (UVLO) circuit to prevent start-up until the
input voltage reaches 5.5 V, an internally set slowstart circuit to limit inrush currents, and a voltage
feed-forward circuit to improve the transient
response. Using the enable (ENA) pin, shutdown
supply current is reduced to 18 μA typically. Other
features include an active-high enable, overcurrent
limiting, overvoltage protection (OVP), and thermal
shutdown. To reduce design complexity and external
component count, the TPS5430-Q1 feedback loop is
internally compensated. The TPS5430-Q1 regulates
a wide variety of power sources including 24-V
buses.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
Wide Input Voltage Range: 5.5 V to 36 V
Up to 3-A Continuous (4-A Peak) Output Current
High Efficiency up to 95% Enabled by 110-mΩ
Integrated MOSFET Switch
Wide Output Voltage Range: Adjustable Down to
1.22 V With 1.5% Initial Accuracy
Internal Compensation Minimizes External Parts
Count
Fixed 500-kHz Switching Frequency for Small
Filter Size
Improved Line Regulation and Transient
Response by Input Voltage Feed Forward
System Protected by Overcurrent Limiting,
Overvoltage Protection, and Thermal Shutdown
–40°C to 125°C Operating Junction Temperature
Range
Available in Small Thermally Enhanced 8-Pin
SOIC PowerPAD™ Package
2 Applications
•
•
•
Car Audio Power Supplies
High-Power LED Supplies, Battery Chargers
12-V and 24-V Supplied Systems
The TPS5430-Q1 device is available in a thermally
enhanced, easy-to-use 8-pin SOIC PowerPAD™
package. TI provides evaluation modules and the
WEBENCH® software tool to aid in quickly achieving
high-performance power supply designs to meet
aggressive equipment development cycles.
Device Information(1)
PART NUMBER
TPS5430-Q1
PACKAGE
BODY SIZE (NOM)
SO PowerPAD (8)
4.89 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VIN
Efficiency vs Output Current
100
VOUT
PH
VIN
95
TPS5430
BOOT
NC
ENA VSENSE
GND
90
Efficiency − %
NC
85
80
75
70
VI = 12 V
65
VO = 5 V
60
fs = 500 kHz
55
o
TA = 25 C
50
0
0.5
2
1
1.5
2.5
3
IO - Output Current - A
3.5
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS5430-Q1
SLVS751D – NOVEMBER 2007 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Applications ................................................ 11
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision C (July 2009) to Revision D
Page
•
Deleted Swift™ from the title .................................................................................................................................................. 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Dissipation Ratings table .......................................................................................................................................... 4
2
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SLVS751D – NOVEMBER 2007 – REVISED JULY 2015
5 Pin Configuration and Functions
DDA Package
8-Pin SO PowerPAD
Top View
BOOT
1
8
PH
NC
2
7
VIN
NC
3
6
GND
VSENSE
4
5
ENA
PowerPAD
Pin Functions
PIN
I/O
DESCRIPTION
BOOT
O
Boost capacitor for the high-side FET gate driver. Connect 0.01-μF low ESR capacitor from BOOT pin
to PH pin.
No connect, not IO
NO.
NAME
1
2, 3
NC
—
4
VSENSE
I
Feedback voltage for the regulator. Connect to output voltage divider.
5
ENA
I
On and off control. Below 0.5 V, the device stops switching. Float the pin to enable.
6
GND
—
7
VIN
I
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high-quality low-ESR
ceramic capacitor.
8
PH
O
Source of the high side power MOSFET. Connected to external inductor and diode.
—
PowerPAD
—
GND pin must be connected to the exposed pad for proper operation.
Ground. Connect to thermal pad.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VI
Input voltage range
(1) (2)
MIN
MAX
UNIT
VIN
–0.3
40 (3)
V
BOOT
–0.3
50
V
PH (steady state)
–0.6
40 (3)
V
ENA
–0.3
7
V
10
V
3
V
BOOT-PH
VSENSE
–0.3
PH (transient < 10 ns)
–1.2
IO
Source current
PH
Ilkg
Leakage current
PH
TJ
Operating virtual-junction temperature range
Internally Limited
Tstg Storage temperature range
(1)
(2)
(3)
V
10
μA
–40
150
°C
–65
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±1500
Charged device model (CDM), per AEC Q100-011
±1500
Machine model (MM)
±200
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VIN
Input voltage
5.5
36
V
TJ
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TPS5430-Q1
THERMAL METRIC (1)
DDA (SO
PowerPAD)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
41.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
44.4
°C/W
RθJB
Junction-to-board thermal resistance
22.1
°C/W
ψJT
Junction-to-top characterization parameter
5.2
°C/W
ψJB
Junction-to-board characterization parameter
21.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3
4.4
mA
18
50
μA
Start threshold voltage, UVLO
5.3
5.5
Hysteresis voltage, UVLO
330
SUPPLY VOLTAGE (VIN PIN)
IQ
Quiescent current
VSENSE = 2 V, Not switching,
PH pin open
Shutdown, ENA = 0 V
UNDERVOLTAGE LOCKOUT (UVLO)
V
mV
VOLTAGE REFERENCE
Voltage reference accuracy
TJ = 25°C
1.202
1.221
1.239
IO = 0 A to 3 A
1.196
1.221
1.245
400
500
600
kHz
150
200
ns
1.3
V
V
OSCILLATOR
Internally set free-running frequency
Minimum controllable on time
Maximum duty cycle
87%
89%
ENABLE (ENA PIN)
Start threshold voltage, ENA
Stop threshold voltage, ENA
0.5
Hysteresis voltage, ENA
V
450
Internal slow-start time (0~100%)
mV
5.4
8
10
ms
4
5
7
A
13
16
21
ms
135
162
°C
14
°C
CURRENT LIMIT
Current limit
Current-limit hiccup time
THERMAL SHUTDOWN
Thermal shutdown trip point
Thermal shutdown hysteresis
OUTPUT MOSFET
RDS(on)
High-side power MOSFET switch
VIN = 5.5 V
150
110
230
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6.6 Typical Characteristics
530
3.5
VI = 12 V
I Q−Quiescent Current −mA
f − Oscillator Frequency − kHz
520
510
500
490
480
3.25
3
2.75
470
460
−50
−25
0
25
50
75
100
2.5
−50
125
−25
T − Junction Temperature − °C
Figure 1. Oscillator Frequency vs Junction Temperature
T J = 125°C
15
T J = 27°C
T J = –40°C
10
5
0
5
10
15
20
25
30
35
100
125
1.220
1.215
1.210
-50
40
Figure 3. Shutdown Quiescent Current vs Input Voltage
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
Figure 4. Voltage Reference vs Junction Temperature
9
180
TSS − Internal Slow Start Time − ms
V I = 12 V
160
150
140
130
120
110
r
DS(on) −On Resistance −mΩ
75
1.225
V I −Input V oltage −V
170
50
1.230
ENA = 0 V
20
25
Figure 2. Non-Switching Quiescent Current vs Junction
Temperature
VREF - Voltage Reference - V
I SD −Shutdown Current
−µ A
25
0
T J −Junction T emperature − °C
100
8.5
8
7.5
90
80
−50
−25
0
25
50
75
100
T J −Junction Temperature − °C
125
Figure 5. ON Resistance vs Junction Temperature
6
7
−50
−25
0
25
50
75
100
TJ − Junction Temperature − °C
125
Figure 6. Internal Slow Start Time vs Junction Temperature
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Typical Characteristics (continued)
8
170
7.75
Minimum Duty Ratio - %
Minimum Controllable On Time − ns
180
160
150
140
7.50
7.25
130
120
−50
−25
0
25
50
75
100
TJ − Junction Temperature − °C
125
Figure 7. Minimum Controllable ON Time vs Junction
Temperature
7
-50
-25
50
0
25
75
100
TJ - Junction Temperature - °C
125
Figure 8. Minimum Controllable Duty Ratio vs Junction
Temperature
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TPS5430-Q1
SLVS751D – NOVEMBER 2007 – REVISED JULY 2015
www.ti.com
7 Detailed Description
7.1 Overview
The TPS5430-Q1 is a 3-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET. The
TPS5430-Q1 is intended to operate from power rails up to 36 V. This device implements constant-frequency
voltage-mode control with voltage feed forward for improved line regulation and line transient response. Internal
compensation reduces design complexity and external component count.
The integrated 110-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering
3-A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is supplied
by a bootstrap capacitor connected from the BOOT to PH pins. The device reduces the external component
count by integrating the bootstrap recharge diode.
The TPS5430-Q1 has a default input start-up voltage of 5.3 V typical. The ENA pin can be used to disable the
device, reducing the supply current to 18 μA typical. An internal pullup current source enables operation when
the ENA pin is floating. The device includes an internal slow-start circuit that slows the output rise time during
start up to reduce in rush current and output voltage overshoot. The minimum output voltage is the internal
1.221-V feedback reference. Output overvoltage transients are minimized by an Overvoltage Protection (OVP)
comparator. When the OVP comparator is activated, the high-side MOSFET is turned off and remains off until
the output voltage is less than 112.5% of the desired output voltage.
Internal cycle-by-cycle overcurrent protection limits the peak current in the integrated high-side MOSFET. For
continuous overcurrent fault conditions the device will enter hiccup mode overcurrent limiting. Thermal protection
protects the device from overheating.
7.2 Functional Block Diagram
VIN
VIN
1.221 V Bandgap
Reference
UVLO
VREF
SHDN
Slow Start
Boot
Regulator
BOOT
HICCUP
5 µA
ENA
ENABLE
SHDN
SHDN
VSENSE
Z1
Thermal
Protection
NC
SHDN
VIN
Ramp
Generator
NC
SHDN
VSENSE
OVP
Z2
Feed Forward
Gain = 25
HICCUP
PWM
Comparator
SHDN
GND
POWERPAD
Error
Amplifier
SHDN
Overcurrent
Protection
Oscillator
SHDN
Gate Drive
Control
112.5% VREF
Gate
Driver
SHDN
BOOT
PH
VOUT
8
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7.3 Feature Description
7.3.1 Oscillator Frequency
The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500-kHz switching
frequency allows less output inductance for the same output ripple requirement resulting in a smaller output
inductor.
7.3.2 Voltage Reference
The voltage reference system produces a precision reference signal by scaling the output of a temperature
stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of
1.221 V at room temperature.
7.3.3 Enable (ENA) and Internal Slow Start
The ENA pin provides electrical on/off control of the regulator. Once ENA voltage exceeds the threshold voltage,
the regulator starts operation and the internal slow start begins to ramp. If ENA voltage is pulled below the
threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin to ground
or to any voltage less than 0.5 V disables the regulator and activates the shutdown mode. The quiescent current
of the TPS5430-Q1 in shutdown mode is typically 18 μA.
ENA has an internal pullup current source, allowing the user to float the ENA pin. If an application requires
controlling ENA, use open-drain or open-collector output logic to interface with the pin. To limit the start-up inrush
current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its final value, linearly.
The internal slow start time is 8 ms typically.
7.3.4 Undervoltage Lockout (UVLO)
The TPS5430-Q1 incorporates a UVLO circuit to keep the device disabled when VIN (the input voltage) is below
the UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is
grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached,
the internal slow start is released and device start-up begins. The device operates until VIN falls below the UVLO
stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
7.3.5 Boost Capacitor (BOOT)
Connect a 0.01-μF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.
7.3.6 Output Feedback (VSENSE) and Internal Compensation
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, VSENSE voltage should be equal to the voltage
reference, 1.221 V.
The TPS5430-Q1 implements internal compensation to simplify the regulator design. Since the TPS5430-Q1
uses voltage-mode control, a type-3 compensation network has been designed on chip to provide a high
crossover frequency and a high phase margin for good stability. See Internal Compensation Network in the
Advanced Information section for more details.
7.3.7 Voltage Feed Forward
The internal voltage feed forward provides a constant dc power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain, i.e,:
VIN
Feed Forward Gain =
VRAMP(pk-pk)
(1)
The typical feed-forward gain of the TPS5430-Q1 is 25.
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Feature Description (continued)
7.3.8 Pulse-Width Modulation (PWM) Control
The regulator employs a fixed-frequency PWM control method. First, the feedback voltage (VSENSE pin voltage)
is compared to the constant voltage reference by the high-gain error amplifier and compensation network to
produce a error voltage. Then, the error voltage is compared to the ramp voltage by the PWM comparator. In this
way, the error voltage magnitude is converted to a pulse width, which is the duty cycle. Finally, the PWM output
is fed into the gate-drive circuit to control the on time of the high-side MOSFET.
7.3.9 Overcurrent Limiting
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The
drain-to-source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
ignores the overcurrent indicator for the leading-edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle current
limiting.
Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen
when using cycle-by-cycle current limiting. A second mode of current limiting is used, i.e., hiccup mode
overcurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-side
MOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts under
control of the slow-start circuit.
7.3.10 Overvoltage Protection (OVP)
The TPS5430-Q1 has an OVP circuit to minimize voltage overshoot when recovering from output fault
conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a
threshold of 112.5% × VREF. Once VSENSE voltage is higher than the threshold, the high-side MOSFET is
forced off. When VSENSE voltage drops lower than the threshold, the high-side MOSFET is enabled again.
7.3.11 Thermal Shutdown
The TPS5430-Q1 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow-start circuit automatically when the junction
temperature drops 14°C below the thermal shutdown trip point.
7.4 Device Functional Modes
7.4.1 Operation near Minimum Input Voltage
The TPS5430-Q1 is recommended to operate with input voltages above 5.5 V. The typical VIN UVLO threshold
is 5.3 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the
actual UVLO voltage the device will not switch. If ENA is floating or externally pulled up to greater up than 1.3 V,
when V(VIN) passes the UVLO threshold the device will become active. Switching is enabled and the slow-start
sequence is initiated. The TPS5430-Q1 starts linearly ramping up the internal reference voltage from 0 V to its
final value over the internal slow-start time period.
7.4.2 Operation with ENA control
The enable start threshold voltage is 1.3 V (maximum). With ENA held below the 0.5 V minimum stop threshold
voltage the device is disabled and switching is inhibited even if VIN is above its UVLO threshold. The quiescent
current is reduced in this state. If the ENA voltage is increased above the maximum start threshold while V(VIN)
is above the UVLO threshold, the device becomes active. Switching is enabled and the slow-start sequence is
initiated. The device starts linearly ramping up the internal reference voltage from 0 V to its final value over the
internal slow-start time period.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS5430-Q1 is a 3-A, step down regulator with an integrated high side MOSFET. This device is typically
used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 3 A.
Example applications are: High Density Point-of-Load Regulators for Car Audio, High Power LED Supply, Battery
Chargers, and other 12-V and 24-V supplied systems. Use the following design procedure to select component
values for the TPS5430-Q1.
8.2 Typical Applications
8.2.1 Application Circuit, 12 V to 5 V
Figure 9 shows the schematic for a typical TPS5430-Q1 application. The TPS5430-Q1 can provide up to 3-A
output current at a nominal output voltage of 5 V. For proper thermal performance, the exposed thermal pad
underneath the device must be soldered down to the printed-circuit-board.
U1
TPS5430DDA
10.8 - 19.8 V
VIN
EN
C1
10 mF
7
5
2
3
6
VIN
C2
0.01 mF
L1
15 mH
5V
1
VOUT
BOOT
ENA
8
NC
PH
NC
4
D1
B340A
+
C3
220 mF
R1
10 kW
VSNS
GND
PwPd
9
R2
3.24 kW
Figure 9. Application Circuit, 12 V to 5 V
8.2.1.1 Design Requirements
For this design example, use the following as the input parameters:
(1)
DESIGN PARAMETER (1)
EXAMPLE VALUE
Input voltage range
10.8 V to 19.8 V
Output voltage
5V
Input ripple voltage
300 mV
Output ripple voltage
30 mV
Output current rating
3A
Operating frequency
500 kHz
As an additional constraint, the design is set up to be small size and low component height.
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8.2.1.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS5430-Q1. Alternately, the
WEBENCH Software may be used to generate a complete design. The WEBENCH Software uses an iterative
design procedure and accesses a comprehensive database of components when generating a design. This
section presents a simplified discussion of the design process.
To begin the design process, a few parameters must be decided upon. The designer needs to know the
following:
• Input voltage range
• Output voltage
• Input ripple voltage
• Output ripple voltage
• Output current rating
• Operating frequency
8.2.1.2.1 Switching Frequency
The switching frequency for the TPS5430-Q1 is internally set to 500 kHz. It is not possible to adjust the switching
frequency.
8.2.1.2.2 Input Capacitors
The TPS5430-Q1 requires an input decoupling capacitor and, depending on the application, a bulk input
capacitor. The recommended value for the decoupling capacitor, C1, is 10 μF. A high-quality ceramic type X5R
or X7R is required. For some applications, a smaller-value decoupling capacitor may be used, so long as the
input voltage and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum
input voltage, including ripple.
This input ripple voltage can be approximated by Equation 2 :
DVIN +
I OUT(MAX)
C BULK
0.25
ƒsw
ǒ
) I OUT(MAX)
Ǔ
ESR MAX
(2)
Where:
IOUT(MAX) is the maximum load current.
fSW is the switching frequency.
CIN is the input capacitor value.
ESRMAX is the maximum series resistance of the input capacitor.
The maximum RMS ripple current also needs to be checked. For worst-case conditions, this can be
approximated by Equation 3 :
I
OUT(MAX)
I
+
CIN
2
(3)
In this case, the input ripple voltage would be 156 mV and the RMS ripple current would be 1.5 A. The maximum
voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitor is
rated for 25 V and the ripple current capacity is greater than 3 A, providing ample margin. It is very important that
the maximum ratings for voltage and current are not exceeded under any circumstance.
Additionally some bulk capacitance may be needed, especially if the TPS5430-Q1 circuit is not located within
approximately 2 inches from the input voltage source. The value for this capacitor is not critical, but it also should
be rated to handle the maximum input voltage including ripple voltage and should filter the output so that input
ripple voltage is acceptable.
8.2.1.2.3 Output Filter Components
Two components must be selected for the output filter, L1 and C2. Because the TPS5430-Q1 is an internally
compensated device, a limited range of filter component types and values can be supported.
12
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8.2.1.2.3.1 Inductor Selection
To calculate the minimum value of the output inductor, use Equation 4:
V
L
MIN
+
ǒ
V
* V
OUT(MAX)
IN(MAX)
OUT
V
K
I
F
IN(max)
IND
OUT
SW
Ǔ
(4)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
Three things need to be considered when determining the amount of ripple current in the inductor: the peak-topeak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current
and the amount of ripple current determines at what point the circuit becomes discontinuous. For designs using
the TPS5430-Q1, KIND of 0.2 to 0.3 yields good results. Low output ripple voltages can be obtained when paired
with the proper output capacitor, the peak switch current will be well below the current limit set point and
relatively low load currents can be sourced before discontinuous operation.
For this design example use KIND = 0.2 and the minimum inductor value is calculated to be 12.5 μH. The next
highest standard value is 15 μH, which is used in this design.
For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 5:
I
L(RMS)
+
Ǹ
I2
1
)
OUT(MAX) 12
ǒ
V
V
OUT
ǒVIN(MAX) * VOUTǓ
L
IN(MAX)
OUT
F
SW
0.8
Ǔ
2
(5)
and the peak inductor current can be determined with Equation 6:
V
I L(PK) + I
OUT(MAX)
)
OUT
1.6
ǒVIN(MAX) * VOUTǓ
V IN(MAX)
L
OUT
F
(6)
SW
For this design, the RMS inductor current is 3.003 A, and the peak inductor current is 3.31 A. The chosen
inductor is a Sumida CDRH104R-150 15 μH. It has a saturation current rating of 3.4 A and a RMS current rating
of 3.6 A, easily meeting these requirements. A lesser rated inductor could be used, however this device was
chosen because of its low profile component height. In general, inductor values for use with the TPS5430-Q1 are
in the range of 10 μH to 100 μH.
8.2.1.2.3.2 Capacitor Selection
The important design factors for the output capacitor are DC voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because, along with the inductor ripple current, it determines the amount of output ripple voltage. The actual
value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between
the desired closed-loop crossover frequency of the design and LC corner frequency of the output filter. Due to
the design of the internal compensation, it is desirable to keep the closed-loop crossover frequency in the range
3 kHz to 30 kHz, as this frequency range has adequate phase boost to allow for stable operation. For this design
example, it is assumed that the intended closed loop crossover frequency is between 2590 Hz and 24 kHz and
also below the ESR zero of the output capacitor. Under these conditions, the closed-loop crossover frequency is
related to the LC corner frequency as:
f CO +
f LC
2
85 VOUT
(7)
And the desired output capacitor value for the output filter to:
C OUT +
1
3357
L OUT
f CO
V OUT
(8)
For a desired crossover of 18 kHz and a 15-μH inductor, the calculated value for the output capacitor is 220 μF.
The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESR is:
ESR MAX +
2p
1
C OUT
f CO
(9)
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus onehalf the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 10:
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ICOUT(RMS) + 1
Ǹ12
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ȡ VOUT ǒVIN(MAX) * VOUTǓ ȣ
ȧVIN(MAX) LOUT FSW NCȧ
Ȣ
Ȥ
(10)
Where:
NC is the number of output capacitors in parallel.
FSW is the switching frequency.
Other capacitor types can be used with the TPS5430-Q1, depending on the needs of the application.
The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output
ripple voltage:
VPP (MAX) =
ESRMAX × VOUT ×
( VIN(MAX)
)
– VOUT
NC × VIN(MAX) × LOUT × FSW
(11)
Where:
ΔVPP is the desired peak-to-peak output ripple.
NC is the number of parallel output capacitors.
FSW is the switching frequency.
For this design example, a single 220-μF output capacitor is chosen for C3. The calculated RMS ripple current is
143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo
Poscap 10TPB220M, rated at 10 V with a maximum ESR of 40 mΩ and a ripple current rating of 3 A. An
additional small 0.1-μF ceramic bypass capacitor may also used, but is not included in this design.
The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero
when the ESR is at a minimum should not be too far above the internal compensation poles at 24 kHz and
54 kHz.
8.2.1.2.4 Output Voltage Setpoint
The output voltage of the TPS5430-Q1 is set by a resistor divider (R1 and R2) from the output to the VSENSE
pin. Calculate the R2 resistor value for the output voltage of 5 V using Equation 12:
R1 1.221
R2 +
V
* 1.221
OUT
(12)
For any TPS5430-Q1 design, start with an R1 value of 10 kΩ. R2 is then 3.24 kΩ for 5-V output.
8.2.1.2.5 Boot Capacitor
The boot capacitor should be 0.01 μF.
8.2.1.2.6 Catch Diode
The TPS5430-Q1 is designed to operate using an external catch diode between PH and GND. The selected
diode must meet the absolute maximum ratings for the application: reverse voltage must be higher than the
maximum voltage at the PH pin, which is VIN(MAX) + 0.5 V. Peak current must be greater than IOUT(MAX) plus onehalf the peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is
important to note that the catch diode conduction time is typically longer than the high-side FET on time, so
attention paid to diode parameters can make a marked improvement in overall efficiency. Additionally, check that
the device chosen is capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen,
with a reverse voltage of 40 V, forward current of 3 A, and forward voltage drop of 0.5 V.
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8.2.1.2.7 Advanced Information
8.2.1.2.7.1 Output Voltage Limitations
Due to the internal design of the TPS5430-Q1, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
V OUTMAX + 0.87
ǒǒVINMIN * I OMAX
Ǔ
Ǔ ǒ
0.230 ) VD * I OMAX
Ǔ
RL * VD
(13)
Where:
VINMIN is the minimum input voltage.
IOMAX is the maximum load current.
VD is the catch diode forward voltage.
RL is the output inductor series resistance.
This equation assumes maximum on resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time, which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
V OUTMIN + 0.12
ǒǒVINMAX * I OMIN
Ǔ
Ǔ ǒ
0.110 ) VD * I OMIN
Ǔ
RL * VD
(14)
Where:
VINMAX is the maximum input voltage.
IOMIN is the minimum load current.
VD is the catch diode forward voltage.
RL is the output inductor series resistance.
This equation assumes nominal on resistance for the high-side FET and accounts for worst-case variation of
operating frequency set point. Any design operating near the operational limits of the device should be carefully
checked to ensure proper functionality.
8.2.1.2.7.2 Internal Compensation Network
The design equations given in the example circuit can be used to generate circuits using the TPS5430-Q1.
These designs are based on certain assumptions and will tend to always select output capacitors within a limited
range of ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal
compensation of the TPS5430-Q1. Equation 15 gives the nominal frequency response of the internal voltagemode type-3 compensation network:
s
s
1)
1)
2p Fz1
2p Fz2
H(s) +
s
s
s
s
1)
1)
1)
2p Fp1
2p Fp2
2p Fp3
2p Fp0
(15)
ǒ
ǒ
Ǔ ǒ
Ǔ ǒ
Ǔ ǒ
Ǔ
Ǔ ǒ
Ǔ
Where:
Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 Hz
Fp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHz
Fp3 represents the non-ideal parasitics effect.
Using this information along with the desired output voltage, feed-forward gain, and output filter characteristics,
the closed-loop transfer function can be derived.
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8.2.1.2.7.3 Thermal Calculations
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working at light loads in the discontinuous conduction mode.
Conduction loss: Pcon = IOUT2 × RDS(on) × VOUT/VIN
Switching loss: Psw = VIN × IOUT × 0.01
Quiescent current loss: Pq = VIN × 0.01
Total loss: Ptot = Pcon + Psw + Pq
Given TA ≥ Estimated junction temperature: TJ = TA + Rth × Ptot
Given TJMAX = 125°C ≥ Estimated maximum ambient temperature: TAMAX = TJMAX – Rth × Ptot
16
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(16)
(17)
(18)
(19)
(20)
(21)
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8.2.1.3 Application Curves
The performance graphs (Figure 10 through Figure 16) are applicable to the circuit in Figure 9, TA = 25°C (unless
otherwise specified).
0.3
100
VI = 10.8 V
95
0.2
VI = 12 V
Output Regulation - %
Efficiency - %
VI = 15 V
90
VI = 18 V
85
VI = 19.8 V
80
0.1
0
-0.1
-0.2
75
-0.3
0
0.5
1
1.5
2
2.5
IO - Output Current - A
3
0
3.5
0.5
1
2
1.5
2.5
3
IO - Output Current - A
Figure 10. Efficiency vs Output Current
Figure 11. Output Regulation vs Output Current
0.1
VIN = 100 mV/Div (AC Coupled)
0.08
0.06
Input Regulation - %
0.04
IO = 3 A
IO = 1.5 A
0.02
0
PH = 5 V/Div
-0.02
-0.04
IO = 0 A
-0.06
-0.08
-0.1
10.8
13.8
16.8
VI - Input Voltage - V
19.8
t -Time - 500 ns/Div
Figure 12. Input Regulation vs Input Voltage
Figure 13. Input Voltage Ripple and PH Node, IO = 3 A
VOUT = 20 mV/Div (AC Coupled)
VOUT = 50 mV/Div (AC Coupled)
PH = 5 V/Div
IOUT = 1 A /Div
t - Time = 200 μs/Div
t - Time = 500 ns/Div
Figure 14. Output Voltage Ripple and PH Node, IO = 3 A
Figure 15. Transient Response, IO Step 0.75 A to 2.25 A
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VIN = 5 V/Div
VOUT = 2 V/Div
t - Time = 2 ms/Div
Figure 16. Start-Up Waveform, VIN and VOUT
8.2.2 9-V to 21-V Input to 5-V Output Application Circuit
9-V to 21-V Input to 5-V Output Application Circuit
Figure 17 and Figure 18 show application circuits using wide input voltage ranges. The design parameters are
similar to those given for the design example, with a larger value output inductor and a lower closed loop
crossover frequency.
10-35 V
VIN
C1
4.7 mF
ENA
C4
4.7 mF
U1
TPS5430DDA
VIN
BOOT
ENA
PH
NC
NC
VSNS
GND
PwPd
C2
0.01 mF
L1
22 mH
5V
VOUT
D1
B340A
+
C3
220 mF
C3 = Sanyo POSCAP 10TP220M
R1
10 kW
R2
3.24 kW
Figure 17. 10-V to 35-V Input to 5-V Output Application Circuit
9-21 V
VIN
ENA
C1
U1
TPS5430DDA
VIN
BOOT
ENA
PH
NC
NC
VSNS
GND
PwPd
L1
C2
5V
VOUT
D1
B340A
+
C3
C3 = Sanyo POSCAP 10TP220M
R1
R2
Figure 18. 9-V to 21-V Input to 5-V Output Application Circuit
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8.2.3 Circuit Using Ceramic Output Filter Capacitors
Figure 19 shows an application circuit using all ceramic capacitors for the input and output filters, which
generates a 3.3-V output from a 10-V to 24-V input. The design procedure is similar to those given for the design
example, except for the selection of the output filter capacitor values and the design of the additional
compensation components required to stabilize the circuit.
U1
TPS5430DDA
VIN 10-24 V
VIN
C1
4.7 mF
EN
7
VIN
1
BOOT
5
ENA
2
8
PH
NC
3
4
NC
VSNS
6
GND PwPd
9
C2
0.01 mF
L1
15 mH
3.3 V
VOUT
C3
100 mF
D1
MRBS340
R1
10 kW
C7
0.1 mF
C4
150 pF
R3
549 W
R2
5.9 kW
C6
1500 pF
Figure 19. Ceramic Output Filter Capacitors Circuit
8.2.3.1 Output Filter Component Selection
Using Equation 10, the minimum inductor value is 12 μH. A value of 15 μH is chosen for this design.
When using ceramic output filter capacitors, the recommended LC resonant frequency should be no more than
7 kHz. Since the output inductor is already selected at 15 μH, this limits the minimum output capacitor value to:
1
CO (MIN) ≥
2
(2π × 7000) × LO
(22)
The minimum capacitor value is calculated to be 34 μF. For this circuit a larger value of capacitor yields better
transient response. A single 100-μF output capacitor is used for C3. It is important to note that the actual
capacitance of ceramic capacitors decreases with applied voltage. In this example, the output voltage is set to
3.3 V, minimizing this effect.
8.2.3.2 External Compensation Network
When using ceramic output capacitors, additional circuitry is required to stabilize the closed loop system. For this
circuit, the external components are R3, C4, C6, and C7. To determine the value of these components, first
calculate the LC resonant frequency of the output filter:
1
FLC =
2π √ LO × CO (EFF)
(23)
For this example, the effective resonant frequency is calculated as 4109 Hz.
The network composed of R1, R2, R3, C5, C6, and C7 has two poles and two zeros that are used to tailor the
overall response of the feedback network to accommodate the use of the ceramic output capacitors. The pole
and zero locations are given by the following equations:
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Fp1 = 500000 ×
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VO
FLC
(24)
Fz1 = 0.7 × FLC
(25)
Fz2 = 2.5 x FLC
(26)
The final pole is located at a frequency too high to be of concern. The second zero, Fz2 as defined by
Equation 26 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower.
Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3-V output voltage as
calculated using Equation 12. For this design R1 = 10 kΩ and R2 = 5.90 kΩ. With Fp1 = 401 Hz, Fz1 = 2876 Hz,
and Fz2 = 10.3 kHz, the values of R3, C6, and C7 are determined using Equation 27, Equation 28, and
Equation 29:
1
C7 =
2π × Fp1 × (R1 || R2)
(27)
1
2π × Fz1 × C7
1
C6 =
2π × Fz2 × R1
R3 =
(28)
(29)
For this design, using the closest standard values, C7 is 0.1 μF, R3 is 549 Ω, and C6 is 1500 pF. C4 is added to
improve load regulation performance. It is effectively in parallel with C6 in the location of the second pole
frequency, so it should be small in relationship to C6. C4 should be less the 1/10 the value of C6. For this
example, 150 pF works well.
For additional information on external compensation of the wide-voltage-range PWM converter devices, see
Using TPS5410/20/30/31 With Aluminum/Ceramic Output Capacitors (SLVA237).
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9 Power Supply Recommendations
The TPS5430-Q1 is designed to operate from an input voltage supply range between 5.5 V and 36 V. This input
supply should remain within the input voltage supply range and the input capacitance for the device should be
located near the supply input pin. If the input supply is located more than a few inches from the TPS5430-Q1
converter, bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 100 μF is a typical choice.
10 Layout
10.1 Layout Guidelines
Connect a low-ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN pin, and the ground pin. The best way to do this is to
extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass capacitor
as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7-μF ceramic with a
X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC, with an exposed area for connection
to the thermal pad. Use vias to connect this ground area to any internal ground planes. Use additional vias at the
ground side of the input and output filter capacitors as well. The GND pin should be tied to the PCB ground by
connecting it to the ground area under the device as shown in Figure 20.
The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is
the switching node, the inductor should be located very close to PH and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device to
minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as
shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by PH, LOUT, COUT, and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not
route this trace too close to the PH trace. Due to the size of the IC package and the device pin-out, the trace
may need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if a
trace under the output capacitor is not desired.
If using the grounding scheme shown in Figure 20, use a via connection to a different layer to route to the ENA
pin.
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10.2 Layout Example
PH
BOOT
CAPACITOR
OUTPUT
INDUCTOR
RESISTOR
DIVIDER
VOUT
BOOT
PH
NC
VIN
NC
GND
VSENSE
ENA
OUTPUT
FILTER
CAPACITOR
Route feedback
trace under output
filter capacitor or on
other layer
CATCH
DIODE
INPUT
INPUT
BYPASS
BULK
CAPACITOR FILTER
Vin
TOPSIDE GROUND AREA
VIA to Ground Plane
Signal VIA
Figure 20. Design Layout
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Layout Example (continued)
0.110
0.220
0.026
0.118
0.050
0.050
0.080
0.013 DIA 4 PL
0.040
0.098
All dimensions in inches
Figure 21. TPS5430-Q1 Land Pattern
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Using TPS5410/20/30/31 With Aluminum/Ceramic Output Capacitors, SLVA237
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS5430QDDARQ1
Package Type Package Pins Package
Drawing
Qty
ACTIVE SO PowerPAD
DDA
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
NIPDAUAG
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
5430Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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