TPS54821EVM-049

www.ti.com Table of Contents User’s Guide TPS54821 Step-Down Converter Evaluation Module User's Guide ABSTRACT This user’s guide contains information for the TPS54821EVM-049 evaluation module (PWR049) as well as for the TPS54821 dc/dc converter. Also included are the performance specifications, the schematic, and the bill of materials for the TPS54821EVM-049. Table of Contents 1 Introduction.............................................................................................................................................................................2 2 Test Setup and Results.......................................................................................................................................................... 4 3 Board Layout......................................................................................................................................................................... 11 4 Schematic and Bill of Materials...........................................................................................................................................14 5 Revision History................................................................................................................................................................... 16 List of Figures Figure 2-1. TPS54821EVM-049 Efficiency.................................................................................................................................. 5 Figure 2-2. TPS54821EVM-049 Low Current Efficiency..............................................................................................................5 Figure 2-3. TPS54821EVM-049 Load Regulation....................................................................................................................... 6 Figure 2-4. TPS54821EVM-049 Line Regulation........................................................................................................................ 6 Figure 2-5. TPS54821EVM-049 Transient Response................................................................................................................. 7 Figure 2-6. TPS54821EVM-049 Loop Response........................................................................................................................ 7 Figure 2-7. TPS54821EVM-049 Output Ripple........................................................................................................................... 8 Figure 2-8. TPS54821EVM-049 Input Ripple.............................................................................................................................. 8 Figure 2-9. TPS54821EVM-049 Start-Up Relative to VIN ........................................................................................................... 9 Figure 2-10. TPS54821EVM-049 Start-Up Relative to Enable....................................................................................................9 Figure 2-11. TPS54821EVM-049 Start-Up Into Pre-Bias...........................................................................................................10 Figure 2-12. TPS54821EVM-049 Hiccup-Mode Current Limit...................................................................................................10 Figure 3-1. TPS54821EVM-049 Top-Side Assembly................................................................................................................. 11 Figure 3-2. TPS54821EVM-049 Top-Side Layout..................................................................................................................... 12 Figure 3-3. TPS54821EVM-049 Internal Layer-1 Layout.......................................................................................................... 12 Figure 3-4. TPS54821EVM-049 Internal Layer-2 Layout.......................................................................................................... 13 Figure 3-5. TPS54821EVM-049 Bottom-Side Layout................................................................................................................13 Figure 4-1. TPS54821EVM-049 Schematic...............................................................................................................................14 List of Tables Table 1-1. Input Voltage and Output Current Summary...............................................................................................................2 Table 1-2. TPS54821EVM-049 Performance Specification Summary.........................................................................................2 Table 1-3. Output Voltages Available...........................................................................................................................................3 Table 2-1. EVM Connectors and Test Points............................................................................................................................... 4 Table 4-1. TPS54821EVM-049 Bill of Materials.........................................................................................................................15 Trademarks All trademarks are the property of their respective owners. SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 TPS54821 Step-Down Converter Evaluation Module User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated 1 Introduction www.ti.com 1 Introduction 1.1 Background The TPS54821 DC/DC converter is designed to provide up to a 8-A output. The TPS54821 implements split-input power rails with separate input voltage inputs for the power stage and control circuitry. The power stage input (PVIN) is rated for 1.6 V to 17 V whereas the control input (VIN) is rated for 4.5 V to 17 V. The TPS54821EVM-049 provides both inputs but is designed and tested using the PVIN connected to VIN. Rated input voltage and output current range for the evaluation module are given in Table 1-1. This evaluation module is designed to demonstrate the small printed-circuit-board areas that can be achieved when designing with the TPS54821 regulator. The switching frequency is externally set at a nominal 480 kHz. The high-side and low-side MOSFETs are incorporated inside the TPS54821 package along with the gate drive circuitry. The low drain-to-source on-resistance of the MOSFET allows the TPS54821 to achieve high efficiencies and helps keep the junction temperature low at high output currents. The compensation components are external to the integrated circuit (IC), and an external divider allows for an adjustable output voltage. Additionally, the TPS54821 provides adjustable slow start, tracking, and undervoltage lockout inputs. The absolute maximum input voltage is 20 V for the TPS54821EVM-049. Table 1-1. Input Voltage and Output Current Summary EVM INPUT VOLTAGE RANGE OUTPUT CURRENT RANGE TPS54821EVM-049 VIN = 8 V to 17 V (VIN start voltage = 6.528 V) 0 A to 8 A 1.2 Performance Specification Summary A summary of the TPS54821EVM-049 performance specifications is provided in Table 1-2. Specifications are given for an input voltage of VIN = 12 V and an output voltage of 3.3 V, unless otherwise specified. The TPS54821EVM-049 is designed and tested for VIN = 8 V to 17 V with the VIN and PVIN pins connect together with the JP1 jumper. The ambient temperature is 25°C for all measurements, unless otherwise noted. Table 1-2. TPS54821EVM-049 Performance Specification Summary SPECIFICATION TEST CONDITIONS VIN voltage range (PVIN = VIN) MIN TYP MAX 8 12 17 UNIT V VIN start voltage 6.528 V VIN stop voltage 6.193 V 3.3 V Output voltage setpoint Output current range VIN = 8 V to 17 V Line regulation IO = 4 A, VIN = 8 V to 17 V ±0.005 Load regulation VIN = 12 V, IO = 0 A to 8 A ±0.07 % –130 mV IO = 2 A to 6 A Load transient response IO = 6 A to 2 A 0 Voltage change 8 A % Recovery time 80 µs Voltage change 130 mV Recovery time 80 µs 60 kHz Loop bandwidth VIN = 12 V, IO = 8 A Phase margin VIN = 12 V , IO = 8 A 74 ° Input ripple voltage IO = 8 A 900 mVPP Output ripple voltage IO = 8 A 10 mVPP 6 ms 480 kHz 95.9 % Output rise time Operating frequency Maximum efficiency TPS54821EVM-049, VIN = 8 V, IO = 1.5 A 1.3 Modifications These evaluation modules are designed to provide access to the features of the TPS54821. Some modifications can be made to this module. 2 TPS54821 Step-Down Converter Evaluation Module User's Guide SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com Introduction 1.3.1 Output Voltage Setpoint The output voltage is set by the resistor divider network of R7 and R8. R7 is fixed at 10 kΩ. To change the output voltage of the EVM, it is necessary to change the value of resistor R8. Changing the value of R8 can change the output voltage above 0.6 V. The value of R8 for a specific output voltage can be calculated using Equation 1. R 8= 10 k W ´ 0.6 V VOUT - 0.6V (1) Table 1-3 lists the R8 values for some common output voltages. Note that VIN must be in a range so that the on-time is greater than the minimum controllable on-time (94-ns typical, 145-ns maximum), and the maximum duty cycle is less than 95%. The values given in Table 1-3 are standard values, not the exact value calculated using Equation 1. Table 1-3. Output Voltages Available OUTPUT VOLTAGE (V) R8 VALUE (kΩ) 1.8 4.99 2.5 3.16 3.3 2.21 5 1.37 1.3.2 Slow-Start Time The slow-start time can be adjusted by changing the value of C8. Use Equation 2 to calculate the required value of C8 for a desired slow-start time. C8(nF)= Tss(ms) ´ Iss(μA) Vref(V) (2) The EVM is set for a slow-start time of 5.7 ms using C8 = 0.022 µF. 1.3.3 Track In The TPS54821 can track an external voltage during start-up. The J3 connector is provided to allow connection to that external voltage. Ratiometric or simultaneous tracking can be implemented using resistor divider R5 and R6. See the TPS54821 4.5 V to 17 V Input, 8 A Synchronous Step Down Converter Data Sheet for details. 1.3.4 Adjustable UVLO The undervoltage lockout (UVLO) can be adjusted externally using R1 and R2. The EVM is set for a start voltage of 6.528 V and a stop voltage of 6.193 V using R1 = 35.7 kΩ and R2 = 8.06 kΩ. Use Equation 3 and Equation 4 to calculate required resistor values for different start and stop voltages. æV ö VSTART ç ENFALLING ÷ - VSTOP V è ENRISING ø R1= æ VENFALLING ö Ip ç 1÷ +Ih è VENRISING ø R2= R1× VENFALLING VSTOP - VENFALLING +R1(Ip +Ih) (3) (4) SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 TPS54821 Step-Down Converter Evaluation Module User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated 3 Introduction www.ti.com 1.3.5 Input Voltage Rails The EVM is designed to accommodate different input voltage levels for the power stage and control logic. During normal operation, the PVIN and VIN inputs are connected using a jumper across JP1. The single input voltage is supplied at J1. If desired, these two input voltage rails may be separated by removing the jumper across JP1. Two input voltages must then be provided at both J1 and J2. 2 Test Setup and Results This section describes how to properly connect, set up, and use the TPS54821EVM-049 evaluation module. The section also includes test results typical for the evaluation module and covers the following: • Efficiency • Output voltage regulation • Load transients • Loop response • Output ripple • Input ripple • Start-up 2.1 Input/Output Connections The TPS54821EVM-049 is provided with input/output connectors and test points as shown in Table 2-1. A power supply capable of supplying 4 A must be connected to J1 through a pair of 20 AWG wires. The jumper across JP1 must be in place. See Section 1.3.5 for split-input voltage rail operation. The load must be connected to J4 through a pair of 20 AWG wires. The maximum load current capability must be 8 A. Wire lengths must be minimized to reduce losses in the wires. Test-point TP1 provides a place to monitor the VIN input voltages with TP2 providing a convenient ground reference. TP9 is used to monitor the output voltage with TP10 as the ground reference. Table 2-1. EVM Connectors and Test Points REFERENCE DESIGNATOR 4 Function J1 PVIN input voltage connector. (See Table 1-1 for VIN range.) J2 VIN input voltage connector. Not normally used. J3 2-pin header for tracking voltage input and ground J4 VOUT, 3.3 V at 8-A maximum J5 2-pin header for tracking output and ground JP1 PVIN to VIN jumper. Normally closed to tie VIN to PVIN for common rail voltage operation. JP2 2-pin header for enable. Connect EN to ground to disable, open to enable. TP1 PVIN test point at PVIN connector TP2 GND test point at PVIN connector TP3 VIN test point at VIN connector TP4 GND test point at VIN connector TP5 Test point provided to connect external voltage source for PWRGD pullup. TP6 PWRGD test point TP7 PH test point TP8 Test point between voltage divider network and output. Used for loop response measurements. TP9 Output voltage test point at VOUT connector TP10 GND test point at VOUT connector TPS54821 Step-Down Converter Evaluation Module User's Guide SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com Test Setup and Results 2.2 Efficiency The efficiency of this EVM peaks at a load current of about 2 A and then decreases as the load current increases toward full load. Figure 2-1 shows the efficiency for the TPS54821EVM-049 at an ambient temperature of 25°C. 100 90 80 Efficiency (%) 70 60 50 40 30 20 VIN = 8 V VIN = 12 V VIN = 17 V 10 0 0 1 2 3 4 Output Current (A) 5 6 7 8 G001 Figure 2-1. TPS54821EVM-049 Efficiency Figure 2-2 shows the efficiency for the TPS54821EVM-049 using a semi-log scale to more easily show efficiency at lower output currents. The ambient temperature is 25°C. 100 90 80 Efficiency (%) 70 60 50 40 30 20 VIN = 8 V VIN = 12 V VIN = 17 V 10 0 0.001 0.01 0.1 1 Output Current (A) G002 Figure 2-2. TPS54821EVM-049 Low Current Efficiency The efficiency may be lower at higher ambient temperatures, due to temperature variation in the drain-to-source resistance of the internal MOSFET. SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 TPS54821 Step-Down Converter Evaluation Module User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated 5 Test Setup and Results www.ti.com 2.3 Output Voltage Load Regulation Figure 2-3 shows the load regulation for the TPS54821EVM-049. 0.1 VIN = 8 V VIN = 12 V VIN = 17 V 0.08 Output Voltage Deviation (%) 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.1 0 1 2 3 4 Output Current (A) 5 6 7 8 G003 Figure 2-3. TPS54821EVM-049 Load Regulation Measurements are given for an ambient temperature of 25°C. 2.4 Output Voltage Line Regulation Figure 2-4 shows the line regulation for the TPS54821EVM-049. 0.02 Output Voltage Deviation (%) 0.015 0.01 0.005 0 −0.005 −0.01 −0.015 IOUT = 4 A −0.02 8 9 10 11 12 13 Input Voltage (V) 14 15 16 17 G004 Figure 2-4. TPS54821EVM-049 Line Regulation 6 TPS54821 Step-Down Converter Evaluation Module User's Guide SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com Test Setup and Results 2.5 Load Transients Figure 2-5 shows the TPS54821EVM-049 response to load transients. The current step is from 25% to 75% of maximum rated load at 12-V input. The current step slew rate is 1 A/µs. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. IOUT = 2 A/div 2 A to 6 A load step, slew rate = 1 A / µsec V OUT = 100 mV/div (ac coupled) Time = 100 µs/div Figure 2-5. TPS54821EVM-049 Transient Response 2.6 Loop Characteristics 50 180 Gain Phase 150 40 120 30 90 20 60 10 30 0 0 Gain (dB) 60 −10 −30 −20 −60 −30 −90 −40 −120 −50 −150 −60 100 1000 10000 Frequency (Hz) 100000 Phase (°) Figure 2-6 shows the TPS54821EVM-049 loop-response characteristics. Gain and phase plots are shown for VIN voltage of 12 V. Load current for the measurement is 8 A. −180 1000000 G001 Figure 2-6. TPS54821EVM-049 Loop Response SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 TPS54821 Step-Down Converter Evaluation Module User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated 7 Test Setup and Results www.ti.com 2.7 Output Voltage Ripple Figure 2-7 shows the TPS54821EVM-049 output voltage ripple. The output current is the rated full load of 8 A and VIN = 12 V. The ripple voltage is measured directly across the output capacitors. VOUT = 20 mV/div (ac coupled) PH = 5 V/div Time = 1 µs/div Figure 2-7. TPS54821EVM-049 Output Ripple 2.8 Input Voltage Ripple Figure 2-8 shows the TPS54821EVM-049 input voltage. The output current is the rated full load of 8 A and VIN = 12 V. The ripple voltage is measured directly across the input capacitors. VIN = 500 mV/div (ac coupled) PH = 5 V/div Time = 1 µs/div Figure 2-8. TPS54821EVM-049 Input Ripple 8 TPS54821 Step-Down Converter Evaluation Module User's Guide SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com Test Setup and Results 2.9 Powering Up Figure 2-9 and Figure 2-10 show the start-up waveforms for the TPS54821EVM-049. In Figure 2-9, the output voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1 and R2 resistor divider network. In Figure 2-10, the input voltage is initially applied and the output is inhibited by using a jumper at JP2 to tie EN to GND. When the jumper is removed, EN is released. When the EN voltage reaches the enable-threshold voltage, the start-up sequence begins and the output voltage ramps up to the externally set value of 3.3 V. The input voltage for these plots is 12 V and the load is 1 Ω. PWRGD is pulled up to an external 5 V supply at TP5. VIN = 10 V/div SS/TR = 1 V/div VOUT = 2 V/div PWRGD = 5 V/div Time = 5 ms/div Figure 2-9. TPS54821EVM-049 Start-Up Relative to VIN EN = 5 V/div SS/TR = 1 V/div VOUT = 2 V/div PWRGD = 5 V/div Time = 5 ms/div Figure 2-10. TPS54821EVM-049 Start-Up Relative to Enable SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 TPS54821 Step-Down Converter Evaluation Module User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated 9 Test Setup and Results www.ti.com 2.10 Pre-Bias Start-Up The TPS54821 is designed to start up into a pre-biased output. The output voltage is not discharged to ground at the beginning of the slow-start sequence. Figure 2-11 shows the start-up waveform with the output voltage pre-biased to 1 V. VIN = 5 V/div VOUT = 1 V/div (1 V pre-bias) Time = 2 ms/div Figure 2-11. TPS54821EVM-049 Start-Up Into Pre-Bias 2.11 Hiccup-Mode Current Limit The TPS54821 features hiccup-mode current limit. When an overcurrent event occurs, the TPS54821 shuts down and restarts. Figure 2-12 shows restart sequence in an overcurrent condition. PH = 10 V/div IOUT = 10 A/div VOUT = 2 V/div Time = 20 ms/div Figure 2-12. TPS54821EVM-049 Hiccup-Mode Current Limit 10 TPS54821 Step-Down Converter Evaluation Module User's Guide SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com Board Layout 3 Board Layout This section provides a description of the TPS54821EVM-049 board layout and layer illustrations. 3.1 Layout The board layout for the TPS54821EVM-049 is shown in Figure 3-1 through Figure 3-5. The top-side layer of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper. The top layer contains the main power traces for PVIN, VIN, VOUT, and VPHASE. Also on the top layer are connections for the remaining pins of the TPS54821 and a large area filled with ground. The internal layer-2 is primarily ground with additional fill areas for PVIN, VIN, and VOUT. The bottom and internal layer-2 contain ground planes only. The top-side ground traces are connected to the bottom and internal ground planes with multiple vias placed around the board including five vias directly under the TPS54821 device to provide a thermal path from the top-side ground plane to the bottom-side ground plane. The input decoupling capacitors (C2 and C4) and bootstrap capacitor (C5) are all located as close to the IC as possible. Additionally, the voltage setpoint resistor divider components are kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation, the copper VOUT trace at the J4 output connector. For the TPS54821, an additional input bulk capacitor may be required, depending on the EVM connection to the input supply. Critical analog circuits such as the voltage setpoint divider, frequency set resistor, slow-start capacitor, and compensation components are terminated to ground using a wide ground trace separate from the power ground pour. Figure 3-1. TPS54821EVM-049 Top-Side Assembly SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 TPS54821 Step-Down Converter Evaluation Module User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated 11 Board Layout www.ti.com Figure 3-2. TPS54821EVM-049 Top-Side Layout Figure 3-3. TPS54821EVM-049 Internal Layer-1 Layout 12 TPS54821 Step-Down Converter Evaluation Module User's Guide SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com Board Layout Figure 3-4. TPS54821EVM-049 Internal Layer-2 Layout Figure 3-5. TPS54821EVM-049 Bottom-Side Layout SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 TPS54821 Step-Down Converter Evaluation Module User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated 13 Schematic and Bill of Materials www.ti.com 4 Schematic and Bill of Materials This section presents the TPS54821EVM-049 schematic and bill of materials. 4.1 Schematic Figure 4-1 is the schematic for the TPS54821EVM-049. TP5 R4 100k TP6 U1 R3 100k TPS54821RHL 1 2 TP1 J1 VIN = 8 - 17 V 2 PVIN 4 TP2 1 GND 3 5 C1 6 C2 10uF 1 V_SNS 7 RT/CLK PWRGD GND BOOT GND PH PVIN PH PVIN EN VIN SS/TR V_SNS COMP PWPD 15 14 C5 0.1uF 13 11 10 C10 47uF C9 47uF EN R5 4.64k C11 470pF GND 1 2 TP4 EN C3 GND J5 1 C8 0.022uf V_SNS R10 1 TRACK OUT GND J3 1 TRACK IN GND R8 2.21k C4 4.7uF JP2 EN R7 10.0k 2 2 VIN GND R6 51.1 TP8 R9 1 R1 35.7k TP3 VOUT 2 8 C6 3900pF J2 J4 1 9 C7 39pF 2 TP9 VOUT = 3.3 V, 8 A TP10 1 VIN L1 3.3 uH 12 JP1 PVIN TP7 1 1 R2 8.06k 1 NOT INSTALLED 2 Figure 4-1. TPS54821EVM-049 Schematic 14 TPS54821 Step-Down Converter Evaluation Module User's Guide SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com Schematic and Bill of Materials 4.2 Bill of Materials Table 4-1 presents the bill of materials for the TPS54821EVM-049. Table 4-1. TPS54821EVM-049 Bill of Materials COUNT REFDES VALUE DESCRIPTION SIZE PART NUMBER MFR 0 C1 Open Capacitor, Ceramic 1210 Std Std 1 C2 10 µF Capacitor, Ceramic, 25 V, X5R, 20% 1210 Std Std 0 C3 Capacitor, Ceramic 0603 Std Std 1 C4 4.7 µF Capacitor, Ceramic, 25 V, X5R, 10% 0805 Std Std 1 C5 0.1 µF Capacitor, Ceramic, 25 V, X5R, 10% 0603 Std Std 1 C6 3900 pF Capacitor, Ceramic, 50 V, X7R, 10% 0603 Std Std 1 C7 39 pF Capacitor, Ceramic, 50 V, COG, 10% 0603 Std Std 1 C8 0.022 µF Capacitor, Ceramic, 25 V, X7R, 10% 0603 Std Std 2 C9, C10 47 µF Capacitor, Ceramic, 10 V, X5R, 10% 1210 Std Std 0 C11 470 pF Capacitor, Ceramic, 50 V, X7R, 10% 0603 Std Std ED555/2DS OST 1 J2 ED555/2DS Terminal Block, 2-pin, 6-A, 3.5 mm 0.27 × 0.25 inch 2 J1, J4 ED120/2DS Terminal Block, 2-pin, 15-A, 5.1 mm 0.40 × 0.35 inch ED120/2DS OST 4 JP1, JP2,J3, PEC02SAAN J5 Header, Male 2-pin, 100 mil spacing 0.100 inch × 2 PEC02SAAN Sullins 1 L1 3.3 µH Inductor, SMT, 10-A, 13.7 milliΩ 0.400 × 0.453 inch IHLP4040DZE R3R3M01 Vishay 1 R1 35.7 k Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R2 8.06 k Resistor, Chip, 1/16W, 1% 0603 Std Std 2 R3, R4 100 k Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R5 4.64 k Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R6 51.1 Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R7 10.0 k Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R8 2.21 k Resistor, Chip, 1/16W, 1% 0603 Std Std 0 R9, R10 Open Resistor, Chip, 1/16W, 1% 0603 Std Std 4 TP1, TP3, TP7, TP9 5000 Test Point, Red, Thru Hole Color Keyed 0.100 × 0.100 inch 5000 Keystone 6 TP2, TP4, TP5, TP6, TP8, TP10 5001 Test Point, Black, Thru Hole Color Keyed 0.100 × 0.100 inch 5001 Keystone 1 U1 TPS54821RHL IC, 1.6V-17V Synchronous Buck PWM Converter with Integrated MOSFET 3.5mm × TPS54821RHL TI 3.5mm QFN14 2 — Shunt, 100-mil, Black 0.100 929950-00 1.25 × 0.25 inch THT-13-457-10 Brady 1 — Label (see note 5) 1 — PCB, 2.5” × 2.5” × 0.062” PWR049 3M Any Notes 1. 2. 3. 4. 5. These assemblies are ESD sensitive, ESD precautions shall be observed. These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable. These assemblies must comply with workmanship standards IPC-A-610 Class 2. Ref designators marked with an asterisk (‘**’) cannot be substituted. All other components can be substituted with equivalent MFG's components. Install label in silkscreened box after final wash. Text shall be 8 pt font SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 TPS54821 Step-Down Converter Evaluation Module User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated 15 Revision History www.ti.com 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (October 2011) to Revision A (August 2021) Page • Updated user's guide title................................................................................................................................... 2 • Updated the numbering format for tables, figures, and cross-references throughout the document. ................2 16 TPS54821 Step-Down Converter Evaluation Module User's Guide SLVU479A – OCTOBER 2011 – REVISED AUGUST 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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