Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
TPS54821 4.5 V to 17 V Input, 8 A Synchronous Step Down Converter With Hiccup
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The TPS54821 in thermally enhanced 3.5 mm x 3.5
mm QFN package is a full featured 17 V, 8 A
synchronous step down converter which is optimized
for small designs through high efficiency and
integrating the high-side and low-side MOSFETs.
Further space savings are achieved through current
mode control, which reduces component count, and
by selecting a high switching frequency, reducing the
inductor's footprint.
1
•
•
Integrated 26 mΩ / 19 mΩ MOSFETs
Split Power Rail: 1.6 V to 17 V on PVIN
200 kHz to 1.6 MHz Switching Frequency
Synchronizes to External Clock
0.6V ±1% Voltage Reference Over Temperature
Low 2 µA Shutdown Quiescent Current
Monotonic Start-Up into Pre-biased Outputs
Adjustable Slow Start/Power Sequencing
Power Good Output Monitor for Undervoltage and
Overvoltage
Adjustable Input Undervoltage Lockout
Software Tools Available
2 Applications
•
•
•
•
•
Digital TV Power Supplies
Set Top Boxes
Blu-ray DVDs
Home Terminals
High Performance Point of Load Regulation
The output voltage startup ramp is controlled by the
SS/TR pin which allows operation as either a stand
alone power supply or in tracking situations. Power
sequencing is also possible by correctly configuring
the enable and the open drain power good pins.
Cycle by cycle current limiting on the high-side FET
protects the device in overload situations and is
enhanced by a low-side sourcing current limit which
prevents current runaway. There is also a low-side
sinking current limit which turns off the low-side
MOSFET to prevent excessive reverse current.
Hiccup protection will be triggered if the overcurrent
condition has persisted for longer than the preset
time. Thermal hiccup protection disables the device
when the die temperature exceeds the thermal
shutdown temperature and enables the part again
after the built-in thermal shutdown hiccup time.
Device Information(1)
PART NUMBER
TPS54821
PACKAGE
VQFN (14)
BODY SIZE (NOM)
3.50 mm x 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Cin
Efficiency, VOUT = 3.3 V, FSW = 480 kHz
100
90
Cboot
80
VOUT
Lo
EN
PH
PWRGD
VSENSE
SS/TR
RT/CLK
GND
COMP
Css
Rrt C2
R3
C1
Exposed
Thermal
Pad
Co
R1
Efficiency (%)
PVIN
VIN
TPS54821
BOOT
VIN
70
60
50
40
30
R2
VIN = 8 V
VIN = 12 V
VIN = 17 V
20
10
0
0
1
2
3
4
5
Output Current (A)
6
7
8
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application .................................................. 21
9 Power Supply Recommendations...................... 29
10 Layout................................................................... 30
10.1 PCB Layout Guidelines......................................... 30
10.2 Layout Example .................................................... 31
11 Device and Documentation Support ................. 33
Detailed Description ............................................ 10
11.1 Trademarks ........................................................... 33
11.2 Electrostatic Discharge Caution ............................ 33
11.3 Glossary ................................................................ 33
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
12 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2014) to Revision B
Page
•
Deleted SWIFT™ from the data sheet title ........................................................................................................................... 1
•
Deleted Features: For SWIFT™ Documentation visit http://www.ti.com/swift........................................................................ 1
•
Moved Storage temperature to the Absolute Maximum Ratings............................................................................................ 4
•
Changed Handling Ratings to ESD Ratings .......................................................................................................................... 4
Changes from Original (October 2011) to Revision A
Page
•
Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation ............... 1
•
Deleted Feature: –40°C to 125°C Operating Junction Temperature Range ......................................................................... 1
•
Added the I/O column to the Pin Functions table .................................................................................................................. 3
•
Added IOUT = 8A and IOUT = 6A to the Operating Junction Temperature row of the ABS MAX table, also Min = -40
and Max =150 ........................................................................................................................................................................ 4
2
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
5 Pin Configuration and Functions
RHL Package
14 Pins
(Top View)
RT/CLK
1
PWRGD
14
GND 2
13 BOOT
GND 3
12 PH
Exposed
Thermal Pad
(15)
PVIN 4
PVIN 5
11 PH
10 EN
VIN 6
9 SS/TR
7
VSENSE
8
COMP
Pin Functions
PIN
NAME
NO.
DESCRIPTION
I/O
1
I
Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the
switching frequency of the device; In CLK mode, the device synchronizes to an external clock.
GND
2, 3
-
Return for control circuitry and low-side power MOSFET.
PVIN
4, 5
I
Power input. Supplies the power switches of the power converter.
VIN
6
I
Supplies the control circuitry of the power converter.
VSENSE
7
I
Inverting input of the gm error amplifier.
COMP
8
I
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation to this pin.
SS/TR
9
I
Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference
rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and
sequencing.
RT/CLK
EN
10
I
Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors.
PH
11, 12
O
The switch node.
BOOT
13
O
A bootstrap cap is required between BOOT and PH. The voltage on this cap carries the gate drive
voltage for the high-side MOSFET.
PWRGD
14
O
Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, EN shutdown or during slow start.
Exposed Thermal
PAD
15
-
Thermal pad of the package and signal ground and it must be soldered down for proper operation.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
3
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input Voltage
Output Voltage
(1)
MIN
MAX
VIN
–0.3
20
PVIN
–0.3
20
EN
–0.3
6
BOOT
–0.3
27
VSENSE
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
6
SS/TR
–0.3
3
RT/CLK
–0.3
6
BOOT-PH
0
7.5
PH
–1
20
PH 10ns Transient
20
0.2
V
±100
µA
PH
Current Limit
A
PH
Current Limit
PVIN
Current Limit
COMP
Operating Junction Temperature
A
±200
µA
PWRGD
–0.1
5
mA
IOUT = 8 A
–40
125
IOUT = 6 A
–40
150
–65
150
Storage temperature, Tstg
(1)
V
–3
RT/CLK
Sink Current
V
–0.2
Vdiff (GND to exposed thermal pad)
Source Current
UNIT
°C
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Input voltage range
VIN
4.5
17
V
Power stage input voltage range
PVIN
1.6
17
V
Output current
TJ = –40°C to 125°C
Operating junction temperature, TJ
4
0
8
A
IOUT = 6 A
–40
150
°C
IOUT = 8 A
–40
125
°C
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
6.4 Thermal Information
TPS54821
THERMAL METRIC (1) (2)
RθJA
Junction-to-ambient thermal resistance
RθJA
Junction-to-ambient thermal resistance (3)
32
RθJCtop
Junction-to-case (top) thermal resistance
64.8
RθJB
Junction-to-board thermal resistance
14.4
ψJT
Junction-to-top characterization parameter
0.5
ψJB
Junction-to-board characterization parameter
14.7
RθJCbot
Junction-to-case (bottom) thermal resistance
3.2
(1)
(2)
(3)
UNITS
RHL (14 PINS)
47.2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where
distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below
125°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more
information.
Test board conditions:
(a) 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer
(d) 4 0.010 inch thermal vias located under the device package
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN AND PVIN PINS)
PVIN operating input voltage
1.6
17
V
VIN operating input voltage
4.5
17
V
4.5
V
VIN internal UVLO threshold
VIN rising
4.0
VIN internal UVLO hysteresis
150
VIN shutdown supply Current
EN = 0 V
VIN operating – non switching supply current
VSENSE = 610 mV
mV
2
5
μA
600
800
μA
1.21
1.26
V
ENABLE AND UVLO (EN PIN)
Enable threshold
Rising
Enable threshold
Falling
Input current
EN = 1.1 V
1.15
μA
Hysteresis current
EN = 1.3 V
3.3
μA
1.10
1.17
VOLTAGE REFERENCE
Voltage reference
0 A ≤ IOUT ≤ 8A
0.594
0.6
0.606
V
MOSFET
High-side switch resistance
BOOT-PH = 3 V
32
60
mΩ
High-side switch resistance (1)
BOOT-PH = 6 V
26
40
mΩ
Low-side Switch Resistance (1)
VIN = 12 V
19
30
mΩ
ERROR AMPLIFIER
Error amplifier Transconductance (gm)
–2 μA < ICOMP < 2 μA, V(COMP) = 1 V
Error amplifier dc gain
VSENSE = 0.6 V
Error amplifier source/sink
V(COMP) = 1 V, 100 mV input overdrive
Start switching threshold
1300
μMhos
4000
V/V
±110
μA
0.25
COMP to Iswitch gm
(1)
1000
21
V
A/V
Measured at pins
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
5
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-side switch current limit threshold
10.5
14.5
17
A
Low-side switch sourcing current limit
9.5
11.5
15
A
3
4
CURRENT LIMIT
Low-side switch sinking current limit
2
Hiccup wait time
Hiccup time before re-start
A
512
Cycles
16384
Cycles
THERMAL SHUTDOWN
Thermal shutdown
160
Thermal shutdown hysteresis
175
°C
10
Thermal shutdown hiccup time
°C
16384
Cycles
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Minimum switching frequency
Rrt = 240 kΩ (1%)
160
200
240
kHz
Switching frequency
Rrt = 100 kΩ (1%)
400
480
560
kHz
Maximum switching frequency
Rrt = 29 kΩ (1%)
1440
1600
1760
kHz
Minimum pulse width
20
RT/CLK high threshold
RT/CLK low threshold
RT/CLK falling edge to PH rising edge delay
ns
2
0.78
Measure at 500 kHz with RT resistor in series
Switching frequency range (RT mode set point and
PLL mode)
V
V
66
200
ns
1600
kHz
145
ns
PH (PH PIN)
Minimum on time
Measured at 90% to 90% of VIN, 25°C, IPH =
2A
Minimum off time
BOOT-PH ≥ 3 V
94
0
ns
BOOT (BOOT PIN)
BOOT-PH UVLO
2.1
3
V
60
mV
SLOW START AND TRACKING (SS/TR PIN)
SS charge current
SS/TR to VSENSE matching
μA
2.3
V(SS/TR) = 0.4 V
20
VSENSE falling (Fault)
POWER GOOD (PWRGD PIN)
VSENSE threshold
92
% Vref
VSENSE rising (Good)
94
% Vref
VSENSE rising (Fault)
106
% Vref
VSENSE falling (Good)
104
% Vref
Output high leakage
VSENSE = Vref, V(PWRGD) = 5.5 V
Output low
I(PWRGD) = 2 mA
Minimum VIN for valid output
V(PWRGD) < 0.5V at 100 μA
Minimum SS/TR voltage for PWRGD
6
Submit Documentation Feedback
30
0.6
100
nA
0.3
V
1
V
1.4
V
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
6.6 Typical Characteristics
40
30
VIN = 12 V
27
RDS(on) - On Resistance - mW
RDS(on) - On Resistance - mW
VIN = 12 V
35
30
25
24
21
18
20
-50
-25
0
25
50
75
TJ - Junction Temperature - °C
100
15
-50
125
Figure 1. High-side MOSFET on Resistance
vs Junction Temperature
-25
0
25
50
75
Tj - Junction Temperature - Deg
100
125
Figure 2. Low-side MOSFET on Resistance
vs Junction Temperature
485
0.606
fsw - Oscillator Frequency - kHz
Vref - Voltage Reference - V
0.604
0.602
0.6
0.598
480
475
470
0.596
0.594
-50
-25
0
25
50
75
TJ - Junction Temperature - °C
100
465
-50
125
Figure 3. Voltage Reference vs Junction Temperature
100
125
3.5
VIN = 12 V
VIN = 12 V
3.45
Hysterisis Current - mA
1.215
EN - UVLO Threshold - V
0
25
50
75
TJ - Junction Temperature - °C
Figure 4. Oscillator Frequency vs Junction Temperature
1.22
1.21
3.4
3.35
1.205
1.2
-50
-25
-25
0
25
50
75
TJ - Junction Temperature - °C
100
125
3.3
-50
Figure 5. EN Pin UVLO Threshold
vs Junction Temperature
-25
0
25
50
75
TJ - Junction Temperature - °C
100
125
Figure 6. EN Pin Hysteresis Current
vs Junction Temperature
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
7
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
Typical Characteristics (continued)
4
1.2
Shutdown Quiesent Current - mA
EN = 0 V
Pullup Current - mA
1.175
1.15
1.125
1.1
-50
TJ = 125°C
3
TJ = 25°C
TJ = -40°C
2
1
0
-25
0
25
50
75
TJ - Junction Temperature - °C
100
3
125
6
Figure 7. EN Pin Pullup Current Threshold
vs Junction Temperature
15
18
Figure 8. Shutdown Quiescent Current
vs Input Voltage
800
2.5
ISS - Slow Start charge Current - mA
Non-Switching Quiesent Current - mA
9
12
VI - Input Voltage - V
TJ = 125°C
700
TJ = 25°C
TJ = -40°C
600
500
6
9
12
VI - Input Voltage - V
15
2.3
2.2
2.1
-50
400
3
2.4
18
-25
0
25
50
75
TJ - Junction Temperature - °C
100
125
Figure 10. Slow Start Charge Current
vs Junction Temperature
Figure 9. VIN Non-Switching Operating Quiescent Current
vs Input Voltage
120
0.04
VSENSE Rising
ISS - SS Charge Current - mA
Voff - SS/TR Vsense Offset - V
VIN = 12 V
0.03
0.02
VSENSE Falling
100
VSENSE Rising
90
VSENSE Falling
0.01
-50
-25
0
25
50
75
TJ - Junction Temperature - °C
100
125
Figure 11. SS/TR Vsense Offset vs Junction Temperature
8
110
80
-50
-25
0
25
50
75
TJ - Junction Temperature - °C
100
125
Figure 12. PWRGD Threshold vs Junction Temperature
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
Typical Characteristics (continued)
120
16
TJ = 125°C
TJ = 25°C
Tonmin - Minimum Controllable On Time - ns
High-Side Current Limit Threshold - A
17
TJ = -40°C
15
14
13
12
11
3
6
9
12
VI - Input Voltage - V
100
90
80
70
-50
18
15
VIN = 12 V
110
Figure 13. High-side Current Limit Threshold
vs Input Voltage
0
25
50
75
TJ - Junction Temperature - °C
100
125
Figure 14. Minimum Controllable on Time
vs Junction Temperature
2.2
6
RT = 100 kW,
VIN = 12 V
BOOT-PH UVLO Threshold - mA
Dmin - Minimum Controllable Duty Ratio - %
-25
5
4
3
-50
-25
0
25
50
75
TJ - Junction Temperature - °C
100
125
2.1
2
-50
Figure 15. Minimum Controllable Duty Ratio
vs Junction Temperature
-25
0
25
50
75
TJ - Junction Temperature - °C
100
125
Figure 16. BOOTH-PH UVLO Threshold
vs Junction Temperature
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
9
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
7 Detailed Description
7.1 Overview
The device is a 17-V, 8-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To
improve performance during line and load transients the device implements a constant frequency, peak current
mode control which also simplifies external frequency compensation. The wide switching frequency of 200 kHz to
1600 kHz allows for efficiency and size optimization when selecting the output filter components. The switching
frequency is adjusted using a resistor to ground on the RT/CLK pin. The device also has an internal phase lock
loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the switching cycle to the falling edge
of an external system clock.
The device has been designed for safe monotonic startup into pre-biased loads. The default start up is when VIN
is typically 4.0V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage
under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to
operate with the internal pull-up current. The total operating current for the device is approximately 600μA when
not switching and under no load. When the device is disabled, the supply current is typically less than 2μA.
The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 8
amperes. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications.
The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for
the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor
voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to
recharge the boot capacitor. The device can operate at 100% duty cycle as long as the boot capacitor voltage is
higher than the preset BOOT-PH UVLO threshold which is typically 2.1V. The output voltage can be stepped
down to as low as the 0.6V voltage reference (Vref).
The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through
the VSENSE pin. The PWRGD pin is an open drain MOSFET which is pulled low when the VSENSE pin voltage
is less than 92% or greater than 106% of the reference voltage Vref and asserts high when the VSENSE pin
voltage is 94% to 104% of the Vref.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor or resistor divider should be coupled to the pin for slow start or critical
power supply sequencing requirements.
The device is protected from output overvoltage, overload and thermal fault conditions. The device minimizes
excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator.
When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning
on until the VSENSE pin voltage is lower than 104% of the Vref. The device implements both high-side MOSFET
overload protection and bidirectional low-side MOSFET overload protections which help control the inductor
current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal
shutdown trip point. The device is restarted under control of the slow start circuit automatically after the built-in
thermal shutdown hiccup time.
10
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
7.2 Functional Block Diagram
PWRGD
VIN
EN
Shutdown
Ip
Ih
Enable
Comparator
Thermal
Hiccup
PVIN PVIN
UVLO
Shutdown
UV
Shutdown
Logic
Logic
Enable
Threshold
Hiccup
Shutdown
OV
Boot
Charge
Current
Sense
Minimum Clamp
Pulse Skip
ERROR
AMPLIFIER
VSENSE
BOOT
Boot
UVLO
SS/TR
HS MOSFET
Current
Comparator
Voltage
Reference
Power Stage
& Deadtime
Control
Logic
PH
PH
Slope
Compensation
VIN
Regulator
Hiccup
Shutdown
Overload
Recovery
Oscillator
with PLL
Maximum
Clamp
LS MOSFET
Current Limit
Current
Sense
GND
GND
COMP
RT/CLK
EXPOSED THERMAL PAD
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The device uses a adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output
is converted into a current reference which compares to the high-side power switch current. When the power
switch current reaches current reference generated by the COMP voltage level the high-side power switch is
turned off and the low-side power switch is turned on.
7.3.2 Continuous Current Mode Operation (CCM)
As a synchronous buck converter, the device normally works in CCM (Continuous Conduction Mode) under all
load conditions.
7.3.3 VIN and Power VIN Pins (VIN and PVIN)
The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN
pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to
the power converter system.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
11
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
Feature Description (continued)
If tied together, the input voltage for VIN and PVIN can range from 4.5 V to 17 V. If using the VIN separately from
PVIN, the VIN pin must be between 4.5 V and 17 V, and the PVIN pin can range from as low as 1.6 V to 17 V. A
voltage divider connected to the EN pin can adjust the either input voltage UVLO appropriately. Adjusting the
input voltage UVLO on the PVIN pin helps to provide consistent power up behavior.
7.3.4 Voltage Reference
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit.
7.3.5 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Referring to the application schematic of Figure 29, start with a 10
kΩ for R6 and use Equation 1 to calculate R5. To improve efficiency at light loads consider using larger value
resistors. If the values are too high the regulator is more susceptible to noise and voltage errors from the
VSENSE input current are noticeable.
Vo - Vref
R5 =
R6
Vref
(1)
Where Vref = 0.6V
The minimum output voltage and maximum output voltage can be limited by the minimum on time of the highside MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in Minimum
Output Voltage and Bootstrap Voltage (BOOT) and Low Dropout Operation.
7.3.6 Safe Start-up into Pre-Biased Outputs
The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During
monotonic pre-biased startup, the low-side MOSFET is not allowed to sink current until the SS/TR pin voltage is
higher than 1.4 V.
7.3.7 Error Amplifier
The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to the
lower of the SS/TR pin voltage or the internal 0.6 V voltage reference. The transconductance of the error
amplifier is 1300 μA/V during normal operation. The frequency compensation network is connected between the
COMP pin and ground.
7.3.8 Slope Compensation
The device adds a compensating ramp to the switch current signal. This slope compensation prevents subharmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
7.4 Device Functional Modes
7.4.1 Enable and Adjusting Undervoltage Lockout
The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low Iq state.
The EN pin has an internal pull-up current source, allowing the user to float the EN pin for enabling the device. If
an application requires controlling the EN pin, use open drain or open collector output logic to interface with the
pin.
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150mV.
If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN, in
split rail applications, then the EN pin can be configured as shown in Figure 17, Figure 18 and Figure 19. When
using the external UVLO function it is recommended to set the hysteresis to be greater than 500mV.
12
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
Device Functional Modes (continued)
The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external
components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO
function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be
calculated using Equation 2 and Equation 3.
TPS54821
VIN
ip
ih
R1
R2
EN
Figure 17. Adjustable VIN Undervoltage Lock Out
TPS54821
PVIN
ip
ih
R1
R2
EN
Figure 18. Adjustable PVIN Undervoltage Lock Out, VIN ≥ 4.5V
TPS54821
VIN
ip
ih
R1
R2
EN
Figure 19. Adjustable VIN and PVIN Undervoltage Lock Out
æV
ö
VSTART ç ENFALLING ÷ - VSTOP
V
è ENRISING ø
R1 =
æ VENFALLING ö
Ip ç1 ÷ + Ih
VENRISING ø
è
R2 =
VSTOP
(2)
R1´ VENFALLING
- VENFALLING + R1(Ip + Ih )
(3)
Where Ih = 3.3 μA, Ip = 1.15 μA, VENRISING = 1.21 V, VENFALLING = 1.17 V
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
13
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
Device Functional Modes (continued)
7.4.2 Adjustable Switching Frequency and Synchronization (RT/CLK)
The RT/CLK pin can be used to set the switching frequency of the device in two modes.
In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of
the device is adjustable from 200 kHz to 1600 kHz by placing a maximum of 240 kΩ and minimum of 29 kΩ
respectively. In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized
to the external clock frequency with PLL.
The CLK mode overrides the RT mode. The device is able to detect the proper mode automatically and switch
from the RT mode to CLK mode.
7.4.3 Adjustable Switching Frequency (RT Mode)
To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 20. To
reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply
efficiency and minimum controllable on time should be considered.
- 0.997
Rrt(k W ) = 48000 × Fsw (kHz )
-2
(4)
RT − Resistance − kW
250
200
150
100
50
0
200
400
600
800
1000
1200
1400
1600
Fsw − Oscillator Frequency − kHz
Figure 20. RT Set Resistor vs Switching Frequency
7.4.4 Synchronization (CLK mode)
An internal Phase Locked Loop (PLL) has been implemented to allow synchronization between 200kHz and
1600kHz, and to easily switch from RT mode to CLK mode.
To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty
cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.78V and higher than 2.0V.
The start of the switching cycle is synchronized to the falling edge of RT/CLK pin.
In applications where both RT mode and CLK mode are needed, the device can be configured as shown in
Figure 21. Before the external clock is present, the device works in RT mode and the switching frequency is set
by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the
SYNC pin is pulled above the RT/CLK high threshold (2 V), the device switches from the RT mode to the CLK
mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external
clock. It is not recommended to switch from the CLK mode back to the RT mode because the internal switching
frequency drops to 100kHz first before returning to the switching frequency set by RT resistor.
14
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
Device Functional Modes (continued)
RT/CLK
mode select
TPS54821
RT/CLK
Rrt
Figure 21. Works with Both RT mode and CLK mode
7.4.5 Slow Start (SS/TR)
The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference
voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start
time. The device has an internal pull-up current source of 2.3 μA that charges the external slow start capacitor.
The calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in
Equation 5. The voltage reference (Vref) is 0.6 V and the slow start charge current (Iss) is 2.3μA.
t SS (ms) =
Css (nF) ´ Vref (V)
Iss (µA)
(5)
When the input UVLO is triggered, the EN pin is pulled below 1.21V, or a thermal shutdown event occurs the
device stops switching and enters low current operation. At the subsequent power up, when the shutdown
condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring
proper soft start behavior.
7.4.6 Power Good (PWRGD)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 104% of the internal
voltage reference the PWRGD pin pull-down is de-asserted and the pin floats. It is recommended to use a pullup resistor between the values of 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a
defined state once the VIN input voltage is greater than 1V but with reduced current sinking capability. The
PWRGD achieves full current sinking capability once the VIN input voltage is above 4.5 V.
The PWRGD pin is pulled low when VSENSE is lower than 92% or greater than 106% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN
pin is pulled low or the SS/TR pin is below 1.4 V.
7.4.7 Bootstrap Voltage (BOOT) and Low Dropout Operation
The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH
pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT
pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor
should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher
is recommended because of the stable characteristics over temperature and voltage.
To improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than the BOOT-PH UVLO threshold which is typically 2.1 V. When the voltage between BOOT
and PH drops below the BOOT-PH UVLO threshold the high-side MOSFET is turned off and the low-side
MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails
100% duty cycle operation can be achieved as long as (VIN – PVIN) > 4 V.
7.4.8 Sequencing (SS/TR)
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
15
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
Device Functional Modes (continued)
The sequential method is illustrated in Figure 22 using two TPS54821 devices. The power good of the first
device is coupled to the EN pin of the second device which enables the second power supply once the primary
supply reaches regulation.
TPS54821
TPS54821
PWRGD
EN
EN
SS/TR
SS/TR
PWRGD
Figure 22. Sequential Start Up Sequence
Figure 23 shows the method implementing ratio-metric sequencing by connecting the SS/TR pins of two devices
together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start
time the pull-up current source must be doubled in Equation 5.
TPS54821
EN
SS/TR
PWRGD
TPS54821
EN
SS/TR
PWRGD
Figure 23. Ratio-metric Start Up Sequence
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 24 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the Vout2
slightly before, after or at the same time as Vout1. Equation 8 is the voltage difference between Vout1 and
Vout2.
To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2
reaches regulation, use a negative number in Equation 6 and Equation 7 for deltaV. Equation 8 results in a
positive number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is
achieved. .
The deltaV variable is zero volt for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
VSENSE offset (Vssoffset, 29mV) in the slow start circuit and the offset created by the pull-up current source
(Iss, 2.3 μA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations.
To ensure proper operation of the device, the calculated R1 value from Equation 6 must be greater than the
value calculated in Equation 9.
R1 =
16
Vout2 + D V
Vssoffset
´
Vref
Iss
(6)
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
Device Functional Modes (continued)
Vref ´ R1
Vout2 + DV - Vref
DV = Vout1 - Vout2
R1 > 2800 ´ Vout1- 180 ´ DV
R2 =
(7)
(8)
(9)
TPS54821
EN
VOUT1
SS/TR
PWRGD
TPS54821
EN
VOUT 2
R1
SS/TR
R2
PWRGD
R4
R3
Figure 24. Ratio-metric and Simultaneous Startup Sequence
7.4.9 Output Overvoltage Protection (OVP)
The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier demands maximum output current. Once the condition is
removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some
applications with small output capacitance, the power supply output voltage can respond faster than the error
amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by
comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP
threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output
overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to
turn on at the next clock cycle.
7.4.10 Overcurrent Protection
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
High-side MOSFET overcurrent protection
The device implements current mode control which uses the COMP pin voltage to control the turn off of the highside MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current
and the current reference generated by the COMP pin voltage are compared, when the peak switch current
intersects the current reference the high-side switch is turned off.
Low-side MOSFET overcurrent protection
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
17
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
Device Functional Modes (continued)
While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current is exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart
after the hiccup time of 16384 cycles. The hiccup mode helps to reduce the device power dissipation under
severe overcurrent conditions.
7.4.11 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C typically. Once the junction temperature drops below 165°C typically, the internal thermal hiccup timer will
start to count. The device reinitiates the power up sequence after the built-in thermal shutdown hiccup time
(16384 cycles) is over.
7.4.12 Small Signal Model for Loop Response
Figure 25 shows an equivalent model for the device control loop which can be modeled in a circuit simulation
program to check frequency response and transient responses. The error amplifier is a transconductance
amplifier with a gm of 1300μA/V. The error amplifier can be modeled using an ideal voltage controlled current
source. The resistor Roea (3.07 MΩ) and capacitor Coea (20.7 pF) model the open loop gain and frequency
response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the
control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of
the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the
overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the
appropriate load step amplitude and step rate in a time domain analysis.
PH
VOUT
Power Stage
21 A/V
a
b
c
0.6 V
R3 Coea
C2
R1
RESR
VSENSE
CO
COMP
C1
Roea
gm
1300 mA/V
RL
R2
Figure 25. Small Signal Model for Loop Response
7.4.13 Simple Small Signal Model for Peak Current Mode Control
Figure 26 is a simple small signal model that can be used to understand how to design the frequency
compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle
modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is
shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in Figure 25) is the power stage
transconductance (gmps) which is 21 A/V for the device. The DC gain of the power stage is the product of gmps
18
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
Device Functional Modes (continued)
and the load resistance, R L, as shown in Equation 11 with resistive loads. As the load current increases, the DC
gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole
moves with load current (see Equation 12). The combined effect is highlighted by the dashed line in Figure 27.
As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
frequency the same for the varying load conditions which makes it easier to design the frequency compensation.
VOUT
VC
RESR
RL
gm ps
CO
Figure 26. Simplified Small Signal Model for Peak Current Mode Control
VOUT
Adc
VC
RESR
fp
RL
gm ps
CO
fz
Figure 27. Simplified Frequency Response for Peak Current Mode Control
æ
ç1+
2p
VOUT
= Adc ´ è
VC
æ
ç1+
è 2p
ö
s
÷
´ ¦z ø
ö
s
÷
´ ¦p ø
(10)
Adc = gmps ´ RL
¦p =
¦z =
(11)
1
C O ´ R L ´ 2p
(12)
1
CO ´ RESR ´ 2p
(13)
Where
gmea is the GM amplifier gain ( 1300μA/V)
gmps is the power stage gain (21A/V).
RL is the load resistance
CO is the output capacitance.
RESR is the equivalent series resistance of the output capacitor.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
19
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
Device Functional Modes (continued)
7.4.14 Small Signal Model for Frequency Compensation
The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly
used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 28. In
Type 2A, one additional high frequency pole, C6, is added to attenuate high frequency noise. In Type III, one
additional capacitor, C11, is added to provide a phase boost at the crossover frequency. See Designing Type III
Compensation for Current Mode Step-Down Converters (SLVA352) for a complete explanation of Type III
compensation.
The design guidelines below are provided for advanced users who prefer to compensate using the general
method. The below equations only apply to designs whose ESR zero is above the bandwidth of the control loop.
This is usually true with ceramic output capacitors. See the Application Information section for a step-by-step
design procedure using higher ESR output capacitors with lower ESR zero frequencies.
VOUT
C11
R8
Type 3
VSENSE
COMP Type 2A
Vref
R9
gm ea
Roea
R4
Coea
C6
Type 2B
R4
C4
C4
Figure 28. Types of Frequency Compensation
The general design guidelines for device loop compensation are as follows:
1. Determine the crossover frequency, fc. A good starting point is 1/10th of the switching frequency, fsw.
2. R4 can be determined by:
2p ´ ¦ c ´ VOUT ´ Co
R4 =
gmea ´ Vref ´ gmps
(14)
Where:
gmea is the GM amplifier gain (1300μA/V)
gmps is the power stage gain (21A/V)
Vref is the reference voltage (0.6V)
æ
ö
1
ç ¦p =
÷
CO ´ RL ´ 2p ø
3. Place a compensation zero at the dominant pole: è
C4 can be determined by:
R ´ Co
C4 = L
R4
(15)
4. C6 is optional. It can be used to cancel the zero from the ESR (Equivalent Series Resistance) of the output
capacitor Co.
´ Co
R
C6 = ESR
R4
(16)
5. Type III compensation can be implemented with the addition of one capacitor, C11. This allows for slightly
higher loop bandwidths and higher phase margins. If used, C11 is calculated from Equation 17.
1
C11 =
(2 × p × R8 × fc )
(17)
20
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54821 is a highly-integrated, synchronous step-down dc-dc converter. The device is used to convert a
higher dc input voltage to a lower dc output voltage with a minimum output current of 8 A.
8.2 Typical Application
PULL UP VOLTAGE
R4
100k
R3
100k
U1
TPS54821RHL
1
2
3
VIN = 8 - 17 V
4
VIN
5
C1
6
10uF
7
PWRGD
PWRGD
RT/CLK
GND
BOOT
GND
PH
PVIN
PH
PVIN
EN
VIN
SS/TR
V_SNS
COMP
V_SNS
PWPD
15
R1
35.7k
EN
14
0.1uF
C3
13
L1 3.3 uH
11
10
EN
9
C7
C8
47uF
47uF
R6
0
8
C9
R5
4.64k
C4
C2
VOUT = 3.3 V, 8 A
VOUT
12
3900pF
470pF
R7
10.0k
C5
39pF
V_SNS
C6
R8
2.21k
0.022uf
4.7uF
R2
8.06k
Figure 29. Typical Application Circuit
8.2.1 Design Parameters
This example details the design of a high frequency switching regulator design using ceramic output capacitors.
A few parameters must be known in order to start the design process. These parameters are typically determined
at the system level. For this example, use the parameters shown in Table 1.
Table 1. Design Parameters
PARAMETER
VALUE
Output Voltage
3.3 V
Output Current
8A
Transient Response 4 A load step
ΔVout = 7 %
Input Voltage
12 V nominal, 8 V to 17 V
Output Voltage Ripple
33 mV p-p
Start Input Voltage (Rising Vin)
6.528 V
Stop Input Voltage (Falling Vin)
6.193 V
Switching Frequency
480 kHz
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
21
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
8.2.2 Design Guide – Step-By-Step Design Procedure
8.2.2.1 Typical Application Schematic
The application schematic of Figure 29 was developed to meet the requirements above. This circuit is available
as the TPS54821EVM-049 evaluation module. The design procedure is given in this section. For more
information about Type II and Type III frequency compensation circuits, see Designing Type III Compensation for
Current Mode Step-Down Converters (SLVA352) and Design Calculator (SLVC219).
8.2.2.2 Operating Frequency
The first step is to decide on a switching frequency for the regulator. There is a trade off between higher and
lower switching frequencies. Higher switching frequencies may produce smaller a solution size using lower
valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency.
However, the higher switching frequency causes extra switching losses, which hurt the converter’s efficiency and
thermal performance. In this design, a moderate switching frequency of 480 kHz is selected to achieve both a
small solution size and a high efficiency operation.
8.2.2.3 Output Inductor Selection
To calculate the value of the output inductor, use Equation 18. KIND is a coefficient that represents the amount
of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the
output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor
since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In
general, the inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3
for the majority of applications.
L1 =
Vinm ax - Vout
Vout
×
Io × Kind
Vinm ax × f sw
(18)
For this design example, use KIND = 0.3 and the minimum inductor value is calculated to be 2.31 µH. For this
design, a larger standard value was chosen: 3.3 µH. For the output filter inductor, it is important that the RMS
current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 20 and Equation 21.
Vinmax - Vout
Vout
×
Iripple =
L1
Vinmax × f sw
(19)
ILrms = Io2 +
1 æ Vo × (Vinmax - Vo ) ö
×ç
÷
12 çè Vinmax × L1× f sw ÷ø
2
Iripple
ILpeak = Iout +
2
(20)
(21)
For this design, the RMS inductor current is 8.015 A and the peak inductor current is 8.839 A. The chosen
inductor is a Vishay IHLP4040DZER3R3M1series 3.3 µH. It has a saturation current rating of 18.6 A (-20%
inductance) and a RMS current rating of 10 A (40°C temperature rise).
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
8.2.2.4 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria
22
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change
in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be
sized to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a
tolerable amount of droop in the output voltage. Equation 22 shows the minimum output capacitance necessary
to accomplish this.
2 × DIout
Co >
f sw × DVout
(22)
Where ΔIout is the change in output current, Fsw is the regulators switching frequency and ΔVout is the
allowable change in the output voltage. For this example, the transient load response is specified as a 7%
change in Vout for a load step of 4 A. For this example, ΔIout = 4 A and ΔVout = 0.07 x 3.3 = 0.231 V. Using
these numbers gives a minimum capacitance of 72.2 μF. This value does not take the ESR of the output
capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to
ignore in this calculation.
Equation 23 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 33mV. Under this requirement,
Equation 23 yields 14.6 µF.
1
1
Co >
×
Voripple
8 × f sw
Iripple
(23)
Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 24 indicates the ESR should be less than 17.9 mΩ. In this case, the ceramic caps’ ESR is
much smaller than 17.9 mΩ.
Voripple
Resr <
Iripple
(24)
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, 2 x 47 μF 10 V X5R ceramic capacitor with 3 mΩ of ESR are used. Capacitors
generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An
output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets
specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 25 can be used to calculate
the RMS ripple current the output capacitor needs to support. For this application, Equation 25 yields 485mA.
Vout × (Vinmax - Vout )
Icorms =
12 × Vinmax × L1× f sw
(25)
8.2.2.5 Input Capacitor Selection
The TPS54821 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 µF of
effective capacitance on the PVIN input voltage pins and 4.7 µF on the Vin input voltage pin. In some
applications additional bulk capacitance may also be required for the PVIN input. The effective capacitance
includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input
voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the
TPS54821. The input ripple current can be calculated using Equation 26.
Icirms = Iout ×
Vout (Vinmin - Vout )
×
Vinmin
Vinmin
(26)
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
23
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at
least a 25 V voltage rating is required to support the maximum input voltage. For this example, one 10 μF and
one 4.7 µF 25 V capacitors in parallel have been selected as the VIN and PVIN inputs are tied together so the
TPS54821 may operate from a single supply. The input capacitance value determines the input ripple voltage of
the regulator. The input voltage ripple can be calculated using Equation 27. Using the design example values,
Ioutmax = 8 A, Cin = 14.7 μF, Fsw=480 kHz, yields an input voltage ripple of 417 mV and a RMS input ripple
current of 3.94 A.
Ioutmax × 0.25
DVin =
Cin × f sw
(27)
8.2.2.6 Slow Start Capacitor Selection
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54821 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor
value can be calculated using Equation 28. For the example circuit, the soft start time is not too critical since the
output capacitor value is 2 x 47 μF which does not require much current to charge to 3.3 V. The example circuit
has the soft start time set to an arbitrary value of 6 ms which requires a 22nF capacitor. In TPS54821, Iss is
2.3µA and Vref is 0.6V.
Tss(ms) × Iss( m A )
C6(nF) =
Vref ( V )
(28)
8.2.2.7 Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or
higher voltage rating.
8.2.2.8 Under Voltage Lockout Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R3 and R4.
R3 is connected between VIN and the EN pin of the TPS54821 and R4 is connected between EN and GND .
The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 6.528V (UVLO start or enable). After the regulator starts
switching, it should continue to do so until the input voltage falls below 6.190 V (UVLO stop or disable).
Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the
stop voltages specified the nearest standard resistor value for R3 is 35.7 kΩ and for R4 is 8.06 kΩ.
8.2.2.9 Output Voltage Feedback Resistor Selection
The resistor divider network R7 and R8 is used to set the output voltage. For the example design, 10 kΩ was
selected for R7. Using Equation 29, R8 is calculated as 2.22 kΩ. The nearest standard 1% resistor is 2.21 kΩ.
R7 × VREF
R8 =
VOUT - VREF
(29)
8.2.2.9.1 Minimum Output Voltage
Due to the internal design of the TPS54821, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Equation 30
24
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
Voutmin = Ontimemin × Fsmax (Vinmax + Ioutmin (RDS2min - RDS1min ))- Ioutmin (RL + RDS2min )
Where:
Voutmin = minimum achievable output voltage
Ontimemin = minimum controllable on-time (135 nsec maximum)
Fsmax = maximum switching frequency including tolerance
Vinmax = maximum input voltage
Ioutmin = minimum load current
RDS1min = minimum high side MOSFET on resistance (36-32 mΩ typical)
RDS2min = minimum low side MOSFET on resistance (19 mΩ typical)
RL = series resistance of output inductor
(30)
8.2.2.10 Compensation Component Selection
There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at –20 dB/decade above the modulator pole frequency. The power stage phase is 0
degrees at low frequencies and starts to fall one decade above the modulator pole frequency reaching a
minimum of –90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole
shown in Equation 31
¦ p m od =
Iout m ax
2 p ´ Vout ´ Cout
(31)
60
180d
40
120d
20
60d
-0
0d
-8.281 dB
-20
-40
Phase - Deg
Gain - dB
For the TPS54821 most circuits will have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase
loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage
transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple
approximations. It is best to use Pspice or TINA-TI to accurately model the power stage gain and phase so that a
reliable compensation circuit can be designed. That is the technique used in this design procedure. Using the
pspice model for the TPS54821, apply the values calculated previously to the output filter components of L1, C7
and C8. Set RLOAD to the appropriate value for the current value to be compensate. For this design, L1 = 3.3 µH.
C7 and C8 use the derated capacitance value of 37.6 µF, and the ESR is set to 3 mΩ. The RLOAD resistor is 3.3
V/4 A = 0.82 Ω. Now the power stage characteristic can be plotted as shown in Figure 30.
-60d
-120d
Gain - dB Phase - Degrees
-60
100Hz
1.0KHz
10KHz
Frequency
-137 deg
100KHz
-180d
1.0MHz
Figure 30. Power Stage Gain and Phase Characteristics
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
25
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
For this design, the intended crossover frequency is 80 kHz. From the power stage gain and phase plots, the
gain at 80 kHz is -8.281 dB and the phase is -137 degrees. For 60 degrees of phase margin, additional phase
boost from a feed forward capacitor in parallel with the upper resistor of the voltage set point divider will be
required. R5 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at
crossover. The required value of R5 can be calculated from Equation 32.
R5 =
- GPWRSTG
10 20
gmEA
×
Vout
VREF
(32)
To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 80 kHz.
The required value for C4 is given by Equation 33.
1
C4 =
F
2 × p × R5 × CO
10
(33)
To maximize phase gain the high frequency pole is placed one decade above the crossover frequency of 80 kHz.
The required value for C5 can be calculated from Equation 34.
1
C5 =
2 × p × R5 × FP
(34)
The feed forward capacitor C9, is used to increase the phase boost at crossover above what is normally
available from Type II compensation. It places an additional zero/pole pair located at Equation 35 and
Equation 36.
1
FZ =
2 × p × C9 × R7
(35)
1
FP =
2 × p × C9 × R7 P R8
(36)
This zero and pole pair is not independent. Once the zero location is chosen, the pole is fixed as well. For
optimum performance, the zero and pole should be located symmetrically about the intended crossover
frequency. The required value for C9 can calculated from Equation 37.
1
C9 =
VREF
2 × p × R7 × FCO ×
VOUT
(37)
For this design the calculated values for the compensation components are R5 = 4.68 kΩ ,C4 = 4290 pF, C5 =
42.9 pF and C9 = 467 pF. Using standard values, the compensation components are R5 = 4.64 kΩ ,C4 = 3900
pF, C5 = 39 pF and C9 = 470 pF.
8.2.2.11 Fast Transient Considerations
In applications where fast transient responses are important, Type III frequency compensation can be used
instead of the traditional Type II frequency compensation.
26
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
8.2.3 Application Curves
IOUT = 2 A/div
VIN = 10 V/div
2 A to 6 A load step,
slew rate = 1 A / µsec
SS/TR = 1 V/div
VOUT = 100 mV/div (ac coupled)
VOUT = 2 V/div
PWRGD = 5 V/div
Time = 100 µs/div
Time = 5 ms/div
Figure 32. STARTUP with VIN
Figure 31. Load Transient
EN = 5 V/div
VIN = 5 V/div
SS/TR = 1 V/div
VOUT = 2 V/div
VOUT = 1 V/div (1 V pre-bias)
PWRGD = 5 V/div
Time = 5 ms/div
Figure 33. STARTUP with EN
Time = 2 ms/div
Figure 34. STARTUP with PRE-BIAS
VOUT = 20 mV/div (ac coupled)
VIN = 500 mV/div (ac coupled)
PH = 5 V/div
PH = 5 V/div
Time = 1 µs/div
Time = 1 µs/div
Figure 35. Output Voltage RipplE with Full Load
Figure 36. Input Voltage RipplE with Full Load
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
27
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
1000
10000
Frequency (Hz)
0.02
−90
−120
−150
−180
1000000
100000
0.015
0.01
0.005
0
−0.005
−0.01
−0.015
IOUT = 4 A
−0.02
G001
8
9
10
Figure 37. Closed Loop ResponsE, IOUT = 4 A
12
13
14
Input Voltage (V)
15
16
17
G004
Figure 38. Line Regulation
1
10
10
VIN = 12 V
0.8
Vout
1
0.6
0.4
Output Voltage - V
Output Voltage Deviation (%)
11
0.2
0
−0.2
−0.4
−0.6
1
0.1
0.1
Ideal Vsense
Vsense
0.01
0.01
0.001
0.001
0.0001
0.0001
Vsense Voltage - V
40
30
20
10
0
−10
−20
−30
−40
−50
−60
100
180
150
120
90
60
30
0
−30
−60
Output Voltage Deviation (%)
Gain
Phase
Phase (°)
Gain (dB)
60
50
www.ti.com
−0.8
−1
0.00001
0.001
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8
Output Current (A)
G003
1
10
Track In Voltage - V
100
150
90
80
125
Efficiency (%)
TA - Maximum Ambient Temperature - °C
0.1
Figure 40. Tracking Performance
Figure 39. Load Regulation
100
75
50
0
1
2
3
4
Load Current - A
5
70
60
50
40
30
VIN = 12 V,
VOUT = 3.3 V,
Fsw = 480 kHz,
room temp, no air flow
VIN = 8 V
VIN = 12 V
VIN = 17 V
20
10
25
6
0
0
Figure 41. Maximum Ambient Temperature vs Load
Current
28
0.00001
0.01
Submit Documentation Feedback
1
2
3
4
5
Output Current (A)
6
7
8
G001
Figure 42. Efficiency vs Load Current
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
100
90
Efficiency (%)
80
PH = 10 V/div
70
60
IOUT = 10 A/div
50
40
30
10
0
0.001
VOUT = 2 V/div
VIN = 8 V
VIN = 12 V
VIN = 17 V
20
0.01
0.1
Output Current (A)
1
G002
Figure 43. Efficiency vs Output Current
Time = 20 ms/div
Figure 44. TPS54821 Hiccup Mode Current Limit
9 Power Supply Recommendations
The TPS54821 is designed to operate from an input voltage supply range between 4.5 V and 17 V. This supply
voltage must be well regulated. Power supplies must be well bypassed for proper electrical performance. This
includes a minimum of one 4.7 μF (after de-rating) ceramic capacitor, type X5R or better from PVIN to GND, and
from VIN to GND. Additional local ceramic bypass capacitance may be required in systems with small input ripple
specifications, in addition to bulk capacitance if the TPS54821 device is located more than a few inches away
from its input power supply. In systems with an auxiliary power rail available, the power stage input, PVIN, and
the analog power input, VIN, may operate from separate input supplies. See Figure 45 (layout recommendation)
for recommended bypass capacitor placement.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
29
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
10 Layout
10.1 PCB Layout Guidelines
Layout is a critical portion of good power supply design. See Figure 45 for a PCB layout example. The top layer
contains the main power traces for VIN, VOUT, and VPHASE. Also on the top layer are connections for the
remaining pins of the TPS54821 and a large top side area filled with ground. The top layer ground area should
be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor
and directly under the TPS54821 device to provide a thermal path from the exposed thermal pad land to ground.
The GND pin should be tied directly to the power pad under the IC and the power pad. For operation at full rated
load, the top side ground area together with the internal ground plane, must provide adequate heat dissipating
area. There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor
with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor
connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a
low ESR ceramic capacitor with X5R or X7R dielectric. Make sure to connect this capacitor to the quite analog
ground trace rather than the power ground trace of the PVIn bypass capacitor. Since the PH connection is the
switching node, the output inductor should be located close to the PH pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The output filter capacitor ground should use the same
power ground trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining
adequate width. The small signal components should be grounded to the analog ground path as shown. The
RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed
with minimal lengths of trace. The additional external components can be placed approximately as shown. It may
be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to
produce good results and is meant as a guideline.
Land pattern and stencil information is provided in the data sheet addendum. The dimension and outline
information is for the standard RHL (S-PVQFN-N14) package. There may be slight differences between the
provided data and actual lead frame used on the TPS54821RHL package.
30
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
10.2 Layout Example
TOPSIDE
GROUND
AREA
FREQUENCY SET RESISTOR
PVIN
INPUT
BYPASS
CAPACITOR
RT/CLK
PWRGD
GND
GND
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
BOOT
EXPOSED THERMAL
PAD AREA
PVIN
PH
PVIN
EN
VIN
SS/TR
VSENSE
PVIN
OUTPUT
INDUCTOR
PH
VOUT
PH
COMP
VIN
SLOW START
CAPACITOR
VIN
INPUT
BYPASS
CAPACITOR
FEEDBACK
RESISTORS
UVLO SET
RESISTORS
COMPENSATION
NETWORK
ANALOG GROUND TRACE
0.010 in. Diameter
Thermal VIA to Ground Plane
VIA to Ground Plane
Etch Under Component
Figure 45. PCB Layout
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
31
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
Layout Example (continued)
Figure 46. Ultra-Small PCB Layout Using TPS54821 (PMP4854-2)
10.2.1 Estimated Circuit Area
The estimated printed circuit board area for the components used in the design of Figure 29 is 0.58 in2
(374mm2). This area does not include test points or connectors.
32
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
TPS54821
www.ti.com
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
33
TPS54821
SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS54821
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS54821RHLR
ACTIVE
VQFN
RHL
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
54821
Samples
TPS54821RHLT
ACTIVE
VQFN
RHL
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
54821
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
