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TPS562200, TPS563200
SLVSCB0D – JANUARY 2014 – REVISED JUNE 2016
TPS56x200 4.5-V To 17-V Input, 2-A, 3-A Synchronous Step-Down Voltage Regulator In
6 Pin SOT-23
1 Features
3 Description
•
The TPS562200 and TPS563200 are simple, easy-touse, 2 A and 3 A synchronous step-down (buck)
converters in 6 pin SOT-23 package.
TPS562200 - 2A converter with Integrated
122 mΩ and 72 mΩ FETs
TPS563200 - 3A converter with Integrated 68 mΩ
and 39 mΩ FETs
D-CAP2™ Mode Control for Fast Transient
Response
Input Voltage Range: 4.5 V to 17 V
Output Voltage Range: 0.76 V to 7 V
650 kHz Switching Frequency
Advanced Eco-mode™ Pulse-skip
Low Shutdown Current Less than 10 µA
1% Feedback Voltage Accuracy (25°C)
Startup from Pre-Biased Output Voltage
Cycle-By-Cycle Overcurrent Limit
Hiccup-Mode Undervoltage Protection
Non-latch OVP, UVLO and TSD Protections
Fixed Soft Start: 1 ms
Create a Custom Design with WEBENCH Tools
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The devices are optimized to operate with minimum
external component counts and also optimized to
achieve low standby current.
These switch mode power supply (SMPS) devices
employ D-CAP2 mode control providing a fast
transient response and supporting both low
equivalent series resistance (ESR) output capacitors
such as specialty polymer and ultra-low ESR ceramic
capacitors
with
no
external
compensation
components.
TPS562200 and TPS563200 operate in Advanced
Eco-mode, which maintains high efficiency during
light load operation. The devices are available in a 6pin 1.6mm x 2.9mm SOT (DDC) package, and
specified from –40°C to 85°C of ambient temperature.
Device Information(1)
PART NUMBER
TPS562200
2 Applications
•
•
•
•
TPS563200
Digital TV Power Supply
High Definition Blu-ray Disc™ Players
Networking Home Terminal
Digital Set Top Box (STB)
PACKAGE
BODY SIZE (NOM)
SOT (6)
1.60mm x 2.90mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Tps562200 Efficiency
100
90
Simplified Schematic
80
TPS562200
TPS563200
CIN
EN
5
4
VOUT
VIN
SW
EN
VBST
VFB
GND
2
6
1
70
VOUT
CBST
CO
RFB1
RFB2
Efficiency (%)
3
VIN
LO
VOUT = 1.8 V
60
VOUT = 3.3 V
50
40
VOUT = 5 V
30
20
Copyright © 2016, Texas Instruments Incorporated
10
0
0.001
0.01
0.1
IOUT - Output Current (A)
1
10
C007
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS562200, TPS563200
SLVSCB0D – JANUARY 2014 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration And Functions ........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
5
6
6
7
9
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics TPS562200..........................
Typical Characteristics TPS563200..........................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagrams ..................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 13
8
Application And Implementation........................ 14
8.1 Application Information............................................ 14
8.2 Typical Applications ................................................ 14
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Custom Design with WEBENCH Tools.................
Receiving Notification of Documentation Updates
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
25
25
12 Mechanical, Packaging, And Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2015) to Revision D
Page
•
Updated the Pinout image in Pin Configuration And Functions ............................................................................................ 4
•
Changed RθJB for TPS562200 From: 3.4 To: 13.4 in Thermal Information ........................................................................... 5
•
The Adaptive On-Time Control And PWM Operation, changed text From: "proportional to the converter input
voltage, VIN, and inversely proportional to the output voltage, VO" To: "inversely proportional to the converter input
voltage, VIN, and proportional to the output voltage, VO"...................................................................................................... 12
Changes from Revision B (July 2014) to Revision C
Page
•
Changed Features From: Integrated 122 mΩ and 72 mΩ FETs ('562200) To: TPS562200 - 2A converter with
Integrated 122 mΩ and 72 mΩ FETs ..................................................................................................................................... 1
•
Changed Features From: Integrated 68-mΩ and 39-mΩ FETs ('563200) To: TPS563200 - 3A converter with
Integrated 68-mΩ and 39-mΩ FETs....................................................................................................................................... 1
•
Added Features: 650 kHz Switching Frequency .................................................................................................................... 1
•
Changed Features From: Cycle-By-Cycle Hiccup Over-current Limit To: Cycle-By-Cycle Overcurrent Limit ....................... 1
•
Added Features: Hiccup-Mode Undervoltage Protection ....................................................................................................... 1
•
Changed text in the first paragraph of the Description From: "..in SOT-23 package." To: "in 6 pin SOT-23 package."........ 1
•
Moved Storage temperature range, Tstg From: Handling Ratings To: Absolute Maximum Ratings (1) ................................... 5
•
Changed the Handling Ratings table to the ESD Ratings table ............................................................................................. 5
•
Changed the TPS562200 Thermal Information values .......................................................................................................... 5
•
Changed VOVP Description in the Electrical Characteristics From: OVP Detect (L > H) To: OVP Detect, and the TYP
value From: 125% To: 125% x Vfbth...................................................................................................................................... 6
•
Changed VUVP Description in the Electrical Characteristics From: Hiccup detect (H < L) To: Hiccup detect , and the
TYP value From: 65% To: 65% x Vfbth ................................................................................................................................. 6
•
Changed the Output Current (A) scale of Figure 7 ............................................................................................................... 7
•
Changed VOUT = 5 V To VOUT = 3.3 V in Figure 15 ............................................................................................................... 9
•
Changed the X axis From: Junction Temperature To: Ambient Temperature in Figure 16 .................................................. 9
2
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SLVSCB0D – JANUARY 2014 – REVISED JUNE 2016
•
Added a NOTE to the Application and Implementation section ........................................................................................... 14
•
Changed column heading C8 + C9 (µF) To: C5 + C6 (µF) in Table 2................................................................................. 16
•
Changed column heading C8 + C9 (µF) To: C5 + C6 + C7 (µF) in Table 2 ........................................................................ 20
Changes from Revision A (January 2014) to Revision B
Page
•
Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Device and Documentation Support section, and Mechanical, Packaging, and
Orderable Information section ............................................................................................................................................... 1
•
Changed the data sheet title From: 4.5 V to 17 V Input, 2A Synchronous Step-Down.. To: 4.5 V to 17 V Input,
2A/3A Synchronous Step-Down.. ........................................................................................................................................... 1
•
Changed device number From: TPS563209 To TPS563200 ................................................................................................ 1
•
Changed Features From: 2% Feedback Voltage Accuracy (25°C) To: 1% Feedback Voltage Accuracy (25°C).................. 1
•
Added the Timing Requirements table .................................................................................................................................. 6
•
Added Table 1 ..................................................................................................................................................................... 14
•
Changed Table 2 ................................................................................................................................................................. 16
•
Deleted sentence following Table 2 "For higher output voltages, additional phase boost can be achieved by adding
a feed forward capacitor (C7) in parallel with R2." ............................................................................................................... 16
•
Added Application Information for the TPS563200 device .................................................................................................. 20
•
Added Table 3 ..................................................................................................................................................................... 20
Changes from Original (January 2014) to Revision A
•
Page
Changed the device status From: Product Preview To: Production....................................................................................... 1
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5 Pin Configuration And Functions
DDC Package
6 Pin (SOT)
Top View
GND
1
6
VBST
SW
2
5
EN
VIN
3
4
VFB
Pin Functions
PIN
NAME
DESCRIPTION
NUMBER
GND
1
Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit.
Connect sensitive VFB to this GND at a single point.
SW
2
Switch node connection between high-side NFET and low-side NFET.
VIN
3
Input voltage supply pin. The drain terminal of high-side power NFET.
VFB
4
Converter feedback input. Connect to output voltage with feedback resistor divider.
EN
5
Enable input control. Active high and must be pulled up to enable the device.
VBST
6
Supply input for the high-side NFET gate drive circuit. Connect a 0.1µF capacitor between VBST and SW pins.
4
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SLVSCB0D – JANUARY 2014 – REVISED JUNE 2016
6 Specifications
6.1 Absolute Maximum Ratings (1)
TJ = -40°C to 150°C(unless otherwise noted)
MIN
MAX
–0.3
VBST
VBST (10 ns transient)
UNIT
19
V
–0.3
25
V
–0.3
27.5
V
VBST (vs SW)
–0.3
6.5
V
VFB
–0.3
6.5
V
–2
19
V
–3.5
21
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature range, Tstg
–55
150
°C
Input voltage range
VIN, EN
SW
SW (10 ns transient)
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TJ = -40°C to 150°C(unless otherwise noted)
VIN
Supply input voltage range
VI
Input voltage range
TA
MIN
MAX
4.5
17
VBST
–0.1
23
VBST (10 ns transient)
–0.1
26
VBST(vs SW)
–0.1
6
EN
–0.1
17
VFB
–0.1
5.5
SW
–1.8
17
SW (10 ns transient)
–3.5
20
–40
85
Operating free-air temperature
UNIT
V
V
°C
6.4 Thermal Information
THERMAL METRIC
(1)
TPS562200
TPS563200
DDC (SOT)
DDC (SOT)
(6 PINS)
(6 PINS)
RθJA
Junction-to-ambient thermal resistance
89.0
87.9
RθJCtop
Junction-to-case (top) thermal resistance
44.5
42.2
RθJB
Junction-to-board thermal resistance
13.4
13.6
ψJT
Junction-to-top characterization parameter
2.2
1.9
ψJB
Junction-to-board characterization parameter
13.2
13.3
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014–2016, Texas Instruments Incorporated
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6.5 Electrical Characteristics
TJ = -40°C to 150°C, VIN = 12V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TPS562200
230
330
TPS563200
190
290
3
10
UNIT
SUPPLY CURRENT
I(VIN)
Operating – non-switching
supply current
VIN current, TA = 25°C, EN = 5V,
VFB = 0.8 V
I(VINSDN)
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
µA
µA
LOGIC THRESHOLD
VEN(H)
EN high-level input voltage
EN
VEN(L)
EN low-level input voltage
EN
1.6
REN
EN pin resistance to GND
VEN = 12 V
V
225
450
0.6
V
900
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, IO = 10mA,
Eco-mode™ operation
VFB(TH)
VFB threshold voltage
I(VFB)
VFB input current
VFB = 0.8V, TA = 25°C
High side switch resistance
TA = 25°C, VBST – SW = 5.5 V
772
TA = 25°C, VO = 1.05 V, continuous mode operation
758
mV
765
772
mV
0
±0.1
µA
MOSFET
RDS(on)h
RDS(on)l
Low side switch resistance
TA = 25°C
TPS562200
122
mΩ
TPS563200
68
mΩ
TPS562200
72
mΩ
TPS563200
39
mΩ
CURRENT LIMIT
Iocl
Current limit
(1)
DC current, VOUT = 1.05 V, LOUT = 2.2 µF
TPS562200
2.5
3.2
4.3
A
DC current, VOUT = 1.05 V, LOUT = 1.5 µF
TPS563200
3.5
4.2
5.3
A
THERMAL SHUTDOWN
Thermal shutdown
threshold (1)
TSDN
Shutdown temperature
155
Hysteresis
°C
35
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP threshold
OVP Detect
125%
x
Vfbth
VUVP
Output Hiccup threshold
Hiccup detect
65% x
Vfbth
tHiccupOn
Hiccup On Time
Relative to soft-start time
1
ms
tHiccupOff
Hiccup Off Time
Relative to soft-start time
7
ms
UVLO
UVLO
(1)
UVLO threshold
Wake up VIN voltage
3.45
3.75
4.05
Hysteresis VIN voltage
0.13
0.32
0.55
V
Not production tested
6.6 Timing Requirements
MIN
TYP
MAX
UNIT
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
150
ns
tOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.5 V
260
310
ns
Soft-start time
Internal soft-start time, TA = 25°C
1
1.3
ms
SOFT START
tss
6
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SLVSCB0D – JANUARY 2014 – REVISED JUNE 2016
6.7 Typical Characteristics TPS562200
VIN = 12 V (unless otherwise noted).
400
Ivccsdn - Shutdown Current (µA)
6
ICC - Supply Current (µA)
350
300
250
200
150
100
50
0
5
4
3
2
1
0
±50
0
50
100
±50
150
TJ - Junction Temperature (ƒC)
0
50
100
150
TJ - Junction Temperature (ƒC)
C001
C002
EN = 0 V
Figure 2. VIN Shutdown Current vs
Junction Temperature
0.780
60
0.775
50
EN Input Current (µA)
VFB Voltage (V)
Figure 1. Supply Current vs Junction Temperature
0.770
0.765
0.760
40
30
20
10
0.755
0
0.750
±10
±50
0
50
100
0
150
TJ - Junction Temperature (ƒC)
3
6
9
12
15
18
EN Input Voltage (V)
C003
C004
IO = 1 A
Figure 3. Vfb Voltage vs Junction Temperature
100
100
90
90
80
80
70
60
VOUT = 3.3 V
50
40
VOUT = 5 V
50
40
30
20
20
10
10
0.01
0.1
IOUT - Output Current (A)
1
VOUT = 3.3 V
60
30
0
0.001
VOUT = 1.8 V
70
VOUT = 1.8 V
Efficiency (%)
Efficiency (%)
Figure 4. En Current vs En Voltage
0
0.001
10
C007
0.01
0.1
IOUT - Output Current (A)
1
10
C008
VIN = 5 V
Figure 5. Efficiency vs Output Current
Figure 6. Efficiency vs Output Current
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Typical Characteristics TPS562200 (continued)
VIN = 12 V (unless otherwise noted).
800
fSW - Switching Frequency (kHz)
IOUT - Output Current (A)
2.5
2.0
VOUT = 0.76 V to 3.3 V
1.5
VOUT = 5 V
1.0
VOUT = 7 V
0.5
0.0
VOUT = 5 V
750
VOUT = 1.8 V
VOUT = 3.3 V
700
650
VOUT = 1.2 V
600
VOUT = 1.05 V
550
500
0
25
50
75
TA - Ambient Temperature (ƒC)
4
100
6
8
10
12
14
16
VIN - Input Voltage (V)
C009
18
C010
IOUT = 500 mA
Figure 7. Output Current vs Ambient Temperature
Figure 8. Switching Frequency vs Input Voltage
fSW - Switching Frequency (kHz)
800
700
600
500
VOUT = 3.3 V
400
300
VOUT = 1.8 V
200
100
0
0.01
VOUT = 1.05 V
0.10
1.00
10.00
IO - Output Current (A)
C011
Figure 9. Switching Frequency vs Output Current
8
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SLVSCB0D – JANUARY 2014 – REVISED JUNE 2016
6.8 Typical Characteristics TPS563200
VIN = 12 V (unless otherwise noted).
400
6
IVCCSHDN - Supply Current (PA)
ICC - Supply Current (PA)
350
300
250
200
150
100
50
0
-50
-25
0
25
50
Junction Temperature (qC)
75
5
4
3
2
1
0
-50
100
-25
0
25
50
Junction Temperature (qC)
D037
75
100
D038
EN = 0 V
Figure 10. Supply Current vs Junction Temperature
Figure 11. VIN Shutdown Current vs
Junction Temperature
60
0.780
50
EN Input Current (µA)
VFB Voltage (V)
0.775
0.770
0.765
0.760
40
30
20
10
0
0.755
±10
0.750
-50
0
-25
0
25
50
Junction Temperature (qC)
75
3
100
6
9
12
15
18
EN Input Voltage (V)
C019
D039
IO = 1 A
Figure 13. En Current vs En Voltage
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Figure 12. Vfb Voltage vs Junction Temperature
60
50
40
50
40
30
30
20
20
VOUT = 5V
VOUT = 3.3V
VOUT = 1.8V
10
0
0.001
60
0.01 0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
VOUT = 3.3 V
VOUT = 1.8 V
10
2 3 45
0
0.001
0.01 0.02 0.05 0.1 0.2
Output Current (A)
D040
0.5
1
2 3 45
D041
VIN = 5 V
Figure 14. Efficiency vs Output Current
Figure 15. Efficiency vs Output Current
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Typical Characteristics TPS563200 (continued)
VIN = 12 V (unless otherwise noted).
800
FSW - Switching Frequency (kHz)
IO - Output Current (A)
4
3
2
1
VO = 0.76 V to 3.3 V
VO = 5 V
VO = 7 V
750
700
650
600
550
VO = 1.05 V
VO = 7 V
500
0
0
25
50
75
TA - Ambient Temperature (qC)
100
4
6
8
10
12
Input Voltage (V)
D042
14
16
18
D043
IOUT = 1 A
Figure 16. Output Current vs Ambient Temperature
Figure 17. Switching Frequency vs Input Voltage
FSW - Switching Frequency (kHz)
900
VO = 1.05 V
VO = 7 V
750
600
450
300
150
0
0.001
0.01 0.02 0.05 0.1 0.2
0.5
IO - Output Current (A)
1
2 3 45
D044
Figure 18. Switching Frequency vs Output Current
10
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7 Detailed Description
7.1 Overview
The TPS562200 and TPS563200 are 2-A and 3-A synchronous step-down converters. The proprietary DCAP2™mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer
ceramic capacitors without complex external compensation circuits. The fast transient response of D-CAP2™
mode control can reduce the output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagrams
EN 5
+
UVP
VUVP
Hiccup
Control Logic
Ref
Soft Start
SS
6
VBST
2
SW
1
GND
VREG5
UVLO
VFB 4
Voltage
Reference
VIN
Regulator
+
OVP
VOVP
3
+
+
PWM
HS
Ton
One-Shot
XCON
VREG5
TSD
OCL
threshold
LS
OCL
+
+
ZC
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Figure 19. Functional Block Diagram: TPS562200 And TPS563200
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7.3 Feature Description
7.3.1 The Adaptive On-Time Control And PWM Operation
The main control loop of the TPS562200 and TPS563200 are adaptive on-time pulse width modulation (PWM)
controller that supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive
on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component
count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at
the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, VIN, and
proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control.
7.3.2 Advanced Eco-Mode™ Control
The TPS562200 and TPS563200 are designed with Advanced Eco-mode™ to maintain high light load efficiency.
As the output current decreases from heavy load condition, the inductor current is also reduced and eventually
comes to point that its rippled valley touches zero level, which is the boundary between continuous conduction
and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor current is
detected. As the load current further decreases, the converter runs into discontinuous conduction mode. The ontime is kept almost the same as it was in the continuous conduction mode so that it takes longer time to
discharge the output capacitor with smaller load current to the level of the reference voltage. This makes the
switching frequency lower, proportional to the load current, and keeps the light load efficiency high. The transition
point to the light load operation IOUT(LL) current can be calculated in Equation 1.
IOUT(LL) =
(VIN - VOUT ) ´ VOUT
1
´
2 ´ L ´ ƒSW
VIN
(1)
7.3.3 Soft Start And Pre-Biased Soft Start
The TPS562200 and TPS563200 have an internal 1 ms soft-start. When the EN pin becomes high, the internal
soft-start function begins ramping up the reference voltage to the PWM comparator. If the output capacitor is prebiased at startup, the devices initiate switching and start ramping up only after the internal reference voltage
becomes greater than the feedback voltage VFB. This scheme ensures that the converters ramp up smoothly
into regulation point.
7.3.4 Current Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the over
current condition exists consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing
the available output current. When a switching cycle occurs where the switch current is not above the lower OCL
threshold, the counter is reset and the OCL threshold is returned to the higher value.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. Then, the device shuts down after the UVP delay time
(typically 14 µs) and re-start after the hiccup time (typically 12 ms).
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Feature Description (continued)
When the overcurrent condition is removed, the output voltage returns to the regulated value.
7.3.5 Over Voltage Protection
TPS562200 and TPS563200 detect overvoltage condition by monitoring the feedback voltage (VFB). When the
feedback voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high and
both the high-side MOSFET driver and the low-side MOSFET driver turn off. This function is non-latch operation.
7.3.6 UVLO Protection
Undervoltage lock out protection (UVLO) monitors the internal regulator voltage. When the voltage is lower than
UVLO threshold voltage, the device is shut off. This protection is non-latching.
7.3.7 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 155°C),
the device is shut off. This is a non-latch protection
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS562200 and TPS563200 can operate in their normal switching modes. Normal continuous conduction mode
(CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS562200 and TPS563200 operate
at a quasi-fixed frequency of 650 kHz.
7.4.2 Eco-Mode Operation
When the TPS562200 and TPS563200 are in the normal CCM operating mode and the switch current falls to 0
A, the TPS562200 and TPS563200 begin operating in pulse skipping eco-mode. Each switching cycle is followed
by a period of energy saving sleep time. The sleep time ends when the VFB voltage falls below the eco-mode
threshold voltage. As the output current decreases the perceived time between switching pulses increases.
7.4.3 Standby Operation
When the TPS562200 and TPS563200 are operating in either normal CCM or eco-mode, they may be placed in
standby by asserting the EN pin low.
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8 Application And Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS562200 and TPS563200 are typically used as step down converters, which convert a voltage from 4.5V
- 17V to a lower voltage. Webench software is available to aid in the design and analysis of circuits
8.2 Typical Applications
8.2.1 Tps562200 4.5-V To 17-V Input, 1.05-V Output Converter
U1
TPS562200
VIN = 4.5 V to 17 V
3
VIN
R1 10.0k
C1
10µF
C2
10µF
C3
EN
5
4
VIN
SW
EN
VBST
VFB
GND
L1
2.2 uH
VOUT = 1.05 V, 2 A
2
VOUT
C4
6
1
C5
22µF
0.1µF
C6
22µF
R2
3.74k
R3
10.0k
Not Installed
Copyright © 2016, Texas Instruments Incorporated
Figure 20. Tps562200 1.05v/2a Reference Design
8.2.1.1
Design Requirements
To begin the design process, the user must know a few application parameters:
Table 1. Design Parameters
PARAMETER
VALUE
Input voltage range
4.5 V to 17 V
Output voltage
1.05 V
Output current
2A
Output voltage ripple
20 mVpp
8.2.1.2 Detailed Design Procedures
8.2.1.2.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance,
– Run thermal simulations to understand the thermal performance of your board,
– Export your customized schematic and layout into popular CAD formats,
– Print PDF reports for the design, and share your design with colleagues.
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8.2.1.2.2 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
æ R2 ö
VOUT = 0.765 ´ ç 1 +
÷
è R3 ø
(2)
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8.2.1.2.3 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
FP =
2p LOUT ´ COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off
at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1.
Table 2. TPS562200 Recommended Component Values
Output Voltage (V)
R2 (kΩ)
R3 (kΩ)
L1(uH)
MIN
TYP
MAX
C5 + C6 (µF)
1
3.09
10.0
1.5
2.2
4.7
20 - 68
1.05
3.74
10.0
1.5
2.2
4.7
20 - 68
1.2
5.76
10.0
1.5
2.2
4.7
20 - 68
1.5
9.53
10.0
1.5
2.2
4.7
20 - 68
1.8
13.7
10.0
1.5
2.2
4.7
20 - 68
2.5
22.6
10.0
2.2
3.3
4.7
20 - 68
3.3
33.2
10.0
2.2
3.3
4.7
20 - 68
5
54.9
10.0
3.3
4.7
4.7
20 - 68
6.5
75
10.0
3.3
4.7
4.7
20 - 68
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
ƒSW.
Use 650 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
VIN(MAX) - VOUT
VOUT
´
IlP -P =
VIN(MAX)
LO ´ ƒSW
(4)
IlPEAK = IO +
IlP -P
2
ILO(RMS) = IO2 +
(5)
1
IlP -P2
12
(6)
For this design example, the calculated peak current is 2.34 A and the calculated RMS current is 2.01 A. The
inductor used is a TDK CLF7045T-2R2N with a peak current rating of 5.5-A and an RMS current rating of 4.3-A
The capacitor value and ESR determines the amount of output voltage ripple. The device is intended for use with
ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
ICO(RMS) =
VOUT ´ (VIN - VOUT )
12 ´ VIN ´ LO ´ ƒSW
(7)
For this design two TDK C3216X5R0J226M 22 µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.
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8.2.1.2.4 Input Capacitor Selection
The device requires an input decoupling capacitor and a bulk capacitor is needed depending on the application.
A ceramic capacitor over 10 µF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor(C3)
from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage rating needs
to be greater than the maximum input voltage.
8.2.1.2.5 Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
8.2.1.3 Application Curves
60
50
40
30
60
50
40
30
20
20
VIN = 5V
VIN = 12V
10
0
0
0.5
1
Output Current (A)
1.5
VIN = 5V
VIN = 12V
10
0
0.001
2
Figure 21. Tps562200 Efficiency
0.5
1
2 3 45
D033
Figure 22. Tps562200 Light Load Efficiency
1
1
0.8
0.8
0.6
0.6
Load Regulation (%)
Load Regulation (%)
0.01 0.02 0.05 0.1 0.2
Output Current (A)
D032
0.4
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
0
0.5
1
Output Current (A)
1.5
2
0
0.5
D034
Figure 23. Tps562200 Load Regulation, VI = 5 V
1
Output Current (A)
1.5
2
D034
Figure 24. Tps562200 Load Regulation, VI = 12 V
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0.5
IO = 2 A
0.4
VI = 100 mV / div (ac coupled)
Line Regulation (%)
0.3
0.2
0.1
0
SW = 5 V / div
-0.1
-0.2
-0.3
-0.4
-0.5
4
6
8
10
12
Input Voltage (V)
14
16
18
Time = 1 µsec / div
D036
Figure 25. Tps562200 Line Regulation
Figure 26. Tps562200 Input Voltage Ripple
IO = 10 mA
VO = 20 mV / div (ac coupled)
IO = 250 mA
VO = 20 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 1 µsec / div
Time = 20 µsec / div
Figure 27. Tps562200 Output Voltage Ripple
Figure 28. Tps562200 Output Voltage Ripple
IO = 2 A
VO = 20 mV / div (ac coupled)
VO = 20 mV / div (ac coupled)
IO = 500 mA / div
SW = 5 V / div
Load step = 0.5 A - 1.5 A
Slew rate = 500 mA / µsec
Time = 200 µsec / div
Time = 1 µsec / div
Figure 29. Tps562200 Output Voltage Ripple
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Figure 30. Tps562200 Transient Response
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VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
EN = 10 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 2 msec / div
Time = 2 msec / div
Figure 31. Tps562200 Start Up Relative To VI
Figure 32. Tps562200 Start Up Relative To En
VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
EN = 10 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 2 msec / div
Time = 2 msec / div
Figure 33. Tps562200 Shut Down Relative To VI
Figure 34. Tps562200 Shut Down Relative To En
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8.2.2 Tps563200 4.5-V To 17-V Input, 1.05-V Output Converter
U1
TPS563200
3
VIN
R1 10.0k
C1
10µF
L1
1.5 uH
VOUT = 1.05 V, 3 A
VIN = 4.5 V to 17 V
C2
10µF
C3 EN
0.1µF
5
4
VIN
SW
EN
VBST
VFB
GND
2
VOUT
C4
6
1
C5
22µF
0.1µF
C6
22µF
C7
22µF
R2
3.74k
R3
10.0k
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Figure 35. Tps563200 1.05v/3a Reference Design
8.2.2.1
Design Requirements
To begin the design process, the user must know a few application parameters:
Table 3. Design Parameters
PARAMETER
VALUE
Input voltage range
4.5 V to 17 V
Output voltage
1.05 V
Output current
3A
Output voltage ripple
20 mVpp
8.2.2.2 Detailed Design Procedures
The detailed design procedure for TPS563200 is the same as for TPS562200 except for inductor selection.
8.2.2.2.1 Output Filter Selection
Table 4. Tps563200 Recommended Component Values
Output Voltage (V)
R2 (kΩ)
R3 (kΩ)
L1 (µH)
MIN
TYP
MAX
C5 + C6 + C7 (µF)
1
3.09
10.0
1.0
1.5
4.7
20 - 68
1.05
3.74
10.0
1.0
1.5
4.7
20 - 68
1.2
5.76
10.0
1.0
1.5
4.7
20 - 68
1.5
9.53
10.0
1.0
1.5
4.7
20 - 68
1.8
13.7
10.0
1.5
2.2
4.7
20 - 68
2.5
22.6
10.0
1.5
2.2
4.7
20 - 68
3.3
33.2
10.0
1.5
2.2
4.7
20 - 68
5
54.9
10.0
2.2
3.3
4.7
20 - 68
6.5
75
10.0
2.2
3.3
4.7
20 - 68
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 8,
Equation 9 and Equation 10. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
ƒSW.
Use 650 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 9 and the RMS
current of Equation 10.
VIN(MAX) - VOUT
VOUT
´
IlP -P =
VIN(MAX)
LO ´ ƒSW
(8)
IlPEAK = IO +
20
IlP -P
2
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(9)
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ILO(RMS) = IO2 +
1
IlP -P2
12
(10)
For this design example, the calculated peak current is 3.505 A and the calculated RMS current is 3.014 A. The
inductor used is a TDK CLF7045T-1R5N with a peak current rating of 7.3-A and an RMS current rating of 4.9-A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS563209 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20μF to 68μF. Use Equation 6
to determine the required RMS current rating for the output capacitor. For this design three TDK
C3216X5R0J226M 22μF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current
is 0.292A and each output capacitor is rated for 4A.
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
8.2.2.3 Application Curves
60
50
40
30
60
50
40
30
20
20
VIN = 5V
VIN = 12V
10
0
0
0.5
1
1.5
2
Output Current (A)
2.5
VIN = 5V
VIN = 12V
10
0
0.001
3
Figure 36. Tps563200 Efficiency
0.5
1
2 3 45
D028
Figure 37. Tps563200 Light Load Efficiency
1
1
0.8
0.8
0.6
0.6
Load Regulation (%)
Load Regulation (%)
0.01 0.02 0.05 0.1 0.2
Output Current (A)
D027
0.4
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
0
0.5
1
1.5
2
Output Current (A)
2.5
3
0
0.5
D029
Figure 38. Tps563200 Load Regulation, VI = 5 V
1
1.5
2
Output Current (A)
2.5
3
D030
Figure 39. Tps563200 Load Regulation, VI = 12 V
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0.5
IO = 3 A
0.4
VI = 50 mV / div (ac coupled)
Line Regulation (%)
0.3
0.2
0.1
0
SW = 5 V / div
-0.1
-0.2
-0.3
-0.4
-0.5
4
6
8
10
12
Input Voltage (V)
14
16
18
Time = 1 µsec / div
D031
Figure 40. Tps563200 Line Regulation
Figure 41. Tps563200 Input Voltage Ripple
IO = 300 mA
IO = 0 mA
VO = 20 mV / div (ac coupled)
VO = 20 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 1 µsec / div
Time = 5 msec / div
Figure 42. Tps563200 Output Voltage Ripple
Figure 43. Tps563200 Output Voltage Ripple
IO = 3 A
VO = 20 mV / div (ac coupled)
VO = 50 mV / div (ac coupled)
SW = 5 V / div
IO = 1 A / div
Load step = 0.75 A - 2.25 A
Slew rate = 500 mA / µsec
Time = 200 µsec / div
Time = 1 µsec / div
Figure 44. Tps563200 Output Voltage Ripple
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Figure 45. Tps563200 Transient Response
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VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
EN = 10 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 1 msec / div
Time = 1 msec / div
Figure 46. Tps563200 Start Up Relative To VI
Figure 47. Tps563200 Start Up Relative To En
VI = 10 V / div
VI = 10 V / div
EN = 10 V / div
EN = 10 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 1 msec / div
Time = 1 msec / div
Figure 48. Tps563200 Shut Down Relative To VI
Figure 49. Tps563200 Shut Down Relative To En
9 Power Supply Recommendations
The TPS562200 and TPS563200 are designed to operate from input supply voltage in the range of 4.5V to 17V.
Buck converters require the input voltage to be higher than the output voltage for proper operation. The
maximum recommended operating duty cycle is 65%. Using that criteria, the minimum recommended input
voltage is VO / 0.65.
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10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
GND
VOUT
Additional
Vias to the
GND plane
OUTPUT
CAPACITOR
Vias to the
internal SW
node copper
BOOST
CAPACITOR
OUTPUT
INDUCTOR
GND
VBST
SW
EN
TO ENABLE
CONTROL
VFB
VIN
Vias to the
internal SW
node copper
FEEDBACK
RESISTORS
HIGH FREQUENCY
INPUT BYPASS
CAPACITOR
SW node copper
pour area on internal
or bottom layer
INPUT BYPASS
CAPACITOR
VIN
Figure 50. Typical Layout
24
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Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: TPS562200 TPS563200
TPS562200, TPS563200
www.ti.com
SLVSCB0D – JANUARY 2014 – REVISED JUNE 2016
11 Device and Documentation Support
11.1 Custom Design with WEBENCH Tools
Create a Custom Design with WEBENCH Tools
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS562200
Click here
Click here
Click here
Click here
Click here
TPS563200
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
D-CAP2, Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: TPS562200 TPS563200
Submit Documentation Feedback
25
TPS562200, TPS563200
SLVSCB0D – JANUARY 2014 – REVISED JUNE 2016
www.ti.com
12 Mechanical, Packaging, And Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: TPS562200 TPS563200
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS562200DDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
200
TPS562200DDCT
ACTIVE
SOT-23-THIN
DDC
6
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
200
TPS563200DDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
320
TPS563200DDCT
ACTIVE
SOT-23-THIN
DDC
6
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
320
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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