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TPS562219A, TPS563219A
SLVSDT2 – NOVEMBER 2016
TPS56x219A 4.5-V to 17-V Input, 2-A, 3-A Synchronous Step-Down Voltage Regulator
in 8 Pin SOT-23
1 Features
3 Description
•
The TPS562219A and TPS563219A are simple,
easy-to-use, 2-A, 3-A synchronous step-down
converters in 8 pin SOT-23 package.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
TPS562219A: 2-A Converter With Integrated
133-mΩ and 80-mΩ FETs
TPS563219A: 3-A Converter With Integrated
68-mΩ and 39-mΩ FETs
D-CAP2™ Mode Control with 650-kHz Switching
Frequency
Input Voltage Range: 4.5 V to 17 V
Output Voltage Range: 0.76 V to 7 V
650-kHz Switching Frequency
Low Shutdown Current Less than 10 µA
1% Feedback Voltage Accuracy (25°C)
Startup from Pre-Biased Output Voltage
Cycle By Cycle Overcurrent Limit
Hiccup-mode Under Voltage Protection
Non-latch OVP, UVLO and TSD Protections
Adjustable Soft Start
Power Good Output
These switch mode power supply (SMPS) devices
employ D-CAP2™ mode control providing a fast
transient response and supporting both low
equivalent series resistance (ESR) output capacitors
such as specialty polymer and ultra-low ESR ceramic
capacitors
with
no
external
compensation
components.
The devices always operate in continuous conduction
mode, which reduces the output ripple voltage in light
load compared to discontinuous conduction mode .
The TPS562219A and TPS563219A are available in
a 8-pin 1.6 × 2.9 (mm) SOT (DDF) package, and
specified from –40°C to 85°C of ambient temperature.
Device Information(1)
2 Applications
•
•
•
•
The devices are optimized to operate with minimum
external component counts and optimized to achieve
low standby current.
PART NUMBER
Digital TV Power Supply
High Definition Blu-ray Disc™ Players
Networking Home Terminal
Digital Set Top Box (STB)
TPS562219A
TPS563219A
PACKAGE
SOT (8)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
SPACER
SPACER
Simplified Schematic
TPS562219A Transient Response
TPS562219A
TPS563219A
VOUT
1
GND
2
VO = 50 mV / div (ac coupled)
VBST
8
SW
EN
7
3
VIN
VFB
6
4
PG
SS
5
VOUT
EN
VIN
IO = 500 mA / div
Load step = 0.5 A - 1.5 A
Slew rate = 500 mA / µsec
Copyright © 2016, Texas Instruments Incorporated
Time = 200 µsec / div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS562219A, TPS563219A
SLVSDT2 – NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
8
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram ......................................
Feature Description.................................................
Device Functional Modes........................................
Application and Implementation ........................ 13
10
10
10
12
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
2
DATE
REVISION
NOTES
November 2016
*
Initial release.
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SLVSDT2 – NOVEMBER 2016
5 Pin Configuration and Functions
DDF Package
8 Pin SOT
Top View
1
GND
2
SW
EN
7
3
VIN
VFB
6
4
PG
SS
5
VBST
8
Pin Functions
PIN
NAME
DESCRIPTION
NO.
GND
1
Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit. Connect
sensitive VFB to this GND at a single point.
SW
2
Switch node connection between high-side NFET and low-side NFET.
VIN
3
Input voltage supply pin. The drain terminal of high-side power NFET.
PG
4
Power good open drain output
SS
5
Soft-start control. An external capacitor should be connected to GND.
VFB
6
Converter feedback input. Connect to output voltage with feedback resistor divider.
EN
7
Enable input control. Active high and must be pulled up to enable the device.
VBST
8
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between VBST and SW pins.
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TPS562219A, TPS563219A
SLVSDT2 – NOVEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
TJ = -40°C to 150°C (unless otherwise noted)
Input voltage range
(1)
MIN
MAX
UNIT
VIN, EN
–0.3
19
V
VBST
–0.3
25
V
VBST (10 ns transient)
–0.3
27.5
V
VBST (vs SW)
–0.3
6.5
V
VFB, PG
–0.3
6.5
V
SS
–0.3
5.5
V
SW
–2
19
V
–3.5
21
V
Operating junction temperature, TJ
SW (10 ns transient)
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TJ = –40°C to 150°C (unless otherwise noted)
VIN
MIN
MAX
4.5
17
VBST
–0.1
23
VBST (10 ns transient)
–0.1
26
VBST(vs SW)
–0.1
6
EN
–0.1
17
VFB, PG
–0.1
5.5
SS
–0.1
5
SW
–1.8
17
SW (10 ns transient)
–3.5
20
–40
85
Supply input voltage range
VI
Input voltage range
TA
Operating free-air temperature
UNIT
V
V
°C
6.4 Thermal Information
TPS562219A
THERMAL METRIC (1)
TPS563219A
DDF (SOT)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
106.1
87.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.1
41.6
°C/W
RθJB
Junction-to-board thermal resistance
10.9
14.6
°C/W
ψJT
Junction-to-top characterization parameter
8.6
4.7
°C/W
ψJB
Junction-to-board characterization parameter
10.8
14.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVSDT2 – NOVEMBER 2016
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
650
900
µA
3
10
µA
SUPPLY CURRENT
IVIN
Operating – non-switching supply current
VIN current, TA = 25°C, EN = 5 V, VFB = 0.8 V
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
LOGIC THRESHOLD
VENH
EN high-level input voltage
EN
VENL
EN low-level input voltage
EN
1.6
REN
EN pin resistance to GND
VEN = 12 V
225
TA = 25°C, VO = 1.05 V
757
TA = 0°C to 85°C, VO = 1.05 V (1)
753
V
0.6
V
450
900
kΩ
765
773
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH
VFB threshold voltage
TA = -40°C to 85°C, VO = 1.05 V
IVFB
VFB input current
(1)
777
751
mV
779
VFB = 0.8V, TA = 25°C
0
±0.1
µA
MOSFET
RDS(on)h
High side switch resistance
RDS(on)l
Low side switch resistance
TA = 25°C, VBST – SW = 5.5 V, TPS562219A
133
TA = 25°C, VBST – SW = 5.5 V, TPS563219A
68
TA = 25°C, TPS562219A
80
TA = 25°C, TPS563219A
39
mΩ
mΩ
CURRENT LIMIT
IOCL
Current limit
(1)
DC current, VOUT = 1.05 V, L1 = 2.2 µH,
TPS562219A
2.5
3.2
4.3
DC current, VOUT = 1.05 V, L1 = 1.5 µH,
TPS563219A
3.5
4.2
5.3
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold (1)
Shutdown temperature
155
Hysteresis
°C
35
SOFT START
ISS
SS charge current
VSS = 1.2 V
4.2
6
7.8
85%
90%
95%
µA
POWER GOOD
VTHPG
PG threshold
IPG
PG sink current
VFB rising (Good)
VFB falling (Fault)
85%
PG = 0.5 V
0.5
1
mA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
125%x
Vfbth
VOVP
Output OVP threshold
OVP Detect
VUVP
Output UVP threshold
Hiccup detect
tHiccupOn
Hiccup Power On Time
1
tHiccupOff
Hiccup Power Off Time
7
65%x
Vfbth
cycle
UVLO
UVLO
(1)
UVLO threshold
Wake up VIN voltage
3.45
3.75
4.05
Hysteresis VIN voltage
0.13
0.32
0.55
V
Not production tested.
6.6 Timing Requirements
MIN
TYP
MAX
UNIT
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
150
tOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.5 V
260
ns
310
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6.7 Typical Characteristics
6.7.1 TPS562219A Characteristics
VIN = 12V (unless otherwise noted)
6
800
IVCCSHDN - Supply Current (µA)
ICC - Supply Current(µA)
700
600
500
400
300
200
100
0
4
3
2
1
0
±50
0
50
100
150
Junction Temperature(ƒC)
0.775
50
EN Input Current (µA)
60
0.765
0.760
150
C012
40
30
20
10
0
0.750
±10
±50
0
50
100
0
150
Junction Temperature (ƒC)
3
6
9
12
15
EN Input Voltage (V)
C013
Figure 3. VFB Voltage vs Junction Temperature
18
C014
Figure 4. EN Current vs EN Voltage
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
100
Figure 2. VIN Shutdown Current vs Junction Temperature
0.780
0.770
50
Junction Temperature (ƒC)
0.755
60
50
40
30
60
50
40
30
Vout = 5V
20
20
Vout = 3.3V
10
0
0.5
1
1.5
Output Current (A)
Figure 5. Efficiency vs Output Current
Vout = 3.3V
10
Vout = 1.8V
0
6
0
±50
C011
Figure 1. Supply Current vs Junction Temperature
VFB Voltage (V)
5
Vout = 1.8V
0
2
0
0.5
1
1.5
Output Current (A)
C015
2
C016
Figure 6. Efficiency vs Output Current (VI= 5V)
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TPS562219A Characteristics (continued)
800
Vo = 0.76V
Vo = 1.05V
Vo = 6.5V
750
FSW - Switching Frequency (kHz)
FSW - Switching Frequency (kHz)
800
700
650
600
550
500
450
400
Vo = 0.76V
Vo = 1.05V
Vo = 6.5V
750
700
650
600
550
500
450
400
4
6
8
10
12
14
16
Input Voltage (V)
Figure 7. Switching Frequency vs Input Voltage
18
0
0.5
1
1.5
Output Current (A)
C017
2
C018
Figure 8. Switching Frequency vs Output Current
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6.7.2 TPS563219A Characteristics
6
800
IVCCSHDN - Supply Current (µA)
ICC - Supply Current (µA)
700
600
500
400
300
200
100
0
4
3
2
1
0
-50
0
50
100
-50
150
Junction Temperature (ƒC)
0.775
50
EN Input Current (µA)
60
0.765
0.760
150
C020
40
30
20
10
0
0.750
±10
-50
0
50
100
150
Junction Temperature (ƒC)
0
3
6
9
12
15
EN Input Voltage (V)
C021
Figure 11. VFB Voltage vs Junction Temperature
18
C022
Figure 12. EN Current vs EN Voltage
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
100
Figure 10. VIN Shutdown Current vs Junction Temperature
0.780
0.770
50
Junction Temperature (ƒC)
0.755
60
50
40
30
60
50
40
30
Vout = 5V
20
20
Vout = 3.3V
10
Vout = 3.3V
10
Vout = 1.8V
0
Vout = 1.8V
0
0
0.5
1
1.5
2
2.5
Output Current (A)
Figure 13. Efficiency vs Output Current
8
0
C019
Figure 9. Supply Current vs Junction Temperature
VFB Voltage (V)
5
3
0
0.5
1
1.5
2
2.5
Output Current (A)
C023
3
C024
Figure 14. Efficiency vs Output Current (VI = 5V)
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TPS563219A Characteristics (continued)
800
Vo = 0.76V
Vo = 1.05V
Vo = 6.5V
750
FSW - Switching Frequency (kHz)
FSW - Switching Frequency (kHz)
800
700
650
600
550
500
450
400
Vo = 0.76V
750
Vo = 1.05V
700
Vo = 6.5V
650
600
550
500
450
400
4
6
8
10
12
14
16
18
Input Voltage (V)
Figure 15. Switching Frequency vs Input Voltage
0
0.5
1
1.5
2
2.5
Output Current (A)
C025
3
C026
Figure 16. Switching Frequency vs Output Current
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7 Detailed Description
7.1 Overview
The TPS562219A and TPS563219A are 2-A, 3-A synchronous step-down converters. The proprietary D-CAP2™
mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic
capacitors without complex external compensation circuits. The fast transient response of D-CAP2™ mode
control can reduce the output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN 7
V UVP
+
UVP
Hiccup
Control Logic
+
OVP
VOVP
3
VIN
8
VBST
2
SW
1
GND
VREG 5
Regulator
UVLO
VFB 6
SS 5
Voltage
Reference
Ref
Soft Start
SS
PWM
+
+
HS
Ton
One - Shot
XCON
VREG 5
TSD
OCL
threshold
PG 4
LS
OCL
+
+
VTHPG
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7.3 Feature Description
7.3.1 The Adaptive On-Time Control and PWM Operation
The main control loop of the TPS562219A and TPS563219A are adaptive on-time pulse width modulation (PWM)
controller that supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive
on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component
count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at
the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely
proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control.
10
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Feature Description (continued)
7.3.2 Soft Start and Pre-Biased Soft Start
The TPS562219A and TPS563219A have adjustable soft-start. When the EN pin becomes high, the SS charge
current (ISS) begins charging the capacitor which is connected from the SS pin to GND (CSS). Smooth control of
the output voltage is maintained during start up. The equation for the soft start time, TSS is shown in Equation 1.
Css ´ VFBTH ´ 0.86
Tss(ms) =
Iss
(1)
where VFBTH is 0.765 V and Iss is 6 µA.
If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.3 Power Good
The power good output, PG is an open drain output. The power good function becomes active after 1.7 times
soft-start time. When the output voltage becomes within –10% of the target value, internal comparators detect
power good state and the power good signal becomes high. If the feedback voltage goes under 15% of the target
value, the power good signal becomes low.
7.3.4 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the over
current condition exists consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing
the available output current. When a switching cycle occurs where the switch current is not above the lower OCL
threshold, the counter is reset and the OCL threshold is returned to the higher value.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device will shut down after the UVP delay time
(typically 14 µs) and re-start after the hiccup time.
When the over current condition is removed, the output voltage returns to the regulated value.
7.3.5 Over Voltage Protection
TPS562219A and TPS563219A detect over voltage condition by monitoring the feedback voltage (VFB). When
the feedback voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high
and the high-side MOSFET turns off. This function is non-latch operation.
7.3.6 UVLO Protection
Under voltage lock out protection (UVLO) monitors the internal regulator voltage. When the voltage is lower than
UVLO threshold voltage, the device is shut off. This protection is non-latching.
7.3.7 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 155°C),
the device is shut off. This is a non-latch protection.
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7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS562219A and TPS563219A can operate in their normal switching modes. Normal continuous conduction
mode (CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS562219A and
TPS563219A operate at a quasi-fixed frequency of 650 kHz.
7.4.2 Forced CCM Operation
When the TPS562209 and TPS563209 are in the normal CCM operating mode and the switch current falls below
0 A, the TPS562219A and TPS563219A begin operating in forced CCM.
7.4.3 Standby Operation
When the TPS562219A and TPS563219A are operating in either normal CCM or forced CCM, they may be
placed in standby by asserting the EN pin low.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS562219A and TPS563219A are typically used as step down converters, which convert a voltage from
4.5 V - 17 V to a lower voltage. Webench software is available to aid in the design and analysis of circuits.
8.2 Typical Application
8.2.1 Typical Application, TPS562219A
U1
TPS562219A
L1
VIN = 4.5 - 17 V
C1
0.1µF
C2
10µF
2.2uH
C5
3
VIN
C3
10µF
EN
R3 10.0k 7
VIN
VBST
VOUT
0.1µF
EN
SW
SS
VFB
PG
5
VOUT = 1.05 V, 2 A
8
GND
2
4
R4
100k
C6
22µF
C7
22µF
PG
C8
22µF
R1
3.74k
6
1
C4
8200pF
R2
10.0k
Copyright © 2016, Texas Instruments Incorporated
Figure 17. TPS562219A 1.05V/2A Reference Design
8.2.1.1 Design Requirements
For this design example, use the parameters shown in Table 1.
Table 1. Design Parameters
PARAMETER
Input voltage range
Output voltage
Output current
Output voltage ripple
VALUES
4.5 V to 17 V
1.05 V
2A
20 mVpp
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at light loads consider using larger value resistors, too high of resistance are more
susceptible to noise and voltage errors from the VFB input current are more noticeable.
R1 ö
æ
VOUT = 0.765 ´ ç 1 +
÷
è R2 ø
(2)
8.2.1.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
FP =
2p LOUT ´ COUT
(3)
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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off
at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of
Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the high
frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values
recommended in Table 2.
Table 2. TPS562219A Recommended Component Values
L1(uH)
C6 + C7 +
C8(µF)
Output Voltage (V)
R2 (kΩ)
R3 (kΩ)
1
3.09
10.0
1.5
2.2
4.7
20 - 68
1.05
3.74
10.0
1.5
2.2
4.7
20 - 68
1.2
5.76
10.0
1.5
2.2
4.7
20 - 68
1.5
9.53
10.0
1.5
2.2
4.7
20 - 68
1.8
13.7
10.0
1.5
2.2
4.7
20 - 68
2.5
22.6
10.0
2.2
3.3
4.7
20 - 68
3.3
33.2
10.0
2.2
3.3
4.7
20 - 68
5
54.9
10.0
3.3
4.7
4.7
20 - 68
6.5
75
10.0
3.3
4.7
4.7
20 - 68
MIN
TYP
MAX
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
VIN(MAX) - VOUT
VOUT
´
IlP -P =
VIN(MAX)
LO ´ ƒSW
(4)
IlPEAK = IO +
IlP -P
2
ILO(RMS) = IO2 +
(5)
1
IlP -P2
12
(6)
For this design example, the calculated peak current is 2.34 A and the calculated RMS current is 2.01 A. The
inductor used is a TDK CLF7045T-2R2N with a peak current rating of 5.5 A and an RMS current rating of 4.3 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS562219A and
TPS563219A are intended for use with ceramic or other low ESR capacitors. Recommended values range from
20 µF to 68 µF. Use Equation 7 to determine the required RMS current rating for the output capacitor.
ICO(RMS) =
VOUT ´ (VIN - VOUT )
12 ´ VIN ´ LO ´ ƒSW
(7)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.286A and each output capacitor is rated for 4A.
8.2.1.2.3 Input Capacitor Selection
The TPS562219A and TPS563219A require an input decoupling capacitor and a bulk capacitor is needed
depending on the application. A ceramic capacitor over 10 µF is recommended for the decoupling capacitor. An
additional 0.1 µF capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The
capacitor voltage rating needs to be greater than the maximum input voltage.
14
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8.2.1.2.4 Bootstrap capacitor Selection
A 0.1µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
8.2.1.3 Application Curves
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
The following application curves were generated using the application circuit of Figure 17.
60
50
40
30
60
50
40
30
20
20
VIN = 5V
VIN = 12V
10
0
0
0.5
1
Output Current (A)
1.5
VIN = 5V
VIN = 12V
10
0
0.001
2
D006
1
1
0.8
0.8
0.6
0.6
0.4
0.2
0
-0.2
-0.4
1
2 3 45
D007
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
0
0.5
1
Output Current (A)
1.5
2
0
0.5
D008
Figure 20. TPS562219A Load Regulation, VI = 5 V
1
Output Current (A)
1.5
2
D009
Figure 21. TPS562219A Load Regulation, VI = 12 V
0.5
IO = 2 A
0.4
VI = 50 mV / div (ac coupled)
0.3
Line Regulation (%)
0.5
Figure 19. TPS562219A Light Load Efficiency
Load Regulation (%)
Load Regulation (%)
Figure 18. TPS562219A Efficiency
0.01 0.02 0.05 0.1 0.2
Output Current (A)
0.2
0.1
0
SW = 5 V / div
-0.1
-0.2
-0.3
-0.4
-0.5
4
6
8
10
12
Input Voltage (V)
14
16
18
D010
Figure 22. TPS562219A Line Regulation
Time = 1 µsec / div
Figure 23. TPS562219A Input Voltage Ripple
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IO = 2 A
VO = 20 mV / div (ac coupled)
VO = 50 mV / div (ac coupled)
IO = 500 mA / div
SW = 5 V / div
Load step = 0.5 A - 1.5 A
Slew rate = 500 mA / µsec
Time = 200 µsec / div
Time = 1 µsec / div
Figure 24. TPS562219A Output Voltage Ripple
Figure 25. TPS562219A Transient Response
VI = 10V/ div
EN = 10V/ div
SS = 5V/ div
SS = 5V/ div
VO = 500mV/ div
VO = 500mV/ div
PG = 1V/ div
PG = 1V/ div
Time = 1 msec / div
Figure 26. TPS562219A Start Up Relative To VI
Time = 1 msec / div
Figure 27. TPS562219A Start Up Relative To EN
VI = 10V/ div
EN = 10V/ div
SS = 5V/ div
SS = 5V/ div
VO = 500mV/ div
VO = 500mV/ div
PG = 1V/ div
PG = 1V/ div
Time = 5 msec / div
Figure 28. TPS562219A Shut Down Relative To VI
16
Time = 5 msec / div
Figure 29. TPS562219A Shut Down Relative To EN
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8.2.2 Typical Application, TPS563219A
U1
TPS563219A
VIN = 4.5 - 17 V
3
VIN
VBST
8
R3
10.0 kΩ 7
EN
SW
2
PG
4
VFB
6
GND
1
VIN
C1
0.1 µF
C2
10 µF
C3
10 µF
EN
5
C5
L1
1.5 µH
0.1 µF
SS
C4
VOUT = 1.05 V, 3 A
VOUT
C6
22 µF
R4
100 kΩ
C7
22 µF
PG
C8
22 µF
R1
3.74 kΩ
R2
10.0 kΩ
8200 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 30. TPS563219A 1.05V/3A Reference Design
8.2.2.1
Design Requirements
For this design example, use the parameters shown in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Input voltage range
4.5 V to 17V
Output voltage
1.05V
Output current
3A
Output voltage ripple
20mVpp
8.2.2.2 Detailed Design Procedures
The detailed design procedure for TPS563219A is the same as for TPS562200 except for inductor selection.
8.2.2.2.1 Output Filter Selection
Table 4. TPS563219A Recommended Component Values
L1 (µH)
C6 + C7 + C8
(µF)
Output Voltage (V)
R2 (kΩ)
R3 (kΩ)
1
3.09
10.0
1.0
1.5
4.7
20 - 68
1.05
3.74
10.0
1.0
1.5
4.7
20 - 68
1.2
5.76
10.0
1.0
1.5
4.7
20 - 68
1.5
9.53
10.0
1.0
1.5
4.7
20 - 68
1.8
13.7
10.0
1.5
2.2
4.7
20 - 68
2.5
22.6
10.0
1.5
2.2
4.7
20 - 68
3.3
33.2
10.0
1.5
2.2
4.7
20 - 68
5
54.9
10.0
2.2
3.3
4.7
20 - 68
6.5
75
10.0
2.2
3.3
4.7
20 - 68
MIN
TYP
MAX
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 8,
Equation 9 and Equation 10. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
ƒSW.
Use 650 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 9 and the RMS
current of Equation 10.
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IlP -P =
IlPEAK
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VIN(MAX) - VOUT
VOUT
´
VIN(MAX)
LO ´ ƒSW
(8)
Il
= IO + P -P
2
ILO(RMS) = IO2 +
(9)
1
IlP -P2
12
(10)
For this design example, the calculated peak current is 3.505 A and the calculated RMS current is 3.014 A. The
inductor used is a TDK CLF7045T-1R5N with a peak current rating of 7.3-A and an RMS current rating of 4.9-A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS563209 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20 μF to 68 μF. Use Equation 6
to determine the required RMS current rating for the output capacitor. For this design, three TDK
C3216X5R0J226M 22 μF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS
current is 0.292 A and each output capacitor is rated for 4 A.
8.2.2.3 Application Curves
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
The following application curves were generated using the application circuit of Figure 30.
60
50
40
60
50
40
30
30
20
20
VIN = 5V
VIN = 12V
10
0
0.001
0
0
0.5
1
1.5
2
Output Current (A)
2.5
VIN = 5V
VIN = 12V
10
3
0.5
1
2 3 45
D002
Figure 32. TPS563219A Light Load Efficiency
1
1
0.8
0.8
0.6
0.6
Load Regulation (%)
Load Regulation (%)
Figure 31. TPS563219A Efficiency
0.4
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
0
0.5
1
1.5
2
Output Current (A)
2.5
3
0
0.5
D003
Figure 33. TPS563219A Load Regulation, VI = 5 V
18
0.01 0.02 0.05 0.1 0.2
Output Current (A)
D001
1
1.5
2
Output Current (A)
2.5
3
D004
Figure 34. TPS563219A Load Regulation, VI = 12 V
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0.5
IO = 3 A
0.4
VI = 50 mV / div (ac coupled)
Line Regulation (%)
0.3
0.2
0.1
0
SW = 5 V / div
-0.1
-0.2
-0.3
-0.4
-0.5
4
6
8
10
12
Input Voltage (V)
14
16
18
D005
Figure 35. TPS563219A Line Regulation
Time = 1 µsec / div
Figure 36. TPS563219A Input Voltage Ripple
IO = 3 A
VO = 20 mV / div (ac coupled)
VO = 50 mV / div (ac coupled)
SW = 5 V / div
IO = 1 A / div
Load step = 0.75 A - 2.25 A
Slew rate = 500 mA / µsec
Time = 1 µsec / div
Figure 37. TPS563219A Output Voltage Ripple
Time = 200 µsec / div
Figure 38. TPS563219A Transient Response
VI = 10V/ div
EN = 10V/ div
SS = 5V/ div
SS = 5V/ div
VO = 500mV/ div
VO = 500mV/ div
PG = 1V/ div
PG = 1V/ div
Time = 1 msec / div
Figure 39. TPS563219A Start Up Relative To VI
Time = 1 msec / div
Figure 40. TPS563219A Start Up Relative To EN
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VI = 10V/ div
EN = 10V/ div
SS = 5V/ div
SS = 5V/ div
VO = 500mV/ div
VO = 500mV/ div
PG = 1V/ div
PG = 1V/ div
Time = 5 msec / div
Figure 41. TPS563219A Shut Down Relative To VI
20
Time = 5 msec / div
Figure 42. TPS563219A Shut Down Relative To EN
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9 Power Supply Recommendations
The TPS562209 and TPS563209 are designed to operate from input supply voltage in the range of 4.5V to 17V.
Buck converters require the input voltage to be higher than the output voltage for proper operation. The
maximum recommended operating duty cycle is 65%. Using that criteria, the minimum recommended input
voltage is VO / 0.65.
10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
GND
VOUT
Additional
Vias to the
GND plane
OUTPUT
CAPACITOR
Vias to the
internal SW
node copper
BOOST
CAPACITOR
OUTPUT
INDUCTOR
GND
VBST
SW
EN
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
TPS56x219A
VIN
Vias to the
internal SW
node copper
SW node copper
pour area on internal
or bottom layer
HIGH FREQUENCY
INPUT BYPASS
CAPACITOR
INPUT BYPASS
CAPACITOR
VIN
VFB
SS
PG
SLOW START
CAPACITOR
VIA TO INTERNAL
GROUND PLANE
POWER GOOD
PG PULL UP
RESISTOR
TO PG PULL
UP VOLTAGE
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11 Device and Documentation Support
11.1 Device Support
11.2 Documentation Support
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS562219A
Click here
Click here
Click here
Click here
Click here
TPS563219A
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
D-CAP2, E2E are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS562219ADDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
2219A
TPS562219ADDFT
ACTIVE
SOT-23-THIN
DDF
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
2219A
TPS563219ADDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
3219A
TPS563219ADDFT
ACTIVE
SOT-23-THIN
DDF
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
3219A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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