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TPS65261, TPS65261-1
SLVSCD3B – DECEMBER 2013 – REVISED MAY 2014
TPS6526x 4.5V to 18V Input Voltage, 3A/2A/2A Output Current
Triple Synchronous Step-Down Converter
1 Features
3 Description
•
The TPS65261, TPS65261-1 is a monolithic triple
synchronous step-down (buck) converter with
3A/2A/2A output currents. A wide 4.5V to 18V input
supply voltage range encompasses the most
intermediate bus voltages operating off 5V, 9V, 12V
or 15V power bus. The converter, with constant
frequency peak current mode, is designed to simplify
its application while giving designers options to
optimize the system according to targeted
applications. The switching frequency of the
converters can be adjusted from 250kHz to 2MHz
with an external resistor. The 180° out-of-phase
operation between Buck1 and Buck2, 3 (Buck2 and 3
run in phase) minimizes the input filter requirements.
1
•
•
•
•
•
•
•
•
•
Operating Input Supply Voltage Range
(4.5 V to 18 V)
Feedback Reference Voltage 0.6V±1%
Maximum Continuous Output Current 3A/2A/2A
Adjustable Clock Frequency from 250kHz to
2MHz
Dedicated Enable and Soft Start Pins for Each
Buck
Automatic Power-up/Power-down Sequence
Pulse Skipping Mode (PSM) at Light Load
(TPS65261 only)
Output Voltage Power Good Indicator
Input Voltage Power Failure Indicator
Thermal Overloading Protection
2 Applications
•
•
•
•
•
•
DTV
Set Top Boxes
Home Gateway and Access Point Networks
Wireless Routers
Surveillance
POS Machine
The TPS65261, TPS65261-1 features an automatic
power sequence with connecting MODE pin to V7V
and configuring EN1/2/3 pins. The device also
features an open drain RESET signal to monitor
power down.
At light load, the TPS65261 automatically operates in
pulse skipping mode (PSM) and the TPS65261-1
operates in force continuous current mode (FCC).
PSM mode provides high efficiency by reducing
switching losses at light loads and FCC mode
reduces noise susceptibility and RF interference.
The device features overvoltage protection,
overcurrent and short-circuit protection and overtemperature protection. A power good pin asserts
when any output voltages are out of regulation.
Device Information (1)
PART NUMBER
TPS65261,
TPS65261-1
(1)
PACKAGE
BODY SIZE (NOM)
VQFN (32)
5.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
4 Typical Application
Vin
Vout1
PVINx
VIN
100
LX1
90
TPS65261
TPS65261-1
80
FB1
VDIV
LX2
Vout2
PGOOD
ENx
FB2
MODE
SSx
ROSC
Vout3
LX3
Efficiency (%)
70
RESET
60
50
40
30
20
VIN = 12 V
VOUT = 3.3 V
0
0.01
10
AGND
FB3
PGND
TPS65261
0.1
Output Load (A)
1
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65261, TPS65261-1
SLVSCD3B – DECEMBER 2013 – REVISED MAY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application ................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
5
5
5
6
8
Absolute Maximum Ratings ......................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 22
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example .................................................... 35
12 Device and Documentation Support ................. 36
12.1
12.2
12.3
12.4
12.5
Documentation Support .......................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
13 Mechanical, Packaging, and Orderable
Information ........................................................... 36
5 Revision History
Changes from Revision A (December 2013) to Revision B
Page
•
Changed all text, tables and graphics to match the new data sheet template. ..................................................................... 1
•
Changed Figure 70............................................................................................................................................................... 35
2
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Copyright © 2013–2014, Texas Instruments Incorporated
TPS65261, TPS65261-1
www.ti.com
SLVSCD3B – DECEMBER 2013 – REVISED MAY 2014
6 Pin Configuration and Functions
EN2
EN1
VDIV
VIN
PVIN1
PGND1
LX1
BST1
RHB PACKAGE
(TOP VIEW)
32
31
30
29
28
27
26
25
24
EN3
1
PGOOD
2
23
COMP1
RESET
3
22
FB1
MODE
4
21
AGND
V7V
5
20
ROSC
FB2
6
19
FB3
COMP2
7
18
COMP3
SS2
8
SS1
14
15
17
16
LX3
BST3
PVIN3
12 13
PGND3
LX2
11
PVIN2
10
PGND2
9
BST2
Thermal Pad
SS3
(There is no electric signal down bonded to thermal pad inside IC.
Exposed thermal pad must be soldered to PCB for optimal thermal performance.)
Pin Functions
PIN
DESCRIPTION
NO.
NAME
1
EN3
2
PGOOD
An open drain output, asserts low if output voltage of any buck beyond regulation range due to thermal shutdown,
over-current, under-voltage or ENx shut down.
3
RESET
Open drain power failure output signal.
4
MODE
When high, an automatic power-up/power-down sequence is provided according to states of EN1, EN2 and EN3
pins.
5
V7V
Internal LDO for gate driver and internal controller. Connect a 1µF capacitor from the pin to power ground
6
FB2
Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.
7
COMP2
Error amplifier output and Loop compensation pin for buck2. Connect a series resistor and capacitor to compensate
the control loop of buck2 with peak current PWM mode.
8
SS2
Soft-start and tracking input for buck2. An internal 5µA pull-up current source is connected to this pin. The soft-start
time can be programmed by connecting a capacitor between this pin and ground.
9
BST2
10
LX2
11
PGND2
Power ground connection of buck2. Connect PGND2 pin as close as practical to the (–) terminal of VIN2 input
ceramic capacitor.
12
PVIN2
Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic
capacitor (suggest 10µF).
13
PVIN3
Input power supply for buck3. Connect PVIN3 pin as close as practical to the (+) terminal of an input ceramic
capacitor (suggest 10µF).
14
PGND3
Power ground connection of buck3. Connect PGND3 pin as close as practical to the (–) terminal of VIN3 input
ceramic capacitor.
15
LX3
Enable for buck3. Float to enable. Can use this pin to adjust the input under-voltage lockout of buck3 with a resistor
divider.
Boot strapped supply to the high side floating gate driver in buck2. Connect a capacitor (recommend 47nF) from
BST2 pin to LX2 pin.
Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is from a
diode voltage below the ground up to PVIN2 voltage.
Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is from a
diode voltage below the ground up to PVIN3 voltage.
Copyright © 2013–2014, Texas Instruments Incorporated
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TPS65261, TPS65261-1
SLVSCD3B – DECEMBER 2013 – REVISED MAY 2014
www.ti.com
Pin Functions (continued)
PIN
DESCRIPTION
NO.
NAME
16
BST3
17
SS3
Soft-start and tracking input for buck3. An internal 5µA pull-up current source is connected to this pin. The soft-start
time can be programmed by connecting a capacitor between this pin and ground.
18
COMP3
Error amplifier output and Loop compensation pin for buck3. Connect a series resistor and capacitor to compensate
the control loop of buck3 with peak current PWM mode.
19
FB3
20
ROSC
Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency.
21
AGND
Analog ground common to buck controllers and other analog circuits. It must be routed separately from high current
power grounds to the (–) terminal of bypass capacitor of input voltage VIN.
22
FB1
23
COMP1
Error amplifier output and Loop compensation pin for buck1. Connect a series resistor and capacitor to compensate
the control loop of buck1 with peak current PWM mode.
24
SS1
Soft-start and tracking input for buck1. An internal 5µA pull-up current source is connected to this pin. The soft-start
time can be programmed by connecting a capacitor between this pin and ground.
25
BST1
26
LX1
27
PGND1
Power ground connection of Buck1. Connect PGND1 pin as close as practical to the (–) terminal of VIN1 input
ceramic capacitor.
28
PVIN1
Input power supply for buck1. Connect PVIN1 pin as close as practical to the (+) terminal of an input ceramic
capacitor (suggest 10µF).
Boot strapped supply to the high side floating gate driver in buck3. Connect a capacitor (recommend 47nF) from
BST3 pin to LX3 pin.
Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider.
Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider.
Boot strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47nF) from
BST1 pin to LX1 pin.
Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a
diode voltage below the ground up to PVIN1 voltage.
29
VIN
30
VDIV
Buck controller power supply.
Input voltage threshold for power failure detection of input voltage.
31
EN1
Enable for buck1. Float to enable. Can use this pin to adjust the input under-voltage lockout of buck1 with a resistor
divider.
32
EN2
Enable for buck2. Float to enable. Can use this pin to adjust the input under-voltage lockout of buck2 with a resistor
divider.
PAD
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for
optimal thermal performance.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
PVIN1, PVIN2, PVIN3,VIN
–0.3
20
V
LX1, LX2, LX3 (Maximum withstand voltage transient < 20 ns)
–1.0
20
V
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively
–0.3
7
V
EN1, EN2, EN3, PGOOD, V7V, MODE, RESET, VDIV
–0.3
7
V
FB1, FB2, FB3, COMP1 , COMP2, COMP3, SS1, SS2, SS3, ROSC
–0.3
3.6
V
AGND, PGND1, PGND2, PGND3
–0.3
0.3
V
Operating junction temperature, TJ
–40
125
°C
(1)
4
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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TPS65261, TPS65261-1
www.ti.com
SLVSCD3B – DECEMBER 2013 – REVISED MAY 2014
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
MIN
MAX
UNIT
–55
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
-2000
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
-500
500
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
PVIN1, PVIN2, PVIN3,VIN
NOM
MAX
4.5
UNIT
18
V
LX1, LX2, LX3 (Maximum withstand voltage transient < 20 ns)
-0.8
18
V
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively
-0.1
6.8
V
EN1, EN2, EN3, PGOOD, V7V, MODE, RESET, VDIV
-0.1
6.3
V
FB1, FB2, FB3, COMP1 , COMP2, COMP3, SS1, SS2, SS3, ROSC
-0.1
3
V
TA
Operating junction temperature
-40
85
°C
TJ
Operating junction temperature
-40
125
°C
7.4 Thermal Information
THERMAL METRIC (1)
TPS65261
RHB (32 PINS)
RθJA
Junction-to-ambient thermal resistance
31.6
RθJC(top)
Junction-to-case (top) thermal resistance
23.4
RθJB
Junction-to-board thermal resistance
6.1
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
6.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2013–2014, Texas Instruments Incorporated
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TPS65261, TPS65261-1
SLVSCD3B – DECEMBER 2013 – REVISED MAY 2014
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7.5 Electrical Characteristics
TA = 25°C, VIN = 12 V, fSW = 600 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY VOLTAGE
VIN
Input voltage range
4.5
18
VIN rising
4
4.25
4.5
3.5
3.75
4
V
V
UVLO
VIN under-voltage lockout
VIN falling
Hysteresis
500
mV
IDDSDN
Shutdown supply current
EN1=EN2=EN3=MODE=0V
9.2
µA
EN1=EN2=EN3=5V,
FB1=FB2=FB3=0.8V
605
µA
EN1=5V, EN2=EN3=0V, FB1=0.8V
330
µA
EN2=5V, EN1=EN3=0V, FB2=0.8V
330
µA
EN3=5V, EN1=EN2=0V, FB3=0.8V
330
µA
IDDQ_NSW
IDDQ_NSW1
IDDQ_NSW2
Input quiescent current without
buck1/2/3 switching
IDDQ_NSW3
V7V
V7V LDO output voltage
IOCP_V7V
V7V LDO current limit
V7V load current=0A
6
6.3
6.6
175
V
mA
FEEDBACK VOLTAGE REFERENCE
VCOMP = 1.2 V, TJ = 25°C
0.596
0.6
0.605
V
VCOMP = 1.2 V, TJ = -40°C to 125°C
0.594
0.6
0.606
V
VFB
Feedback voltage
VLINEREG_BUCK
Line regulation-DC
IOUT1 = 1.5A, IOUT2 = 1A, IOUT3 = 1A
5V < PVINx < 18V
VLOADREG_BUCK
Load regulation-DC
IOUTx = (10–100%) × IOUTx_max
0.002
%/V
0.02
%/A
Buck1, Buck2, Buck3
VENXH
EN1/2/3 high level input voltage
1.2
1.1
1.26
V
VENXL
EN1/2/3 low level input voltage
1.15
V
IENX1
EN1/2/3 pull-up current
ENx = 1V
3.6
µA
IENX2
EN1/2/3 pull-up current
ENx = 1.5V
6.6
µA
IENhys
Hysteresis current
ISSX
Soft start charging current
TON_MIN
Minimum on time
3
4.3
µA
5
6
µA
80
100
ns
Gm_EA
Error amplifier trans-conductance
–2 µA < ICOMPX < 2 µA
300
µS
Gm_PS1/2/3
COMP1/2/3 voltage to inductor current
Gm
ILX = 0.5 A
7.4
A/V
ILIMIT1
Buck1 peak inductor current limit
4.33
5.1
6.02
A
ILIMITSOURCE1
Buck1 low side source current limit
4.3
A
ILIMITSINK1
Buck1 low side sink current limit
1.3
A
ILIMIT2/3
Buck2/3 peak inductor current limit
ILIMITSOURCE2/3
Buck2/3 low side source current limit
ILIMITSINK2/3
Buck2/3 low side sink current limit
THiccup_wait
Over current wait time
THiccup_re
Hiccup time before re-start
Rdson_HS1
Buck1 High-side switch resistance
Rdson_LS1
Buck1 low-side switch resistance
Rdson_HS2
2.6
3.1
2.7
1
3.73
A
A
A
256
cycles
8192
cycles
VIN = 12V
100
mΩ
VIN = 12V
65
mΩ
Buck2 High-side switch resistance
VIN = 12V
140
mΩ
Rdson_LS2
Buck2 low-side switch resistance
VIN = 12V
95
mΩ
Rdson_HS3
Buck3 High-side switch resistance
VIN = 12V
140
mΩ
Rdson_LS3
Buck3 low-side switch resistance
VIN = 12V
95
mΩ
6
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www.ti.com
SLVSCD3B – DECEMBER 2013 – REVISED MAY 2014
Electrical Characteristics (continued)
TA = 25°C, VIN = 12 V, fSW = 600 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD, MODE, POWER SEQUENCE
FBx under-voltage Falling
92.5
%VREF
FBx under-voltage Rising
95
%VREF
FBx over-voltage Rising
107.5
%VREF
FBx over-voltage Falling
Vth_PG
Feedback voltage threshold
105
%VREF
TDEGLITCH(PG)_F
PGOOD falling edge deglitch time
128
cycles
TRDEGLITCH(PG)_R PGOOD rising edge deglitch time
512
cycles
IPG
PGOOD pin leakage
VLOW_PG
PGOOD pin low voltage
VMODEH
MODE high level input voltage
ISINK = 1 mA
1.2
1.1
0.05
µA
0.4
V
1.26
V
VMODEL
MODE low level input voltage
1.15
V
IMODE1
MODE pull-up current
MODE = 1V
3.6
µA
IMODE2
MODE pull-up current
MODE = 1.5V
6.6
µA
Tpsdelay
Delay time between bucks at automatic
MODE = 1.5V
power sequencing mode
1024
cycles
POWER FAILURE DETECTOR
VDIVth
VDIV threshold
IVDIV
VDIV pull-up current
IVDIVhys
VDIV hysteresis current
Tdeglitch_R
RESET deglitch on the rising edge
Tdeglitch_F
RESET deglitch on the falling edge
1.18
1.23
1.26
V
VDIV = 1V
1
µA
VDIV = 1.5V
2
µA
1
µA
534
cycles
12
14
16
cycles
560
600
640
kHz
2000
kHz
OSCILLATOR
FSW
FSW_range
Switching frequency
ROSC = 73.2 kΩ
250
THERMAL PROTECTION
TTRIP_OTP
THYST_OTP
Thermal protection trip point
Copyright © 2013–2014, Texas Instruments Incorporated
Temperature rising
Hysteresis
160
°C
20
°C
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TPS65261, TPS65261-1
SLVSCD3B – DECEMBER 2013 – REVISED MAY 2014
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7.6 Typical Characteristics
100
100
90
90
80
80
70
70
60
50
PSM
1.2V
PSM Mode,
Mode, Vout
VO = =1.2
V
40
PSM
3.3V
V
PSM Mode,
Mode, VO
VO == 3.3
30
PSM
5.0V
PSM Mode,
Mode, VO
VO == 5.0
V
Efficiency (%)
Efficiency (%)
TA = 25°C, VIN = 12 V, VOUT1 = 1.2 V, VOUT2 = 3.3 V, VOUT3 = 1.8 V, fSW = 600 kHz (unless otherwise noted)
FCC
1.2V
FCC Mode,
Mode, VO
VO == 1.2
V
20
0.1
PSM
1.8V
PSM Mode,
Mode, Vout
VO = =1.8
V
40
PSM
3.3V
V
PSM Mode,
Mode, Vout
VO = =3.3
30
PSM
5.0V
PSM Mode,
Mode, Vout
VO = =5.0
V
FCC
1.8V
FCC Mode,
Mode, Vout
VO = =1.8
V
FCC
3.3V
FCC Mode,
Mode, Vout
VO = =3.3
V
10
FCC
5.0V
V
FCC Mode,
Mode, VO
VO == 5.0
0
0.01
50
20
FCC
3.3V
FCC Mode,
Mode, VO
VO == 3.3
V
10
60
FCC
5.0V
V
FCC Mode,
Mode, Vout
VO = =5.0
0
0.01
1
Output Load (A)
0.1
Figure 1. BUCK 1 Efficiency
C003
Figure 2. BUCK 2 Efficiency
1.220
3.33
1.215
3.32
1.210
Output Voltage (V)
Output Voltage (V)
1
Output Load (A)
C002
1.205
1.200
1.195
1.190
VIN=12V
VIN = 12 V
1.180
0.0
0.5
1.0
1.5
2.0
2.5
3.30
3.29
3.28
VIN=5V
VIN = 5 V
1.185
3.31
VIN=12V
VIN = 12 V
3.27
3.0
Output Load (A)
VIN=5V
VIN = 5 V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Output Load (A)
C004
VOUT = 1.2 V
C005
VOUT = 3.3 V
Figure 3. BUCK1, PSM Mode, Load Regulation
Figure 4. BUCK2, PSM Mode, Load Regulation
1.820
1.210
1.206
1.810
Output Voltage (V)
Output Voltage (V)
1.815
1.805
1.800
1.795
1.790
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Output Load (A)
VOUT = 1.8 V
Figure 5. BUCK3, PSM Mode, Load Regulation
8
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IOUT=0.1A
IOUT = 0.1 A
IOUT=1.5A
IOUT = 1.5 A
VIN=12V
VIN = 12 V
1.780
1.198
1.194
VIN=5V
VIN = 5 V
1.785
1.202
IOUT = 3.0 A
IOUT=3.0A
1.190
2.0
4
6
8
10
12
14
16
Input Voltage (V)
C006
18
C007
VOUT = 1.2 V
Figure 6. BUCK1, PSM Mode, Line Regulation
Copyright © 2013–2014, Texas Instruments Incorporated
TPS65261, TPS65261-1
www.ti.com
SLVSCD3B – DECEMBER 2013 – REVISED MAY 2014
Typical Characteristics (continued)
3.300
1.810
3.298
1.806
Output Voltage (V)
Output Voltage (V)
TA = 25°C, VIN = 12 V, VOUT1 = 1.2 V, VOUT2 = 3.3 V, VOUT3 = 1.8 V, fSW = 600 kHz (unless otherwise noted)
3.296
3.294
IOUT=0.1A
IOUT = 0.1 A
3.292
1.802
1.798
IOUT=0.1A
IOUT = 0.1 A
1.794
IOUT=1A
IOUT = 1.0 A
IOUT=1A
IOUT = 1.0 A
IOUT = 2.0 A
IOUT=2A
3.290
4
6
8
10
12
14
16
18
Input Voltage (V)
IOUT = 2.0 A
IOUT=2A
1.790
4
8
10
12
14
16
18
Input Voltage (V)
VOUT = 3.3 V
C009
VOUT = 1.8 V
Figure 7. BUCK2, PSM MODE, LINE REGULATION
Figure 8. BUCK3, PSM Mode, Line Regulation
640
0.606
Oscillator Frequency (kHz)
0.604
Voltage Reference (V)
6
C008
0.602
0.600
0.598
0.596
620
600
580
560
0.594
±50
±25
0
25
50
75
100
-50
125
Junction Temperature (C)
-25
0
25
50
75
100
Junction Temperature (°C)
C011
125
C012
ROSC = 73.2 kΩ
Figure 10. Oscillator Frequency vs Temperature
Figure 9. Voltage Reference vs Temperature
4.4
4.2
13
En Pin On Pullup ( A)
Shutdown Quiescent Current ( A)
15
11
9
4.0
3.8
3.6
3.4
7
3.2
5
3.0
±50
±25
0
25
50
75
100
125
Junction Temperature (C)
VIN = 12 V
Figure 11. Shutdown Quiescent vs Temperature
Copyright © 2013–2014, Texas Instruments Incorporated
±50
±25
0
25
50
75
100
Junction Temperature (C)
C013
VIN = 12 V
125
C014
EN = 1 V
Figure 12. EN Pin Pull-Up Current vs Temperature, EN=1.0V
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Typical Characteristics (continued)
TA = 25°C, VIN = 12 V, VOUT1 = 1.2 V, VOUT2 = 3.3 V, VOUT3 = 1.8 V, fSW = 600 kHz (unless otherwise noted)
7.4
1.28
EN Pin Threshold Raising (V)
En Pin On Pullup ( A)
7.2
7.0
6.8
6.6
6.4
6.2
6.0
1.24
1.20
1.16
1.12
±50
±25
0
25
50
75
100
Junction Temperature (C)
VIN = 12 V
125
±50
EN = 1.5 V
50
75
100
125
C016
Figure 14. EN Pin Threshold Raising vs Temperature
5.4
Soft Start Current (mA)
EN Pin Threshold Falling (V)
25
VIN = 12 V
1.23
1.19
1.15
1.11
1.07
5.2
5.0
4.8
4.6
±50
±25
0
25
50
75
100
Junction Temperature (C)
125
±50
±25
0
25
50
75
100
Junction Temperature (C)
C017
VIN = 12 V
125
C018
VIN = 12 V
Figure 15. EN Pin Threshold Falling vs Temperature
Figure 16. SS Pin Charge Current vs Temperature
3.5
High Side Current Limit (A)
5.5
High Side Current Limit (A)
0
Junction Temperature (C)
Figure 13. EN Pin Pull-Up Current vs Temperature, EN=1.5V
5.3
5.1
4.9
4.7
3.3
3.1
2.9
2.7
±50
±25
0
25
50
75
Junction Temperature (C)
100
125
Figure 17. Buck1 High-Side Current Limit vs Temperature
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±50
±25
0
25
50
75
Junction Temperature (C)
C019
VIN = 12 V
10
±25
C015
100
125
C020
VIN = 12 V
Figure 18. Buck2 High-Side Current Limit vs Temperature
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SLVSCD3B – DECEMBER 2013 – REVISED MAY 2014
Typical Characteristics (continued)
TA = 25°C, VIN = 12 V, VOUT1 = 1.2 V, VOUT2 = 3.3 V, VOUT3 = 1.8 V, fSW = 600 kHz (unless otherwise noted)
1.25
VDIV Pin Threshold (V)
High Side Current Limit (A)
3.5
3.3
3.1
2.9
2.7
1.24
1.23
1.22
1.21
±50
±25
0
25
50
75
Junction Temperature (C)
100
125
C021
±50
±25
0
25
50
75
100
Junction Temperature (C)
125
C022
VIN = 12 V
Figure 19. Buck3 High-Side Current Limit vs Temperature
Copyright © 2013–2014, Texas Instruments Incorporated
Figure 20. VDIV Pin Threshold vs Temperature
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8 Detailed Description
8.1 Overview
The TPS65261, TPS65261-1 is a monolithic triple synchronous step-down (buck) converter with 3A/2A/2A output
currents. A wide 4.5V to 18V input supply voltage range encompasses the most intermediate bus voltages
operating off 5V, 9V, 12V or 15V power bus. The feedback voltage reference for each buck is 0.6V. Each buck is
independent with dedicated enable, soft-start and loop compensation pins.
The TPS65261, TPS65261-1 implements a constant frequency, peak current mode control that simplifies
external loop compensation. The wide switching frequency of 250kHz to 2MHz allows optimizing system
efficiency, filtering size and bandwidth. The switching frequency can be adjusted with an external resistor
connected between ROSC pin and ground. The switching clock of buck1 is 180° out-of-phase operation from the
clocks of buck2 and buck3 channels to reduce input current ripple, input capacitor size and power supply induced
noise.
The TPS65261, TPS65261-1 has been designed for safe monotonic startup into pre-biased loads. The default
start up is when VIN is typically 4.5V. The ENx pin also can be used to adjust the input voltage under voltage
lockout (UVLO) with an external resistor divider. In addition, the ENx pin has an internal 3.6uA current source, so
the EN pin can be floating to automatically power up the converters.
The TPS65261, TPS65261-1 reduces the external component count by integrating a bootstrap circuit. The bias
voltage for the integrated high-side MOSFET is supplied by a capacitor between the BST and LX pin. A UVLO
circuit monitors the bootstrap capacitor voltage VBST-VLX in each buck. When VBST-VLX voltage drops to the
threshold, LX pin is pulled low to recharge the bootstrap capacitor. The TPS65261, TPS65261-1 can operate at
100% duty cycle as long as the bootstrap capacitor voltage is higher than the BOOT-LX UVLO threshold which is
typically 2.1V.
The TPS65261, TPS65261-1 features a PGOOD pin to supervise each output voltage of the buck converters.
The TPS65261, TPS65261-1 has power good comparators with hysteresis, which monitor the output voltages
through feedback voltages. When all bucks are in regulation range and power sequence is done, PGOOD is
asserted to high.
The SS (soft start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during
power up. A small value capacitor or resistor divider is connected to the pin for soft start or voltage tracking.
At light loading, TPS65261 will automatically operate in pulse skipping mode (PSM) to save power.
The TPS65261, TPS65261-1 is protected from overload and over temperature fault conditions. The converter
minimizes excessive output overvoltage transients by taking advantage of the power good comparator. When the
output is overvoltage, the high-side MOSFET is turned off until the internal feedback voltage is lower than 105%
of the 0.6V reference voltage. The TPS65261, TPS65261-1 implements both high-side MOSFET overload
protection and bidirectional low-side MOSFET overload protection to avoid inductor current runaway. If the over
current condition has lasted for more than the OC wait time (256 clock cycles), the converter will shut down and
re-start after the hiccup time (8192 clock cycles). The TPS65261, TPS65261-1 shuts down if the junction
temperature is higher than the thermal shutdown trip point. When the junction temperature drops 20°C typically
below the thermal shutdown trip point, the TPS65261, TPS65261-1 will be restarted under control of the soft start
circuit automatically.
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8.2 Functional Block Diagram
ROSC
VIN
VIN
BST1
VIN
enable
CLK2
PVIN1
clk
OSC/Phase Shift
CLK3
VIN
V7V
V3V
CLK1
V7V LDO
Bias
V7V
en_buck2
PGND1
PGND
BUCK2
SS
LX2
LX
PGND2
PGND
Comp
5 µA
vfb
Comp
5 µA
SS1
MODE
VIN
BST2
BST
MODE
BUCK1
LX
PVIN2
VIN
en_buck1
BST
LX1
V7V
clk
enable
SS
vfb
SS2
FB2
FB1
COMP1
1 µA
1 µA
VIN
COMP2
1.23 V
Power
Failure
deglitch
VDIV
RESET
PGOOD
en_buck3
Power
Good
3.6 µA
3 µA
2K
6.3 V
3.6 µA
V7V
enable
VIN
PVIN3
BUCK3
MODE
Comp
1.2 V
vfb
3 µA
LX3
LX
PGND
SS
VIN
BST3
BST
FB1
FB2
FB3
MODE
clk
PGND3
5 µA
SS3
FB3
EN1
en_buck1
6.3 V 1.2 V
2K
State
Machine
3 µA
3.6 µA
en_buck2
en_buck3
EN2
COMP3
2K
6.3 V 1.2 V
3.6 µA
OT
3 µA
Over
Temp
AGND
EN3
2K
6.3 V 1.2 V
8.3 Feature Description
8.3.1 Adjusting the Output Voltage
The output voltage of each buck is set with a resistor divider from the output of buck to the FB pin. It is
recommended to use 1% tolerance or better resistors.
Vout
R1
FB
COMP
R2
0.6 V
Figure 21. Voltage Divider Circuit
R2 = R1 ´
0.6
Vout - 0.6
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Feature Description (continued)
To improve efficiency at light loads, consider using larger value resistors. If the values are too high, the regulator
is more sensitive to noise. The recommended resistor values are shown in Table 1.
Table 1. Output Resistor Divider Selection
OUTPUT VOLTAGE
(V)
R1
(kΩ)
R2
(kΩ)
1
10
15
1.2
10
10
1.5
15
10
1.8
20
10
2.5
31.6
10
3.3
45.3
10
3.3
22.6
4.99
5
73.2
10
5
36.5
4.99
8.3.2 Power Failure Detector
The power failure detector monitors the voltage on VDIV, and sets open-drain output RESET low when VDIV is
below 1.23V. There is deglitch on the rising edge, 534 frequency cycles. Figure 22 shows the power failure
detector timing diagram.
1 µA
VIN
V7V
Threshold_r
Threshold_f
VIN
ih
1 µA
R1
1.23 V
VDIV
V7V
Power
ip
Failure
RESET
RESET
R2
Delay Time
534 Cycles
Figure 22. Power Failure Detector Timing Diagram
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The thresholds can be calculated using Equation 2 and Equation 3.
R1 ö
æ
Threshold _ r = Vref ç 1 +
÷ - Ip ´ R1
R2
è
ø
(2)
R1 ö
æ
Threshold _ f = Vref ç 1 +
÷ - (IP + Ih )´ R1
R2
è
ø
(3)
The divider resisters can be calculated using Equation 4 and Equation 5.
Threshold _ r - Threshold _ f
R1 =
Ih
(4)
Vref
R2 =
Threshold _ r - Vref
´ Ih + Ip
Threshold _ r - Threshold _ f
(5)
Where Ih = 1µA, Ip = 1µA.
8.3.3 Enable and Adjusting Under-Voltage Lockout
The EN1/2/3 pin provides electrical on/off control of the device. Once the EN1/2/3 pin voltage exceeds the
threshold voltage, the device starts operation. If each ENx pin voltage is pulled below the threshold voltage, the
regulator stops switching and enters low Iq state.
The EN pin has an internal pull-up current source, allowing the user to float the EN pin to enable the device. If an
application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin.
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 500mV. If an
application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVINx in split
rail applications, then the ENx pin can be configured as shown in Figure 23, Figure 24 and Figure 25. When
using the external UVLO function, it is recommended to set the hysteresis to be greater than 500mV.
The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external
components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO
function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be
calculated using Equation 6 and Equation 7.
æV
ö
VSTART ç ENFALLING ÷ - VSTOP
V
è ENRISING ø
R1 =
æ
ö
V
IP ç 1 - ENFALLING ÷ + Ih
VENRISING ø
è
(6)
R2 =
R1 ´ VENFALLING
VSTOP - VENFALLILNG + R1 Ih + Ip
(
)
(7)
Where Ih = 3µA, IP = 3.6uA, VENSRISING = 1.2V, VENFALLING = 1.15V.
VIN
PVIN
ih
ih
R1
R1
ip
ip
EN
EN
R2
R2
Figure 23. Adjustable VIN
Under-voltage Lockout
Copyright © 2013–2014, Texas Instruments Incorporated
Figure 24. Adjustable PVIN Under-voltage
Lockout, VIN>4.5V
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PVIN
VIN
ih
R1
ip
EN
R2
Figure 25. Adjustable VIN and PVIN Under-voltage Lockout
8.3.4 Soft-Start Time
The voltage on the respective SS pin controls the start-up of the buck output. When the voltage on the SS pin is
less than the internal 0.6V reference, the TPS65261, TPS65261-1 regulates the internal feedback voltage to the
voltage on the SS pin instead of 0.6V. The SS pin can be used to program an external soft-start function or to
allow output of the buck to track another supply during start-up. The device has an internal pull-up current source
of 5µA (typical) that charges an external soft-start capacitor to provide a linear ramping voltage at the SS pin.
The TPS65261, TPS65261-1 regulates the internal feedback voltage to the voltage on the SS pin, allowing
VOUT to rise smoothly from 0V to its regulated voltage without inrush current. The soft-start time can be
calculated approximately by Equation 8.
Css(nF) ´ Vref(V)
Tss (ms ) =
Iss(µA)
(8)
Many of the common power supply sequencing methods can be implemented using the SSx and ENx pins.
Figure 26 shows the method implementing ratio-metric sequencing by connecting the SSx pins of three buck
channels together. The regulator outputs ramp up and reach regulation at the same time. When calculating the
soft-start time, the pull-up current source must be tripled in Equation 8.
EN
31
EN threshold=1.2 V
EN1
32
EN2
1
EN3
Vout3 = 3.3 V
24
SS1
Vout2 1.8 V
8
SS2
Vout1 1.2 V
SS3
PGOOD
17
Css
PGOOD Deglitch Time
Tss = Css*0.6 V/15 µA
Figure 26. Ratio Metric Power Up Using SSx Pins
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Simultaneous power supply sequencing can be implemented by connecting capacitor to SSx pin, shown in
Figure 27. The capacitors can be calculated using Equation 8 and Equation 9.
Css1
Css2
Css3
=
=
Vout1 Vout2 Vout3
(9)
EN
31
EN1
EN threshold = 1.2 V
32
EN2
1
EN3
Vout3 = 3.3 V
24
SS1
Css1
Vout2 1.8 V
8
SS2
Css2
Vout1 1.2 V
17
SS3
PGOOD
Css3
PGOOD Deglitch Time
Tss = Css3*0.6 V/5 µA
Figure 27. Simultaneous Startup Sequence Using SSx Pins
8.3.5 Power Up Sequencing
TPS65261, TPS65261-1 features a comprehensive sequencing circuit for the 3 bucks. If the MODE pin ties high
to V7V, three buck start up and shutdown is in sequence according to different buck enable pin setup. If the
MODE pin ties low to ground, three buck on/off is separately controlled by three enable pins.
8.3.5.1 External Power Sequencing
The TPS65261, TPS65261-1 has a dedicated enable pin and soft-start pin for each converter. The converter
enable pins are biased by a current source that allows for easy sequencing with the addition of an external
capacitor. Disabling the converter with an active pull-down transistor on the ENs pin allows for a predictable
power-down timing operation. Figure 28 shows the timing diagram of a typical buck power-up sequence by
connecting a capacitor at ENx pin.
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VIN
EN Threshold
V7V
ENx Rise Time
Dictated by C EN
EN Threshold
Charge C EN
with 6.6 µA
ENx
Soft Start Rise Time
Dictated by C SS
Pre-Bias Startup
PGOOD Deglitch Time
VOUTx
T = CSS *0.6 V/5 µA
T = C EN *(1.2-0.4) V/3.6 µA
T = C EN *0.4 V/1.4 µA
PGOOD
Figure 28. Startup Power Sequence
8.3.5.2 Automatic Power Sequencing
The TPS65261, TPS65261-1 starts with a pre-defined power-up and power-down sequence when the MODE pin
ties high to V7V. As shown in Table 2, the sequence is dictated by the different combinations of EN1 and EN2
status. EN3 is used to start/stop the converters. Buck2 and buck3 are identical converters and can be swapped
in the system operation to allow for additional sequencing stages. Figure 29 shows the power sequencing when
EN1 and EN2 are pulled up high.
Table 2. Power Sequencing
Automatic Power
Sequencing
Externally
controlled
sequencing
18
MODE
EN1
EN2
High
High
High
High
Low
High
High
High
Low
High
Low
Low
Low
Used to start/stop Used to start/stop
buck1
buck2
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EN3
Used to start/stop
bucks in sequence
Start Sequencing
Shutdown Sequencing
Buck1→Buck2→Buck3
Buck3→Buck2→Buck1
Buck2→Buck1→Buck3
Buck3→Buck1→Buck2
Buck2→Buck3→Buck1
Buck1→Buck3→Buck2
Reserved
Reserved
Reserved
Used to start/stop
buck3
x
x
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VIN
V7V
MODE
EN1
EN2
EN3
Buck1
Buck2
Buck3
PGOOD
t1
t2
t3
t4
T psdelay = t1 = t2 = t3 = t4 = 1024*(1/fsw)
Figure 29. Automatic Power Sequencing
8.3.6 V7V Low Dropout Regulator and Bootstrap
Power for the high-side and low-side MOSFET drivers and most other internal circuitry is derived from the V7V
pin. The internal built-in low dropout linear regulator (LDO) supplies 6.3V (typical) from VIN to V7V. A 1µF
ceramic capacitor should be connected from V7V pin to power ground.
If the input voltage, VIN, decreases to UVLO threshold voltage, the UVLO comparator detects the V7V pin
voltage and forces the converter off.
Each high-side MOSFET driver is biased from the floating bootstrap capacitor, CB, shown in Figure 30, which is
normally recharged during each cycle through an internal low-side MOSFET or the body diode of a low-side
MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less
than VIN and BST-LX voltage is below regulation. The recommended value of this ceramic capacitor is 47nF. A
ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended
because of the stable characteristics over temperature and voltage. Each low-side MOSFET driver is powered
from the V7V pin directly.
To improve drop out, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage
is greater than the BST-LX UVLO threshold, which is typically 2.1V. When the voltage between BST and LX
drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is
turned on allowing the boot capacitor to be recharged.
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Figure 30. V7V Linear Dropout Regulator and Bootstrap Voltage Diagram
8.3.7 Out-of-Phase Operation
In order to reduce input ripple current, the switch clock of buck1 is 180° out-of-phase from the clock of buck2 and
buck3. This enables the system, having less input current ripple, to reduce the input capacitors’ size, cost and
EMI.
8.3.8 Output Overvoltage Protection (OVP)
The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot.
When the output is overloaded, the error amplifier compares the actual output voltage to the internal reference
voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output of
the error amplifier demands maximum output current. Once the condition is removed, the regulator output rises
and the error amplifier output transitions to the steady state voltage. In some applications with small output
capacitance, the load can respond faster than the error amplifier. This leads to the possibility of an output
overshoot. Each buck compares the FB pin voltage to the OVP threshold. If the FB pin voltage is greater than
the OVP threshold, the high-side MOSFET is turned off preventing current from flowing to the output and
minimizing output overshoot. When the FB voltage drops lower than the OVP threshold, the high-side MOSFET
turns on at the next clock cycle.
8.3.9 Slope Compensation
In order to prevent the sub-harmonic oscillations when the device operates at duty cycles greater than 50%, the
device adds built-in slope compensation, which is a compensating ramp to the switch current signal.
8.3.10 Overcurrent Protection
The device is protected from over current conditions with cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
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8.3.10.1 High-side MOSFET Over Current Protection
The device implements current mode control which uses the COMP pin voltage to control the turn off of the highside MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. During each cycle, the switch
current and the current reference generated by the COMP pin voltage are compared, when the peak switch
current intersects the current reference, the high-side switch is turned off.
8.3.10.2 Low-side MOSFET Over Current Protection
While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During
normal operation, the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded, the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time which is programmed for 256 switching cycles shown in Figure 31, the device will shut down
itself and restart after the hiccup time of 8192 cycles. The hiccup mode helps reduce the device power
dissipation under severe overcurrent condition.
OCP peak inductor current threshold
OC limiting (waiting) time
256 cycles
hiccup time
8192 cycles
soft start time
T=Css*0.6V/5uA
Output over loading
iL
Inductor Current
Soft-start is reset after OC waiting time
~2.1V
OC fault removed, soft-start and output recovery
SS
0.6V
SS Pin Voltage
Output hard short circuit
Vout
Output Voltage
Figure 31. Over Current Protection
8.3.11 Power Good
The PGOOD pin is an open drain output. Once feedback voltage of each buck is between 95% (rising) and 105%
(falling) of the internal voltage reference, the PGOOD pin pull-down is de-asserted and the pin floats. It is
recommended to use a pull-up resistor between the values of 10kΩ and 100kΩ to a voltage source that is 5.5V
or less. The PGOOD is in a defined state once the VIN input voltage is greater than 1V, but with reduced current
sinking capability. The PGOOD achieves full current sinking capability once the VIN input voltage is above UVLO
threshold, which is 4.25V.
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The PGOOD pin is pulled low when any feedback voltage of a buck is lower than 92.5% (falling) or greater than
107.5% (rising) of the nominal internal reference voltage. Also, the PGOOD is pulled low if the input voltage is
under-voltage locked up, thermal shutdown is asserted, the EN pin is pulled low or the converter is in a soft-start
period.
8.3.12 Adjustable Switching Frequency
The ROSC pin can be used to set the switching frequency by connecting a resistor to GND. The switching
frequency of the device is adjustable from 250KHz to 2MHz.
To determine the ROSC resistance for a given switching frequency, use Equation 10 or the curve in Figure 32.
To reduce the solution size, set the switching frequency as high as possible, but tradeoffs of the supply efficiency
and minimum controllable on time should be considered.
ƒosc (kHz ) = 39557 ´ R(kW )-0.975
(10)
200
175
ROSC (k
150
125
100
75
50
25
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Switching Frequency (kHz)
C010
Figure 32. ROSC versus Switching Frequency
8.3.13 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
160°C typically. The device reinitiates the power up sequence when the junction temperature drops below 140°C
typically.
8.4 Device Functional Modes
8.4.1 Pulse Skipping MODE (PSM)
The TPS65261 can enter high efficiency pulse skipping mode (PSM) operation at light load current.
When a controller is enabled for PSM operation, the peak inductor current is sensed and compared with 230mA
current typically. Since the integrated current comparator catches the peak inductor current only, the average
load current entering PSM varies with applications and external output filters. In PSM, the sensed peak inductor
current is clamped at 230mA.
When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current
comparator turns off the low-side MOSFET when the inductor current reaches zero, preventing it from reversing
and going negative.
Due to the delay in the circuit and current comparator tdly (typical 50ns at VIN = 12V), the real peak inductor
current threshold to turn off high-side power MOSFET, could shift higher depending on inductor inductance and
input/output voltages. The threshold of peak inductor current to turn off high-side power MOSFET can be
calculated by Equation 11.
Vin - Vout
ILPEAK = 230 mA +
´ tdly
(11)
L
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Device Functional Modes (continued)
Once the charge accumulated on the Vout capacitor is more than loading need, COMP pin voltage drops to low
voltage driven by the error amplifier. There is an internal comparator at the COMP pin. If COMP voltage is lower
than 0.35V, the power stage stops switching to save power.
230 mA
Turn off
high-side Power MOSFET
IL_Peak
Inductor Peak Current
Inductor
Current Peak
Current
Sensing
x1
Current Comparator
Delay: tdly
Figure 33. PSM Current Comparator
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9 Application and Implementation
9.1 Application Information
The devices are triple synchronous step down dc/dc converters. They are typically used to convert a higher dc
voltage to lower dc voltages with continuous available output current of 3A/2A/2A. The following design
procedure can be used to select component values for the TPS65261 and TPS65261-1. This section presents a
simplified discussion of the design process.
9.2 Typical Application
C26
22pF
R263
20K
C15
22pF
R153
19.5K
R152 39K
VIN
17
19
20
ROSC
21
AGND
22
FB1
EN1
LX2
2
1
R2
PULL
R7
30K
C5
1uF
BST2
4.7uH
13
C13
10uF
C152
22uF
C101
22uF
C102
22uF
Vin
C12
10uF
L2
10
9
C151
22uF
Vin
12
11
Vout3
+1.8V
Max. 2A
L3
R9
0
C9
47nF
4.7uH
Vout2
+3.3V
Max. 2A
C72
22pF
C71
2.2nF
100K
R3
C16
47nF
SS2
EN2
EN3
32
PGND2
VDIV
R16
0
8
31
PGND3
14
PVIN2
COMP2
30
15
PVIN3
7
R30
20K
29
16
LX3
TPS65261
TPS65261-1
FB2
C29
1uF
PVIN1
6
Vin
R29
146K
28
V7V
C28
10uF
BST3
PGND1
5
27
C182
22pF
LX1
MODE
Vin
26
4.7uH
BST1
4
C262
22uF
25
RESET
C261
22uF
R25
0
C25
47nF
3
L1
PGOOD
Vout1
+1.2V
Max. 3A
COMP1
SS1
24
23
R23
20K
C17
10nF
C181
2.2nF
R18
30K
FB3
C232
22pF
R20
73.2K
18
C231
3.3nF
COMP3
C24
10nF
SS3
R262 20K
C8
10nF
R102 39K
RESET
PGOOD
100K
R103
8.67K
C10
22pF
Figure 34. Typical Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
This example details the design of triple synchronous step-down converter. A few parameters must be known in
order to start the design process. These parameters are typically determined at the system level. For this
example, we start with the following known parameters:
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Vout1
1.2 V
Iout1
3A
Vout2
3.3 V
Iout2
2A
Vout3
1.8 V
Iout3
2A
Transient Response 1A Load Step
±5%
Input Voltage
12 V normal, 4.5 V to 18 V
Output Voltage Ripple
±1%
Switching Frequency
600 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Output Inductor Selection
To calculate the value of the output inductor, use Equation 12. LIR is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor since the
output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general,
the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for the
majority of applications.
V
- Vout
Vout
L = inmax
´
Io ´ LIR
Vin max ´ ƒ sw
(12)
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS and peak inductor current can be found from Equation 14 and Equation 15.
V
- Vout
Vout
Iripple = inmax
´
L
Vinmax ´ ƒ sw
(13)
æ Vout ´ (Vinmax - Vout ) ö
çç
÷÷
Vinmax ´ L ´ ƒ sw
è
ø
2
ILrms = IO +
12
Iripple
ILpeak = Iout +
2
2
(14)
(15)
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
9.2.2.2 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
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The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change
in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be
sized to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a
tolerable amount of drop in the output voltage. Equation 16 shows the minimum output capacitance necessary to
accomplish this.
2 ´ DIout
Co =
ƒ sw ´ DVout
(16)
Where ΔIout is the change in output current, fsw is the regulators switching frequency and ΔVout is the allowable
change in the output voltage.
Equation 17 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Ioripple is the
inductor ripple current.
1
1
Co >
´
8 ´ ƒ sw Voripple
Ioripple
(17)
Equation 18 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification.
Voripple
Resr <
Ioripple
(18)
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in, which increases this
minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or
producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some
capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 19 can
be used to calculate the RMS ripple current the output capacitor needs to support.
Icorms =
Vout ´ (Vinmax - Vout )
12 ´ Vinmax ´ L ´ ƒ sw
(19)
9.2.2.3 Input Capacitor Selection
The TPS65261, TPS65261-1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at
least 10 µF of effective capacitance on the PVIN input voltage pins. In some applications, additional bulk
capacitance may also be required for the PVIN input. The effective capacitance includes any DC bias effects.
The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of The TPS65261, TPS65261-1.
The input ripple current can be calculated using Equation 20.
Iinrms = Iout ´
(Vinmin - Vout )
Vout
´
Vinmin
Vinmin
(20)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be calculated using Equation 21.
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DVin =
SLVSCD3B – DECEMBER 2013 – REVISED MAY 2014
Iout max ´ 0.25
Cin ´ ƒ sw
(21)
9.2.2.4 Loop Compensation
The TPS65261, TPS65261-1 incorporates a peak current mode control scheme. The error amplifier is a transconductance amplifier with a gain of 300 µS. A typical type II compensation circuit adequately delivers a phase
margin between 60° and 90°. Cb adds a high frequency pole to attenuate high frequency noise when needed. To
calculate the external compensation components, follow these steps.
1. Select switching frequency fsw that is appropriate for application depending on L and C sizes, output ripple,
and EMI. Switching frequency between 500kHz to 1MHz gives best trade-off between performance and cost.
To optimize efficiency, lower switching frequency is desired.
2. Set up cross over frequency, ƒc, which is typically between 1/5 and 1/20 of fsw.
3. RC can be determined by
2p ´ ƒc ´ Vo ´ Co
RC =
Gm _EA ´ Vref ´ Gm _PS
(22)
Where Gm_EA is the error amplifier gain (300µS), Gm_PS is the power stage voltage to current conversion gain
(7.4A/V).
æ
ö
1
÷.
4. Calculate CC by placing a compensation zero at or before the dominant pole ç ƒp =
Co ´ RL ´ 2p ø
è
RL ´ Co
CC =
RC
(23)
5. Optional Cb can be used to cancel the zero from the ESR associated with CO.
´ Co
R
Cb = ESR
RC
(24)
LX
VOUT
iL
Current Sense
I/V Converter
RESR
RL
Gm _ PS = 7.4 A/V
Co
R1
Vfb
C1
FB
COMP
EA
V ref = 0.6 V
Rc
R2
Gm _ EA = 300 µS
Cb
Cc
Figure 35. DC/DC Loop Compensation
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9.2.3 Application Curves
28
Figure 36. BUCK1, Soft-Start with No Load
Figure 37. BUCK1, Soft-Start with Full Load
Figure 38. BUCK2, Soft-Start with No Load
Figure 39. BUCK2, Soft-Start with Full Load
Figure 40. BUCK3, Soft-Start with No Load
Figure 41. BUCK3, Soft-Start with Full Load
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Figure 42. BUCK1, PSM Mode,
Steady State Operation at Light Load
Figure 43. BUCK1, Steady State
Operation with Full Load
Figure 44. BUCK2, PSM Mode,
Steady State Operation at Light Load
Figure 45. BUCK2,
Steady State Operation with Full Load
Figure 46. BUCK3, PSM Mode,
Steady State Operation with Light Load
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Figure 47. BUCK3,
Steady State Operation with Full Load
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Figure 48. BUCK1, Load Transient,
0.75A to 1.5A SR=0.25A/µs
Figure 49. BUCK1, Load Transient,
1.5A to 2.25A SR=0.25A/µs
Figure 50. BUCK2, Load Transient, 0.5A to 1.0A
SR=0.25A/µs
Figure 51. BUCK2, Load Transient, 1.0A to 1.5A
SR=0.25A/µs
Figure 52. BUCK3, Load Transient, 0.5A to 1.0A
SR=0.25A/µs
Figure 53. BUCK3, Load Transient, 1.0A to 1.5A
SR=0.25A/µs
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Figure 54. BUCK1, Over Current Protection
Figure 55. BUCK1, Hiccup and Recovery
Figure 56. BUCK2, Over Current Protection
Figure 57. BUCK2, Hiccup and Recovery
Figure 58. BUCK3, Over Current Protection
Figure 59. BUCK3, Hiccup and Recovery
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Figure 60. Automatic Power Sequencing,
MODE=EN1=EN2=HIGH
Figure 61. Automatic Power Sequencing,
MODE=EN1=EN2=HIGH
Figure 62. Automatic Power Sequencing,
MODE=EN1= HIGH, EN2=LOW
Figure 63. Automatic Power Sequencing,
MODE=EN1=HIGH, EN2=LOW
Figure 64. Automatic Power Sequencing,
MODE=EN2=HIGH, EN1=LOW
Figure 65. Automatic Power Sequencing,
MODE=EN2=HIGH, EN1=LOW
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Figure 66. Trigger Voltage 1.23V, Reset vs VDIV
VIN = 12 V
Figure 67. Deglitch Time, Reset vs VDIV
VOUT1 = 1.2 V/1.5 A
VOUT2 = 3.3 V/1 A
VOUT3 = 1.8 V/1 A
EVM Condition 4 Layers, 64mm x 69mm, TA = 27.2°C
VOUT1 = 1.2 V/3 A
VOUT2 = 3.3 V/2 A
VOUT3 = 1.8 V/2 A
EVM Condition 4 Layers, 64mm x 69mm, TA = 27.2°C
Figure 68. Thermal Signature of TPS65261EVM
Figure 69. Thermal Signature of TPS65261EVM
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VIN = 12 V
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10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 18 V. This input
power supply should be well regulated. If the input supply is located more than a few inches from the TPS65261
or TPS65261-1 converter additional bulk capacitance may be required in addition to the ceramic bypass
capacitors. An electrolytic capacitor with a value of 47 μF is a typical choice.
11 Layout
11.1 Layout Guidelines
The TPS65261, TPS65261-1 can be laid out on 2-layer PCB, illustrated in Figure 70.
Layout is a critical portion of good power supply design. See Figure 70 for a PCB layout example. The top
contains the main power traces for PVIN, VOUT, and LX. Also on the top layer are connections for the remaining
pins of the TPS65261, TPS65261-1 and a large top side area filled with ground. The top layer ground area
should be connected to the bottom layer ground using vias at the input bypass capacitor, the output filter
capacitor and directly under the TPS65261, TPS65261-1 device to provide a thermal path from the exposed
thermal pad land to ground. The bottom layer acts as ground plane connecting analog ground and power ground.
For operation at full rated load, the top side ground area together with the bottom side ground plane must provide
adequate heat dissipating area. There are several signals paths that conduct fast changing currents or voltages
that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies
performance. To help eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR
ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by
the bypass capacitor connections, the PVIN pins and the ground connections. The VIN pin must also be
bypassed to ground using a low ESR ceramic capacitor with X5R or X7R dielectric.
Since the LX connection is the switching node, the output inductor should be located close to the LX pins, and
the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor
ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this
conductor length while maintaining adequate width. The small signal components should be grounded to the
analog ground path.
The FB and COMP pins are sensitive to noise so the resistors and capacitors should be located as close as
possible to the IC and routed with minimal lengths of trace. The additional external components can be placed
approximately as shown.
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11.2 Layout Example
VOUT1
SS3
FB3
COMP3
ROSC
AGND
FB1
SS1
COMP1
VOUT3
BST3
BST1
PGND3
PVIN1
PVIN3
VIN
PVIN2
VDIV
PGND2
EN1
LX2
EN2
BST2
SS2
COMP2
FB2
V7V
MODE
RESET
PVIN
EN3
VIN
LX3
PGND1
PGOOD
PVIN
LX1
VOUT2
TOPSIDE
GROUND
AREA
0.010 in. Diameter
Thermal VIA to Ground Plane
VIA to Ground Plane
Figure 70. PCB Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
TPS65262
4.5V to 18V, triple buck with dual adjustable
LDOs
Triple buck 3A/1A/1A output current, dual LDOs 100mA/200mA output
current, automatic power sequencing
TPS65263
4.5V to 18V, triple buck with I2C interface
Triple buck 3A/2A/2A output current, I2C controlled dynamic voltage
scaling (DVS)
TPS65651-1/2/3
4.5V to 18V, triple buck with different
PGOOD deglitch time
Triple buck 3A/2A/2A output current, support 1s, 32ms, 256ms PGOOD
deglitch time, adjustable current limit setting by external resistor
TPS65287
4.5V to 18V, triple buck with power switch
and push button control
Triple buck 3A/2A/2A output current, up to 2.1-A USB power with over
current setting by external resistor, push button control for intelligent
system power-on/power-off operation
TPS65288
4.5V to 18V, triple buck with dual power
switches
Triple buck 3A/2A/2A output current, 2 USB power switches current
limiting at typical 1.2A (0.8/1.0/1.4/1.6/1.8/2.0/2.2A available with
manufacture trim options)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS65261
Click here
Click here
Click here
Click here
Click here
TPS65261-1
Click here
Click here
Click here
Click here
Click here
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65261-1RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65261-1
TPS65261-1RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65261-1
TPS65261RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65261
TPS65261RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65261
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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