TPS65283-1RGET

Order Now Product Folder Support & Community Tools & Software Technical Documents TPS65283, TPS65283-1 SLVSCL3E – JUNE 2014 – REVISED MAY 2019 TPS65283, TPS65283-1 4.5-V to 18-V Input Voltage, Maximum 3.5-A and 2.5-A Current, Synchronous Dual Buck Converter With Power Distribution Switch 1 Features 2 Applications • • • • • • • Buck Converter – Wide input voltage range 4.5 to 18 V – Integrated dual buck converter, maximum continuous current 3.5 A (Buck1) / 2.5 A (Buck2) – Feedback reference voltage 0.6 V ±1% – Adjustable switching frequency 200 kHz to 2 MHz – Internal built soft start time 2.4 ms – External clock synchronization – Cycle-by-cycle current limit – Power good indicator for each buck – Continuous current mode (TPS65283) or pulse skipping mode (PSM) (TPS65283-1) at light load Power distribution switch – Integrated a power distribution switch with onresistance 60 mΩ – Operating input voltage range 2.4 to 6 V – Adjustable current limiting up to 2.7 A – Current-limit accuracy ±10% at 1.25 A (typical) – Auto recovery overcurrent protection – Reverse input to output voltage protection – Overtemperature protection – 24-lead VQFN (RGE) 4-mm × 4-mm package 1 • USB ports and hubs Set top box Digital TV DSL/cable modem, wireless router Home gateway and access point networks Car infotainment 3 Description The TPS65283, TPS65283-1 in thermally-enhanced 4-mm × 4-mm VQFN package is a full featured 4.5- to 18-V Vin, 3.5-A/2.5-A output current synchronous step down DC-DC converter, which is optimized for small designs through high efficiency and integrating the high-side and low-side MOSFETs. The device also incorporates one N-channel MOSFET power switches for power distribution systems. This device provides a total power distribution solution, where precision current limiting and fast protection response are required. Device Information(1) PART NUMBER TPS65283 TPS65283-1 PACKAGE BODY SIZE (NOM) VQFN (24) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Efficiency, Vin = 12 V, PSM 4 Typical Schematic 100% TPS65283 TPS65283-1 90% 80% 18 19 20 Vout1 21 22 VIN 23 DVCC 24 PGOOD1 PGOOD2 1 2 3 FB1 COMP1 BST1 LX1 PGND1 VIN1 V7V PGOOD1 FB2 COMP2 14 70% 13 12 BST2 LX2 11 Vout2 PGND2 10 VIN2 SW_IN SW_OUT EN2 50% 40% VIN 20% 8 7 0% 0.002 6 5 Buck2 at 5 V 10% Vswout nFAULT SW_EN 60% 30% 9 PGOOD2 EN1 Efficiency (%) 17 nFAULT Buck1 at 1.2 V 0.02 0.2 Loading (A) 2 C001 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65283, TPS65283-1 SLVSCL3E – JUNE 2014 – REVISED MAY 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Typical Schematic.................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 3 5 8.1 8.2 8.3 8.4 8.5 8.6 5 5 5 5 6 9 Absolute Maximum Ratings ...................................... Handling Ratings ...................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 9.1 Overview ................................................................. 12 9.2 Functional Block Diagram ....................................... 13 9.3 Feature Description................................................. 13 9.4 Device Functional Modes........................................ 21 10 Application and Implementation........................ 22 10.1 Application Information.......................................... 22 10.2 Typical Application ................................................ 22 11 Power Supply Recommendations ..................... 31 12 Layout................................................................... 31 12.1 Layout Guidelines ................................................. 31 12.2 Layout Example .................................................... 33 13 Device and Documentation Support ................. 34 13.1 13.2 13.3 13.4 Documentation Support ....................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 34 34 34 34 14 Mechanical, Packaging, and Orderable Information ........................................................... 34 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (August 2017) to Revision E • Page Added ROSC resistor in Figure 26 ........................................................................................................................................ 17 Changes from Revision C (August 2014) to Revision D Page • Changed Feature bullet from "...from 100 mA to 2.7 A" to "....up to 2.7 A" .......................................................................... 1 • Deleted text "between typical 100 mA to about 2.7 A" in the 1st sentence of 2nd paragraph of Description. ..................... 3 • Changed "232 kΩ" to "80.6 kΩ" in the Description for RSET in the Pin Functions table. ..................................................... 4 • Added IOS spec condition for RSET = 80.6 kΩ ........................................................................................................................ 7 • Changed from "RSET is 9.1 kΩ ≤ RLIM ≤ 232 kΩ" to "RSET is 9.1 kΩ ≤ RLIM ≤ 80.6 kΩ" in the Programming the Current-Limit Threshold section. .......................................................................................................................................... 15 • Changed from "...adjustable 75 mA to 2.7 A" to "up to 2.7 mA..." in the Comments section of Table 2 (4 places). .......... 22 Changes from Revision B (July 2014) to Revision C Page • Updated V7V and VSYNC_LO minimum in Electrical Characteristics .......................................................................................... 6 • Updated transition voltage to lower than 0.4 V for clock signal amplitude........................................................................... 17 Changes from Revision A (June 2014) to Revision B • Changed device status to production data ............................................................................................................................ 1 Changes from Original (June 2014) to Revision A • 2 Page Page Changed Equation 3 From: ƒosc (kHz) = 41008 × R (kΩ)–0.979 To: ƒosc (kHz) = 47863 × R (kΩ)–0.988 .................................. 16 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated TPS65283, TPS65283-1 www.ti.com SLVSCL3E – JUNE 2014 – REVISED MAY 2019 6 Description (continued) The 60-mΩ independent power distribution switch limits the output current to a programmable current limit threshold by using an external resistor. The current limit accuracy can be achieved as tight as ±10% at typical 1.25 A. The nFAULT output asserts low under overcurrent and reverse-voltage conditions. Constant frequency peak current mode control in DC-DC converter simplifies the compensation and optimizes transient response. Cycle-by-cycle overcurrent protection and operating in hiccup mode limit MOSFET power dissipation during buck output short circuit or over loading conditions. When die temperature exceeds thermal over loading threshold, the overtemperature protection shuts down the device. spacer 7 Pin Configuration and Functions 24 Leads Plastic VQFN (RGE) (Top View) COMP1 FB1 AGND RSET FB2 COMP2 18 17 16 15 14 13 12 BST2 BST1 19 11 LX2 LX1 20 PGND1 21 10 PGND2 Thermal Pad VIN1 22 9 VIN2 8 SW_IN V7V 23 7 SW_OUT 3 4 EN1 EN2 ROSC/SYNC 5 6 nFAULT 2 SW_EN 1 PGOOD2 PGOOD1 24 (There is no electric signal down boned to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.) Pin Functions PIN NAME DESCRIPTION NO. PGOOD2 1 Power good indicator pin. Asserts low if the output voltage of buck2 is out of range due to thermal shutdown, dropout, over-voltage, EN, shutdown, or during slow start. EN1 2 Enable pin for buck 1. A high signal on this pin enables buck1. For a delayed start-up, add a small ceramic capacitor from this pin to ground. EN2 3 Enable pin for buck 2. A high signal on this pin enables buck2. For a delayed start-up, add a small ceramic capacitor from this pin to ground. ROSC/SYNC 4 Automatically select clock frequency program mode and clock synchronization mode. Program the switching frequency of the device from 200 kHz to 2 MHz with an external resistor connecting to the pin. In clock synchronization mode, the device automatically synchronizes to an external clock applied to the pin. SW_EN 5 Enable power switch. Float to enable. nFAULT 6 Active low open-drain output. Asserted during overcurrent or reverse-voltage condition of power switch. Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS65283, TPS65283-1 SLVSCL3E – JUNE 2014 – REVISED MAY 2019 www.ti.com Pin Functions (continued) PIN NAME DESCRIPTION NO. SW_OUT 7 Power switch output SW_IN 8 Power switch input VIN2 9 Input power supply for buck2. Connect this pin as close as possible to the (+) terminal of input ceramic capacitor (10 µF suggested). PGND2 10 Power ground connection. Connect this pin as close as possible to the (–) terminal of input capacitor of buck2. LX2 11 Switching node connection to the inductor and bootstrap capacitor for buck2 converter. This pin voltage swings from a diode voltage below the ground up to input voltage of buck2. BST2 12 Bootstrapped supply to the high-side floating gate driver in buck converter. Connect a capacitor (47 nF recommended) from this pin to LX2. COMP2 13 Error amplifier output and loop compensation pin for buck2. Connect a series resistor and capacitor to compensate the control loop of buck2 with peak current PWM mode. FB2 14 Feedback sensing pin for buck2 output voltage. Connect this pin to the resistor divider of buck2 output. The feedback reference voltage is 0.6 V ±1%. RSET 15 Power switch current limit control pin. An external resistor used to set current limit threshold of power switch. Recommended 9.1 kΩ ≤ RSET ≤ 80.6 kΩ. AGND 16 Analog ground common to buck controller and power switch controller. AGND must be routed separately from high current power grounds to the (–) terminal of bypass capacitor of internal V7V LDO output. FB1 17 Feedback sensing pin for buck1 output voltage. Connect this pin to the resistor divider of buck1 output. The feedback reference voltage is 0.6 V ±1%. COMP1 18 Error amplifier output and loop compensation pin for buck1. Connect a series resistor and capacitor to compensate the control loop of buck1 converter with peak current PWM mode. BST1 19 Bootstrapped supply to the high side floating gate driver in buck converter. Connect a capacitor (recommend 47 nF) from this pin to LX1. LX1 20 Switching node connection to the inductor and bootstrap capacitor for buck1. This pin voltage swings from a diode voltage below the ground up to input voltage of buck1. PGND1 21 Power ground connection. Connect this pin as close as possible to the (–) terminal of input capacitor of buck1. VIN1 22 Input power supply for buck1 and internal analog bias circuitries. Connect this pin as close as possible to the (+) terminal of an input ceramic capacitor (10 µF suggested). V7V 23 Internal linear regulator (LDO) output with input from VIN1. The internal driver and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum 1-µF ceramic capacitor. The output voltage level of LDO is regulated to typical 6.3 V for optimal conduction on-resistances of internal power MOSFETs. In PCB design, the power ground and analog ground should have one-point common connection at the (–) terminal of V7V bypass capacitor. PGOOD1 24 Power good indicator pin. Asserts low if the output voltage of buck1 is out of range due to thermal shutdown, dropout, over-voltage, EN shutdown or during slow start. PowerPAD™ — Exposed pad beneath the IC. Connect to the power ground. Always solder power pad to the board, and have as many vias as possible on the PCB to enhance power dissipation. There is no electric signal down bonded to paddle inside the IC package. 4 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated TPS65283, TPS65283-1 www.ti.com SLVSCL3E – JUNE 2014 – REVISED MAY 2019 8 Specifications 8.1 Absolute Maximum Ratings (Operating in a typical application circuit) over operating free-air temperature range and all voltages are with respect to AGND (unless otherwise noted) (1) VIN1, LX1, VIN2, LX2 MIN MAX –0.3 20 V LX1, LX2 (Maximum withstand voltage transient