TPS659161RGZR

Product Folder Order Now Technical Documents Tools & Software Support & Community TPS65916 SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 TPS65916 3.1-V to 5.2-V, 5 Buck Converter and 5 LDO Power Management IC (PMIC) 1 Device Overview 1.1 Features 1 • System Voltage Range from 3.135 V to 5.25 V • Low-Power Consumption – 20 μA in Off Mode – 90 μA in Sleep Mode With Two SMPSs Active • Five Step-Down Switched-Mode Power Supply (SMPS) Regulators: – 0.7- to 3.3-V Output Range in 10- or 20-mV Steps – Two SMPS Regulators With 3.5-A Capability, With the Ability to Combine into 7-A Output in Dual-Phase Configuration, With Differential Remote Sensing (Output and Ground) – Three Other SMPS Regulators with 3-A, 2-A, and 1.5-A Capabilities – Dynamic Voltage Scaling (DVS) Control and Output Current Measurement in 3.5-A and 3-A SMPS Regulators – Hardware and Software Controlled Eco-mode™ Supplying up to 5 mA – Short-Circuit Protection – Power-Good Indication (Voltage and Overcurrent Indication) – Internal Soft-Start for In-Rush Current Limitation – Ability to Synchronize to External Clock between 1.7 MHz and 2.7 MHz • Five Low-Dropout (LDO) Linear Regulators: – 0 .9- to 3.3-V Output Range in 50-mV steps – Two With 300-mA Capability and Bypass Mode 1.2 • • • • • • • • Applications Industrial Automation Human Machine Interface (HMI) Camera Surveillance System 1.3 • – One With 100-mA Capability and Capable of Low-Noise Performance up to 50 mA – Two Other LDOs With 200-mA Current Capability – Short-Circuit Protection 12-Bit Sigma-Delta General-Purpose ADC (GPADC) With 8 Input Channels (2 external) Thermal Monitoring With High Temperature Warning and Thermal Shutdown Power Sequence Control: – Configurable Power-Up and Power-Down Sequences (OTP) – Configurable Sequences Between the SLEEP and ACTIVE State Transition (OTP) – Three Digital Output Signals that can be Included in the Startup Sequence Selectable Control Interface: – One SPI for Resource Configurations and DVS Control – Two I2C Interfaces. – One Dedicated for DVS Control – One General Purpose I2C Interface for Resource Configuration and DVS Control OTP Bit-Integrity Error Detection With Options to Proceed or Hold Power-Up Sequence and RESET_OUT Release Package Option: – 7-mm × 7-mm 48-pin VQFN With 0.5-mm Pitch • • Programmable Logic Controller (PLC) Factory Automation Description The TPS65916 PMIC integrates five configurable step-down converters with up to 3.5 A of output current to power the processor core, memory, I/O, and preregulation of LDOs The step-down converters are synchronized to an internal 2.2-MHz clock to improve EMC performance of the device. The GPIO_3 pin allows the step-down converters to synchronize to an external clock, allowing multiple devices to synchronize to the same clock which improves system-level EMC performance. The device also contains five LDOs to power low-current or low-noise domains. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65916 SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 www.ti.com The power-sequence controller uses one-time programmable (OTP) memory to control the power sequences, as well as default configurations such as output voltage and GPIO configurations. The OTP is factory-programmed to allow start-up without any software required. Most static settings can be changed from the default through SPI or I2C to configure the device to meet many different system needs. For example, voltage-scaling registers are used to support dynamic voltage-scaling requirements of processors. The OTP also contains a bit-integrity-error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS65916 device also includes an analog-to-digital converter (ADC) to monitor the system state. The GPADC includes two external channels to monitor any external voltage, as well as internal channels to measure supply voltage, output current, and die temperature, allowing the processor to monitor the health of the system. The device offers a watchdog to monitor for software lockup, and includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring, shutdown, and automatic ADC conversions to detect if a voltage is below a predefined threshold. The PMIC can notify the processor of these events through the interrupt handler, allowing the processor to take action in response. Device Information (1) PART NUMBER TPS65916 (1) 2 PACKAGE VQFN (48) BODY SIZE (NOM) 7.00 mm × 7.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Overview Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 TPS65916 www.ti.com 1.4 SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 Functional Diagram VCCA VCCA I2C and SPI VSYS Monitor VCC_SENSE INT First Supply Detection 32-kHz RC Oscillator Interrupt Handler PWRON SYNCCLKOUT Bandgap REFSYS VBG 1.23-V Vref REFGND PWRDOWN POWERHOLD RESET_IN NSLEEP NRESWARM BBS Independent Bandgap ÷6 Event Handler RC15M OSC SYNCDCDC PLL I2C/SPI OFF2ACT ACT2OFF ACT2SLP SLP2ACT NRESWARM Watchdog Timer OSC + PLL LDOVRTC OTP LDOVRTC_OUT Power Sequencer LDO1, Bypass CRC SMPS1 VIN Monitor, Thermal SD, Short Circuit Monitor Registers LDO1_OUT SMPS1_IN SMPS1_FDBK Short Circuit Monitor Dual Phase or Single Phase LDO12_IN VCCA LDO2, Bypass Thermal Monitor Short Circuit Monitor LDO2_OUT VIN Monitor, Thermal SD, Short Circuit Monitor SMPS/LDO POWERGOOD/SHORT/ VINLOW LDO3 LDO3_IN SMPS2 SMPS2_IN Resource Controller SMPS2_FDBK Short Circuit Monitor LDO3_OUT I2C and SPI SMPS3 GPADC Controller LDO4 LDO4_IN CNTRL Short Circuit Monitor Registers VIN Monitor, Thermal SD, Short Circuit Monitor LDO4_OUT SMPS3_IN SMPS3_FDBK LDO5, LN LDO5_IN SMPS4_IN Short Circuit Monitor SMPS4 LDO5_OUT VIN Monitor, Short Circuit Monitor I2C and SPI I/O 12-Bit GPADC LDOVANA SMPS4_FDBK LDOVANA_OUT GPIO6 NSLEEP REGEN3 POWERGOOD I2C1_SDA_SDO I2C2_SCL_SCE I2C1_SDA_SDI I2C1_SCL_CLK ADCIN2 VIN Monitor, Thermal SD, Short Circuit Monitor ADCIN1 GPIO_6 GPIO5 REGEN3 POWERHOLD GPIO_5 GPIO_4 DVFS_CLK SMPS5 GPIO4 REGEN2 I2C2_SCL_SCE GPIO3 ENABLE2 REGEN1 SYNCDCDC GPIO_3 GPIO_2 GPIO2 ENABLE1 I2C2_SDA_SDO DVFS_DAT GPIO1 RESET_IN NRESWARM VBUS_SENSE VIO GPIO_1 VIO_IN GPIO_0 GPIO0 ENABLE2 PWRDOWN REGEN1 VCC_SENSE 7x GPIO POWERGOOD Monitor SMPS5_IN SMPS5_FDBK POWERGOOD Figure 1-1. Functional Diagram Device Overview Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 3 TPS65916 SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 www.ti.com Table of Contents 1 Device Overview ......................................... 1 Features .............................................. 1 1.1 2 3 4 1.2 Applications ........................................... 1 1.3 Description ............................................ 1 1.4 Functional Diagram ................................... 3 4.24 4.25 Revision History ......................................... 5 Pin Configuration and Functions ..................... 6 4.26 3.1 Pin Attributes ......................................... 6 4.27 3.2 Signal Descriptions ................................... 9 5 Switching Characteristics — Reference Generator (Bandgap) ........................................... Switching Characteristics — PLL for SMPS Clock Generation .......................................... Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers ................. Switching Characteristics — 12-Bit Sigma-Delta ADC ................................................. 23 23 23 24 Typical Characteristics .............................. 26 Detailed Description ................................... 29 ............................................ Specifications ........................................... 12 5.1 Overview 4.1 Absolute Maximum Ratings ......................... 12 5.2 Functional Block Diagram ........................... 30 4.2 ESD Ratings ........................................ Recommended Operating Conditions ............... Thermal Information ................................. Electrical Characteristics — LDO Regulators ....... 5.3 5.4 Device State Machine ............................... 31 Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs) .................................. 41 5.5 SMPS and LDO Input Supply Connections 5.6 First Supply Detection 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 Electrical Characteristics — SMPS1&2 in DualPhase Configuration ................................ Electrical Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators ........................................... Electrical Characteristics — Reference Generator (Bandgap) ........................................... Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers ................. Electrical Characteristics — 12-Bit Sigma-Delta ADC ................................................. Electrical Characteristics — Thermal Monitoring and Shutdown ............................................ Electrical Characteristics — System Control Thresholds .......................................... 12 12 13 13 5.7 5.8 15 16 17 17 18 18 19 Electrical Characteristics — Current Consumption . 19 Electrical Characteristics — Digital Input Signal Parameters .......................................... 19 Electrical Characteristics — Digital Output Signal Parameters .......................................... 20 6 4.16 I/O Pullup and Pulldown Characteristics ............ 20 7 4.17 Electrical Characteristics — I2C Interface ........... 20 4.18 Timing Requirements — I2C Interface .............. 21 4.19 Timing Requirements — SPI 4.20 4.21 22 Switching Characteristics — SMPS1&2 in DualPhase Configuration ................................ 22 Switching Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators ........................................... 23 4.13 4.14 4.15 4.22 4 4.23 ....................... Switching Characteristics — LDO Regulators ...... 22 8 ........ .............................. Long-Press Key Detection .......................... 29 50 50 51 12-Bit Sigma-Delta General-Purpose ADC (GPADC) ............................................ 51 5.9 General-Purpose I/Os (GPIO Pins) ................. 55 5.10 Thermal Monitoring .................................. 56 ........................................... ................................... 5.13 OTP Configuration Memory ........................ 5.14 Watchdog Timer (WDT) ............................ 5.15 System Voltage Monitoring ......................... 5.16 Register Map ........................................ 5.17 Device Identification ................................. Applications, Implementation, and Layout........ 6.1 Application Information .............................. 6.2 Typical Application .................................. 6.3 Layout ............................................... 6.4 Power Supply Coupling and Bulk Capacitors ....... Device and Documentation Support ............... 7.1 Device Support ...................................... 7.2 Documentation Support ............................. 7.3 Receiving Notification of Documentation Updates .. 7.4 Community Resources .............................. 7.5 Trademarks.......................................... 7.6 Electrostatic Discharge Caution ..................... 7.7 Glossary ............................................. 5.11 Interrupts 5.12 Control Interfaces 57 60 65 65 66 69 69 70 70 71 79 82 83 83 83 83 84 84 84 84 Mechanical, Packaging, and Orderable Information .............................................. 84 Table of Contents Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 TPS65916 www.ti.com SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2017) to Revision C • • • • • • • • • • • • • • • • • • • Page Added footnote recommending not to pull open-drain GPIOs up to an always-on voltage domain ....................... 9 Clarified that LDO1 and LDO2 input pins are not included in this minimum recommended operating voltage. See Electrical Characteristics: LDO Regulators for more information. ............................................................ 12 Added LDO and SMPS output capacitance footnote ........................................................................... 13 Added SMPS Output voltage slew rate description ............................................................................ 15 Changed the comparison condition from VCCA to VCC_SENSE in the Embedded Power Controller section......... 32 Added typical debounce time from POWERHOLD to the enable of the first rail in the power sequence. .............. 33 Changed discharge resistance to match electrical characteristics table ..................................................... 42 Changed description of clock dithering from internal to external only ........................................................ 44 Added information about shutdown timing during short circuit detection ................................................... 45 Updated POWERGOOD block diagram and description to clarify dual phase operation. ................................ 46 Added notes to the SMPS Controls for DVS image ............................................................................ 48 Added the equation to convert GPADC code to internal die temperature in the 12-Bit Sigma-Delta GeneralPurpose ADC (GPADC) section ................................................................................................... 52 Additional description of VSYS_LO functionality ............................................................................... 66 Added details on identifying device version. .................................................................................... 69 SMPS and LDO output capacitance specification further explained ......................................................... 74 Added design considerations for VCCA capacitance to support loss of power ............................................. 74 Corrected 9-Vpp with 7V absolute maximum specification in the Layout Guidelines section ............................. 79 Updated requirements relating to measurement of high-side and low-side FETs in the Layout Guidelines section ... 80 Updated images and description on differential measurements across high-side and low-side FETs .................. 81 Changes from Revision A (September 2016) to Revision B • • • • • • • • • • Page Added recommendation for external pulldown resistor on the LDOVRTC_OUT pin in the Pin Attributes table ......... 7 Added OTP to the PU/PD selection for GPIO_1 as NRESWARM in the Signal Descriptions table ...................... 9 Changed the caption of the SMPS Efficiency For SMPS1 and SMPS 2 in Dual-Phase PWM Mode graph to SMPS Load Regulation for SMPS1 and SMPS2 Single-Phase PWM Mode in the Typical Characteristics section ... 26 Added the SMPS Load regulation for SMPS3, PWM Mode graph to the Typical Characteristics section .............. 26 Changed single-phase to dual-phase and increased the output current to 7 A in the SMPS Load Regulation for SMPS12 graph in the Typical Characteristics section.......................................................................... 26 Changed the debounce for PWRON to N/A in the ON Requests table ...................................................... 33 Added description of VIO power-up timing in the Device Power Up Timing section ....................................... 37 Changed the description of the LDOVRTC when in the BACKUP and OFF states and added a note in the LDOVRTC section .................................................................................................................. 50 Added the note and pulldown equations to the System Voltage Monitoring section ....................................... 67 Changed the Electrostatic Discharge Caution statement ...................................................................... 84 Changes from Original (March 2016) to Revision A • Page Changed the device status from Product Preview to Production Data ........................................................ 2 Revision History Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 5 TPS65916 SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 www.ti.com 3 Pin Configuration and Functions VCC_SENSE REFGND 41 37 VCCA 42 ADCIN1 LDOVANA_OUT 43 38 LDOVRTC_OUT 44 VBG SMPS5_FDBK 45 ADCIN2 SMPS5_IN 46 39 SMPS5_SW 47 40 SYNCCLKOUT 48 Figure 3-1 shows the 48-pin RGZ plastic quad-flatpack no-lead (VQFN) pin assignments and thermal pad. GPIO_4 1 36 I2C1_SDA_SDI GPIO_2 2 35 I2C1_SCL_SCK LDO5_IN 3 34 VIO_IN LDO5_OUT 4 33 SMPS1_FDBK LDO3_IN 5 32 SMPS1_IN LDO3_OUT 6 31 SMPS1_SW LDO4_OUT 7 30 SMPS2_SW LDO4_IN 8 29 SMPS2_IN SMPS3_FDBK 9 28 SMPS2_FDBK SMPS3_IN 10 27 GPIO6 SMPS3_SW 11 26 INT GPIO_0 12 25 RESET_OUT 13 14 15 16 17 18 19 20 21 22 23 24 GPIO_1 GPIO_3 GPIO_5 BOOT SMPS4_FDBK SMPS4_IN SMPS4_SW VPROG LDO2_OUT LDO12_IN LDO1_OUT PWRON Thermal Pad (PGND) Figure 3-1. 48-Pin RGZ (VQFN) Package, 0.5-mm Pitch, With Thermal Pad (Top View) 3.1 Pin Attributes Pin Attributes PIN NAME NO. I/O DESCRIPTION CONNECTION IF NOT USED PU/PD (1) Ground — — — System supply — Ground — REFERENCE REFGND 41 — System reference ground VBG 40 O Bandgap reference voltage STEP-DOWN CONVERTERS (SMPSs) SMPS1_IN 32 I Power input for SMPS1 SMPS1_FDBK 33 I Output voltage-sense (feedback) input for SMPS1 or differential voltage-sense (feedback) positive input for SMPS12 in dual-phase configuration SMPS1_SW 31 O Switch node of SMPS1; connect output inductor SMPS2_IN 29 I Power input for SMPS2 SMPS2_FDBK 28 I Output voltage-sense (feedback) input for SMPS2 or differential voltage-sense (feedback) negative input for SMPS12 in dual-phase configuration SMPS2_SW 30 O Switch node of SMPS2; connect output inductor SMPS3_IN 10 I Power input for SMPS3 Floating — System supply — Ground — Floating — System supply — SMPS3_FDBK 9 I Output voltage-sense (feedback) input for SMPS3 Floating — SMPS3_SW 11 O Switch node of SMPS3; connect output inductor Floating — SMPS4_IN 18 I Power input for SMPS4 System supply — (1) 6 The PU/PD column shows the pullup and pulldown resistors on the digital input lines. Pullup and pulldown resistors: PU = Pullup, PD = Pulldown, PPU = Software-programmable pullup, PPD = Software-programmable pulldown. Pin Configuration and Functions Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 TPS65916 www.ti.com SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 Pin Attributes (continued) PIN NAME NO. I/O DESCRIPTION CONNECTION IF NOT USED PU/PD (1) SMPS4_FDBK 17 I Output voltage-sense (feedback) input for SMPS4 Ground — SMPS4_SW 19 O Switch node of SMPS4; connect output inductor Floating — SMPS5_IN 46 I Power input for SMPS5 System supply — SMPS5_FDBK 45 I Output voltage-sense (feedback) input for SMPS5 Ground — SMPS5_SW 47 O Switch node of SMPS5; connect output inductor Floating — LOW-DROPOUT REGULATORS LDO12_IN 22 I Power input voltage for LDO1 and LDO2 regulators System supply — LDO1_OUT 23 O LDO1 output voltage Floating — LDO2_OUT 21 O LDO2 output voltage Floating — LDO3_IN 5 I Power input voltage for LDO3 regulator System supply — LDO3_OUT 6 O LDO3 output voltage LDO4_IN 8 I Power input voltage for LDO4 regulator LDO4_OUT 7 O LDO4 output voltage LDO5_IN 3 I Power input voltage for LDO5 regulator LDO5_OUT 4 O LDO5 output voltage Floating — System supply — Floating — System supply — Floating — LOW-DROPOUT REGULATORS (INTERNAL) LDOVRTC_OUT 44 O LDOVRTC output voltage. To support rapid power off and on, connect a pulldown resistor on the LDOVRTC_OUT pin. See Section 5.15 for more details. — — LDOVANA_OUT 43 O LDOVANA output voltage — — ADCIN1 38 I GPADC input 1 Ground — ADCIN2 39 I GPADC input 2 Ground — Floating — Boot ball for power-up sequence selection Ground or VRTC — Primary function: General-purpose input (2) and output Ground or VRTC PPD Floating PPD (2) GPADC CLOCKING SYNCCLKOUT 48 O 16 I Primary function: 2.2-MHz fallback switching frequency for SMPS Secondary function: 32-kHz digital-gated output clock when VIO_IN input supply is present SYSTEM CONTROL BOOT I/O GPIO_0 12 I Secondary function: ENABLE2 which is the peripheral power request input 2 Secondary function: PWRDOWN input GPIO_1 13 Ground or VIO PPD O Secondary function: REGEN1 which is the external regulator enable output 1 Floating — I/O Primary function: General-purpose input (2) and output Floating PPD Secondary function: RESET_IN which is the reset input Floating PPD Ground or VIO — VRTC PPD Primary function: General-purpose input (2) and output Floating PPU PPD I Secondary function: ENABLE1 which is the peripheral power request input 1 Floating PPU PPD (2) I/O Secondary function: I2C2_SDA_SDO which is the DVS I2C serial bidirectional data (external pullup) and the SPI output data signal Floating — I Secondary function: VBUS_SENSE input Secondary function: NRESWARM which is the warm reset input I/O GPIO_2 (2) 2 Default option. Pin Configuration and Functions Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 7 TPS65916 SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 www.ti.com Pin Attributes (continued) PIN NAME NO. GPIO_3 GPIO_4 14 1 I/O GPIO_6 I2C1_SCL_SCK 15 27 35 CONNECTION IF NOT USED PU/PD (1) I/O Primary function: General-purpose input (2) and output Floating PPD O Secondary function: REGEN1 which is the external regulator enable output 1 Floating — I Secondary function: ENABLE2 which is the peripheral power request input 2 I Secondary function: SYNCDCDC which is the synchronization signal for SMPS switching Floating PPD (2) I/O Primary function: General-purpose input (2) and output Floating PPU PPD O Secondary function: REGEN2 which is the external regulator enable output 2 Floating — I Secondary function: I2C2_SCL_SCE which is the DVS I2C serial clock (external pullup) and the SPI chip enable signal Floating — Primary function: General-purpose input (2) and output Ground PPD I/O GPIO_5 DESCRIPTION PPD (2) I Secondary function: POWERHOLD input Ground or VIO PPD O Secondary function: REGEN3 which is the external regulator enable output 3 Floating — I/O Primary function: General-purpose input (2) and output Ground PPD I Secondary function: NSLEEP request signal Floating PPU (2) PPD O Secondary function: POWERGOOD which is the indication signal for valid regulator output voltages Floating — O Secondary function: REGEN3 which is the external regulator enable output 3 Floating — I Control I2C serial clock (external pullup) and SPI clock signal — — 2 I2C1_SDA_SDI 36 I/O Control I C serial bidirectional data (external pullup) and SPI input data signal — — INT 26 O Maskable interrupt output request to the host processor — — PWRON 24 I External power-on event (on-button switch-on event) Floating PU O System reset or power on output (low = reset, high = active or sleep) Floating — I Primary function: OTP programming voltage Ground or floating — O Secondary function: TESTV Floating — RESET_OUT 25 PROGRAMMING, TESTING VPROG 20 POWER SUPPLIES VCCA 42 I Analog input voltage for internal LDOs System supply — VCC_SENSE 37 I System supply sense line System supply — VIO_IN 34 I Digital supply input for GPIOs and I/O supply voltage N/A — 8 Pin Configuration and Functions Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 TPS65916 www.ti.com 3.2 SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 Signal Descriptions Table 3-1. Signal Descriptions SIGNAL NAME PWRON BOOT I/O (1) LEVEL ACTIVITY OTP POLARITY SELECTION Input PU fixed N/A (fixed) N/A (input) Low No Tri-level input N/A (input) N/A (input) N/A (input) Boot conf. No Input (1)/output PPD OTP/SW Open-drain Low or high Yes Input PPD (Opt. Ext. PU) OTP/SW N/A (input) High Yes Input PPD (1) SW N/A (input) High No, but software possible Output N/A (output) N/A (output) Open-drain High No Input (1)/output PPD OTP/SW Open-drain Low or high Yes Input PPD OTP/SW N/A (input) Low Yes Input PPD OTP/SW N/A (input) Low or high Yes Input No No N/A (input) High No VRTC, fail-safe (5.25-V tolerance) GPIO_0 secondary function: REGEN1 (3) GPIO_1 (primary function) GPIO_1 secondary function: RESET_IN VRTC, fail-safe (5.25-V tolerance) GPIO_1 secondary function: VBUS_SENSE (1) (2) (3) OUTPUT TYPE SELECTION VRTC GPIO_0 secondary function: PWRDOWN GPIO_1 secondary function: NRESWARM PU/PD SELECTION VSYS (VCCA) GPIO_0 (primary function) GPIO_0 secondary function: ENABLE2 INPUT PU/PD (2) Default option. Pullup and pulldown resistors: PU = Pullup, PD = Pulldown, PPU = Software-programmable pullup, PPD = Software-programmable pulldown. This pin should not be pulled up to an always-on voltage domain. Before OTP is loaded, this will be configured as an input, and an active pull-up domain will pull this pin to a high level. Pin Configuration and Functions Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 9 TPS65916 SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 www.ti.com Table 3-1. Signal Descriptions (continued) I/O (1) INPUT PU/PD (2) PU/PD SELECTION OUTPUT TYPE SELECTION ACTIVITY OTP POLARITY SELECTION Input (1)/output PPU/PPD OTP/SW Push-pull (1) or open-drain Low or high Yes Input PPU/PPD (1) SW N/A (input) High No, but software possible GPIO_2 secondary function: I2C2_SDA_SDO Input/output No No Open-drain High No GPIO_3 (primary function) Input (1)/output PPD OTP/SW Open-drain Low or high Yes Input PPD (1) SW N/A (input) High No, but software possible Output N/A (output) N/A (output) Open-drain High No Input PPD (1) SW N/A (input) Toggling No Input (1)/output PPU/PPD OTP/SW Push-pull (1) or open-drain Low or high Yes Output N/A (output) N/A (output) Push-pull (1) or open-drain High No Input No No N/A (input) High No SIGNAL NAME LEVEL GPIO_2 (primary function) GPIO_2 secondary function: ENABLE1 VIO (VIO_IN) GPIO_3 secondary function: ENABLE2 GPIO_3 secondary function: REGEN1 (3) VRTC, fail-safe (5.25-V tolerance) GPIO_3 secondary function: SYNCDCDC GPIO_4 (primary function) GPIO_4 secondary function: REGEN2 VIO (VIO_IN) GPIO_4 secondary function: I2C2_SCL_SCE 10 Pin Configuration and Functions Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 TPS65916 www.ti.com SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 Table 3-1. Signal Descriptions (continued) I/O (1) INPUT PU/PD (2) PU/PD SELECTION OUTPUT TYPE SELECTION ACTIVITY OTP POLARITY SELECTION Input (1)/output PPD OTP/SW Open-drain Low or high Yes Input PPD (1) SW N/A (input) High Yes Output N/A (output) N/A (output) Open-drain High No GPIO_6 (primary function) Input (1)/output PPD OTP/SW Open-drain Low or high Yes GPIO_6 secondary function: NSLEEP Input PPU (1)/PPD SW N/A (input) Low Yes Output N/A (output) N/A (output) Open-drain Low or high Yes Output N/A (output) N/A (output) Open-drain High No Output N/A (output) N/A (output) Push-pull (1) or open-drain Low No Push-pull (1) or open-drain Low No, but software possible SIGNAL NAME LEVEL GPIO_5 (primary function) GPIO_5 secondary function: POWERHOLD VRTC, fail-safe (5.25-V tolerance) GPIO_5 secondary function: REGEN3 (3) GPIO_6 secondary function: POWERGOOD (3) VRTC GPIO_6 secondary function: REGEN3 (3) RESET_OUT INT VIO (VIO_IN) VIO (VIO_IN) Output N/A (output) N/A (output) SYNCCLKOUT VRTC Output N/A (output) N/A (output) Push-pull Toggling No I2C1_SDA_SDI VIO (VIO_IN) Input/output No No Open-drain High No I2C1_SCL_CLK VIO (VIO_IN) Input No No N/A (input) High No VCC_SENSE VSYS (VCCA) Input No No N/A (analog) Analog No Pin Configuration and Functions Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 11 TPS65916 SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 www.ti.com 4 Specifications 4.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VCCA –0.3 6 VCC_SENSE –0.3 7 All LDOs and SMPS supply voltage input pins –0.3 6 SMPSx_SW pins, 10-ns transient All SMPS-related input pins _FDBK –2 7 –0.3 3.6 I/O digital supply voltage (VIO_IN with respect to VIO_GND) –0.3 VIOmax + 0.3 Voltage VIOmax + 0.3 VBUS –0.3 6 GPADC pins: ADCIN1 and ADCIN2 –0.3 2.4 OTP supply voltage VPROG –0.3 7 VRTC digital input pins, without fail-safe –0.3 2.15 VRTC digital input pins, with fail-Safe –0.3 5.25 VIO digital input pins (VIO_IN pin reference) –0.3 VIOmax + 0.3 VSYS digital input pins (VCCA pin reference) –0.3 6 –5 5 Peak output current on all pins other than power resources Current UNIT Buck SMPS, SMPSx_IN, SMPSx_SW, and SMPSx_OUT total per phase 4 LDOs 1 V mA A Junction temperature, TJ –45 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4.2 ESD Ratings VALUE (1) ±2000 All pins ±500 Corner pins (1, 12, 13, 24, 25, 36, 37, and 48) ±750 Human-body model (HBM), per AEC Q100-002 V(ESD) (1) 4.3 Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted). MIN NOM MAX UNIT System voltage input pin VCCA (named VSYS in the specification) 3.135 3.8 5.25 V VCC_SENSE, HIGH_VCC_SENSE = 0 (if measured with GPADC, see also Table 5-9) 3.135 VCCA V VCC_SENSE, HIGH_VCC_SENSE = 1 (if measured with GPADC, see also Table 5-9) 3.135 VCCA – 1 V 5.25 V ELECTRICAL All LDO-related input pins _IN (1) All SMPS-related input pins _IN All SMPS-related input pins _FDBK 3.135 3.8 –0.3 I/O digital supply voltage VIO_IN 12 3.8 0 All SMPS-related input pins _FDBK_GND (1) 1.75 5.25 V VOUTmax + 0.3 V 0.3 V VIO = 1.8 V 1.71 1.8 1.89 VIO = 3.3 V 3.135 3.3 3.465 V Does not include LDO1 and LDO2 minimum input voltages. Specifications Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 TPS65916 www.ti.com SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 Recommended Operating Conditions (continued) Over operating free-air temperature range (unless otherwise noted). MIN Voltage on the GPADC pins ADCIN1 (channel 0) and ADCIN2 (channel 1) 0 OTP supply voltage VPROG 0 Voltage on VRTC digital input pins NOM MAX UNIT 1.25 V 6 V without fail-safe 0 LDOVRTC 1.85 with fail-safe 0 LDOVRTC 5.25 V Voltage on VIO digital input pin (VIO_IN pin reference) 0 VIO VIOmax V Voltage on VSYS digital input pins (VCCA pin reference) 0 3.8 5.25 V °C TEMPERATURE Operating free-air temperature range (2) Junction temperature, TJ –40 27 105 Operational –40 27 150 Parametric compliance –40 27 125 27 150 Storage temperature, Tstg –65 Lead temperature (soldering, 10 s) (2) °C °C 260 °C Additional cooling strategies may be necessary to maintain junction temperature at recommended limits. 4.4 Thermal Information TPS65916 THERMAL METRIC (1) RGZ (VQFN) UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 24.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 5.6 °C/W RθJB Junction-to-board thermal resistance 3.9 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 3.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 4.5 Electrical Characteristics — LDO Regulators Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted). PARAMETER TEST CONDITIONS Input filtering capacitance (C18, C19) Connected from LDOx_IN to GND Shared input tank capacitance (depending on platform requirements) Output filtering capacitance (C20, C21, C22, Connected from LDOx_OUT to GND C23, C24) (1) < 100 kHz CESR TYP 0.6 2.2 MAX 0.6 2.2 2.7 20 100 600 1 10 20 µF mΩ 1 to 10 MHz VIN(LDOx) UNIT µF Filtering capacitor ESR 0.9 V ≤ VOUT < 2.2 V 1.2 VCCA 2.2 V ≤ VOUT ≤ 3.3 V 1.2 5.25 LDO1, LDO2 from LDO12_IN, Bypass Mode VOUT = VIN 1.2 3.6 LDO3, LDO4, LDO5 from LDO3_IN, LDO4_IN and LDO5_IN 0.9 V ≤ VOUT < 2.2 V 1.75 VCCA 2.2 V ≤ VOUT ≤ 3.3 V 1.75 5.25 LDO1, LDO2 from LDO12_IN, Normal Mode Input voltage (2) (except Range 0.9 VOUT(LDOx) LDO output voltage programmable LDOVRTC and LDOVANA) TDCOV(LDOx) All LDOs except LDOVANA and LDOVRTC Total DC output voltage accuracy, including VIN(LDOx) ≥ 2.5 V voltage references, DC load and line regulations, process and temperature All LDOs except LDOVANA and LDOVRTC VIN(LDOx) < 2.5 V and VOUT(LDOx) < 1.5 V (1) (2) MIN Step size 3.3 50 V V mV 0.99 × VOUT(LDOx) – 0.014 1.006 × VOUT(LDOx) + 0.014 0.99 × VOUT(LDOx) – 0.014 1.006 × VOUT(LDOx) + 0.014 V Additional information about how this parameter is specified is located in Section 6.2.2. LDO output voltages are programmed separately. Specifications Copyright © 2016–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65916 13 TPS65916 SLVSD09C – MARCH 2016 – REVISED FEBRUARY 2019 www.ti.com Electrical Characteristics — LDO Regulators (continued) Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted). MIN TYP MAX –40°C ≤ TA ≤ 85°C 1.726 1.8 1.85 TDCOV(LDOx) Total DC output voltage accuracy, including voltage references, DC load and line LDOVRTC_OUT regulations, process and temperature PARAMETER 85°C