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TPS65186
SLVSB04A – JULY 2011 – REVISED AUGUST 2015
TPS65186 PMIC for E Ink® Vizplex™ Enabled Electronic Paper Display
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
•
•
Single Chip Power-Management Solution for
E Ink® Vizplex™ Electronic Paper Displays
Generates Positive and Negative Gates, Source
Driver Voltages, and Back-Plane Bias From a
Single, Low-Voltage Input Supply
Supports 9.7 Inch and Larger Panel Size
3-V to 6-V Input Voltage Range
Boost Converter for Positive Rail Base
Inverting Buck-Boost Converter for Negative Rail
Base
Two Adjustable LDOs for Source Driver Supply
– LDO1: 15 V, 120 mA (VPOS)
– LDO2: –15 V, 120 mA (VNEG)
Accurate Output Voltage Tracking
– VPOS – VNEG = ±50 mV
Two Charge Pumps for Gate Driver Supply
– CP1: 22 V, 10 mA (VDDH)
– CP2: –20 V, 12 mA, (VEE)
Adjustable VCOM Driver for Accurate PanelBackplane Biasing
– 0 V to –5.11 V
– ± 1.5% accuracy (±10 mV)
– 9-Bit Control (10-mV Nominal Step Size)
Integrated 10-Ω, 3.3-V Power Switch for Disabling
System Power Rail to E-Ink Panel
•
•
•
•
•
Power Supply for Active Matrix E Ink Vizplex
Panels
EPD Power Supplies
E-Book Readers
EPSON® S1D13522 (ISIS) Timing Controller
EPSON® S1D13521 (Broadsheet) Timing
Controller
Application Processors With Integrated or
Software Timing Controller (OMAP™)
3 Description
The TPS65186 device is a single-chip power supply
designed to for E Ink Vizplex displays used in
portable e-reader applications, and the device
supports panel sizes up to 9.7 inches and greater.
Two high-efficiency DC-DC boost converters
generate ±16-V rails that are boosted to 22 V and
–20 V by two change pumps to provide the gate
driver supply for the Vizplex panel. Two tracking
LDOs create the ±15-V source driver supplies that
support up to 120-mA of output current. All rails are
adjustable through the I2C interface to accommodate
specific panel requirements.
Device Information(1)
PART NUMBER
TPS65186
PACKAGE
VQFN (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
From Input
Supply
(3.0 V-6.0 V)
VIN
TS
Temp
Sensor
VN _SW
VN
Positive
Charge
Pump
LDO1
VDDH_D
VDDH_ DRV
VDDH_FB
VPOS
DCDC2
VCOM
From Input
Supply
(3.0 V-6.0 V)
VCOM
VB_SW
VB
VCOM_ PANEL
DCDC1
LDO2
I/O Control
VCOM
Negative
Charge
Pump
VNEG
VEE_D
VEE_ DRV
VEE_FB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65186
SLVSB04A – JULY 2011 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements: Data Transmission.............. 10
Typical Characteristics ............................................ 12
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 24
8.5 Programming........................................................... 26
8.6 Register Maps ......................................................... 27
9
Application and Implementation ........................ 44
9.1 Application Information............................................ 44
9.2 Typical Application ................................................. 44
10 Power Supply Recommendations ..................... 46
11 Layout................................................................... 46
11.1 Layout Guidelines ................................................. 46
11.2 Layout Example .................................................... 46
12 Device and Documentation Support ................. 47
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
47
47
47
47
47
13 Mechanical, Packaging, and Orderable
Information ........................................................... 47
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2011) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Changed ROUT from “TBD” to “5 Ω” ........................................................................................................................................ 8
2
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SLVSB04A – JULY 2011 – REVISED AUGUST 2015
5 Description (continued)
Accurate back-plane biasing is provided by a linear amplifier that can be adjusted from 0 V to –5.11 V with 9-bit
control through the serial interface; it can also source or sink current depending on panel condition. The
TPS65186 supports automatic panel kickback voltage measurement, which eliminates the need for manual
VCOM calibration in the production line. The measurement result can be stored in nonvolatile memory to become
the new VCOM power-up default value.
TPS65186 is available in a 48-pin 7-mm × 7-mm2 VQFN with 0.5-mm pitch.
6 Pin Configuration and Functions
25 – VN_SW
27 – VIN_P
26 – N/C
28 – VN
29 – VEE_IN
30 – VEE_DRV
31 – VEE_D
32 – VEE_FB
33 – PGND2
34 – VDDH_FB
35 – VDDH_D
36 – VDDH_DRV
RGZ Package
48-Pin VQFN
Top View
VDDH_IN – 37
24 – PWR_GOOD
23 – PBKG
N/C – 38
N/C – 39
22 – PWRUP
VB_SW – 40
21 – N/C
PGND1 – 41
20 – N/C
VB – 42
VPOS_IN – 43
19 – N/C
18 – SDA
VPOS – 44
17 – SCL
VIN3P3 – 45
16 – VCOM_PWR
V3P3 – 46
TS – 47
15 – N/C
14 – VCOM
VCOM_CTRL – 12
N/C – 11
N/C – 9
VIN – 10
AGND1 – 8
INT_LDO – 7
DGND – 6
WAKEUP – 5
VNEG_IN – 4
VNEG – 3
nINT – 2
13 – N/C
VREF – 1
AGND2 – 48
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
AGND1
8
—
Analog ground for general analog circuitry
AGND2
48
—
Reference point to external thermistor and linearization resistor
DGND
6
—
Digital ground. Connect to ground plane.
INT_LDO
7
O
Filter pin for 2.7-V internal supply
nINT
2
O
Open drain interrupt pin (active low)
N/C
9, 11, 13, 15,
19, 20, 21, 26,
38, 39
—
Not internally connected
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TPS65186
SLVSB04A – JULY 2011 – REVISED AUGUST 2015
www.ti.com
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
PBKG
23
—
Die substrate. Connect to VN (–16 V) with short, wide trace. Wide copper trace will
improve heat dissipation.
PGND1
41
—
Power ground for DCDC1
PGND2
33
—
Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps
PWR_GOOD
24
O
Open-drain power good output pin. Pin is pulled low when one or more rails are disabled
or not in regulation. DCDC1, DCDC2, and VCOM have no effect on this pin. (1)
PWRUP
22
I
Power-up pin. Pull this pin high to power up all output rails. (1)
SCL
17
I
Serial interface (I2C) clock input
SDA
18
I/O
TS
47
I
Thermistor input pin. Connect a 10-kΩ NTC thermistor and a 43-kΩ linearization resistor
between this pin and AGND.
V3P3
46
O
Output pin of 3.3-V power switch
VB
42
I
Feedback pin for boost converter (DCDC1) and supply for VPOS LDO and VDDH charge
pump
VB_SW
40
O
Boost converter switch out (DCDC1)
VCOM
14
I
Filter pin for panel common-voltage driver
VCOM_CTRL
12
I
VCOM enable. Pull this pin high to enable the VCOM amplifier. When pin is pulled low
and VN is enabled, VCOM discharge is enabled. (2)
VCOM_PWR
16
I
Internal supply input pin to VCOM buffer. Connect to the output of DCDC2.
VDDH_D
35
O
Base voltage output pin for positive charge pump (CP1)
VDDH_DRV
36
O
Driver output pin for positive charge pump (CP1)
VDDH_FB
34
I
Feedback pin for positive charge pump (CP1)
VDDH_IN
37
I
Input supply pin for positive charge pump (CP1)
VEE_D
31
I
Base voltage output pin for negative charge pump (CP2)
VEE_DRV
30
O
Driver output pin for negative charge pump (CP2)
VEE_FB
32
I
Feedback pin for negative charge pump (CP2)
VEE_IN
29
I
Input supply pin for negative charge pump (CP2) (VEE)
VIN
10
I
Input power supply to general circuitry
VIN3P3
45
I
Input pin to 3.3-V power switch
VIN_P
27
I
Input power supply to inverting buck-boost converter (DCDC2)
VN
28
I
Feedback pin for inverting buck-boost converter (DCDC2) and supply for VNEG LDO and
VEE charge pump
VNEG
3
O
Negative supply output pin for panel source drivers
VNEG_IN
4
I
Input pin for LDO2 (VNEG)
VN_SW
25
O
Inverting buck-boost converter switch out (DCDC2)
VREF
1
O
Filter pin for 2.25-V internal reference to ADC
VPOS
44
O
Positive supply output pin for panel source drivers
VPOS_IN
43
I
Input pin for LDO1 (VPOS)
WAKEUP
5
I
Wake-up pin (active high). Pull this pin high to wake up from sleep mode. IC accepts I2C
commands after WAKEUP pin is pulled high but power rails remain disabled until
PWRUP pin is pulled high. (3)
PowerPad
—
—
PowerPad, internally connected to PBKG. Connect to VN with short, wide trace. Wide
copper trace will improve heat dissipation. PowerPad must not be connected to ground.
(1)
(2)
(3)
4
Serial interface (I2C) data input/output
There will be 0-ns of deglitch for PWRx.
There will be 62.52-µs of deglitch for VCOM_CTRL.
There will be 93.75-µs of deglitch for WAKEUP.
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SLVSB04A – JULY 2011 – REVISED AUGUST 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
Input voltage at VIN (2), VIN_P, VIN3P3
–0.3
7
V
Ground pins to system ground
–0.3
0.3
V
Voltage at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL, VDDH_FB, VEE_FB,
PWR_GOOD, nINT
–0.3
3.6
V
Voltage on VB, VB_SW, VPOS_IN, VDDH_IN
–0.3
20
V
Voltage on VN, VEE_IN, VCOM_PWR, VNEG_IN
–20
0.3
V
Voltage from VIN_P to VN_SW
–0.3
30
V
Peak output current
Internally limited
Continuous total power dissipation
mA
2
W
TJ
Operating junction temperature
–10
125
°C
TA
Operating ambient temperature (3)
–10
85
°C
–65
150
°C
Tstg Storage temperature
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
TI recommends that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad is
electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the buckboost output will help heat dissipated efficiently.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Input voltage at VIN, VIN_P, VIN3P3
3
3.7
6
V
Voltage at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL, VDDH_FB,
VEE_FB, PWR_GOOD, nINT
0
3.6
V
TA
Operating ambient temperature
–10
85
°C
TJ
Operating junction temperature
–10
125
°C
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SLVSB04A – JULY 2011 – REVISED AUGUST 2015
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7.4 Thermal Information
TPS65186
THERMAL METRIC (1)
RGZ [VQFN]
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
30
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
15.6
°C/W
Junction-to-board thermal resistance
6.6
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
6.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
3.7
6
UNIT
INPUT VOLTAGE
VIN
Input voltage range
VUVLO
Undervoltage lockout threshold
VIN falling
2.9
V
V
VHYS
Undervoltage lockout hysteresis
VIN rising
400
mV
mA
INPUT CURRENT
IQ
Operating quiescent current into VIN
Device switching, no load
5.5
ISTD
Operating quiescent current into VIN
Device in standby mode
130
ISLEEP
Shutdown current
Device in sleep mode
3.5
µA
10
µA
INTERNAL SUPPLIES
VINT_LDO
Internal supply
CINT_LDO
Nominal output capacitor
VREF
Internal supply
CREF
Nominal output capacitor
Capacitor tolerance ±10%
1
Capacitor tolerance ±10%
3.3
2.7
V
4.7
µF
2.25
V
4.7
µF
DCDC1 (POSITIVE BOOST REGULATOR)
VIN
Input voltage range
PG
Fraction of nominal output voltage
Power good time-out
Not tested in production
DC set tolerance
IOUT
Output current
RDS(ON)
MOSFET ON-resistance
LDCDC1
Inductor
CDCDC1
Nominal output capacitor
ESR
Output capacitor ESR
(1)
6
ms
V
4.5%
350
–30%
A
30%
1
2.2
1
mA
mΩ
1.5 (1)
Capacitor tolerance ±10%
V
16
250
VIN = 3.7 V
Switch current accuracy
Switching frequency
6
50
–4.5%
Switch current limit
fSW
3.7
90%
Output voltage range
VOUT
ILIMIT
3
Power good threshold
MHz
µH
2 × 4.7
µF
20
mΩ
Contact TI for 1-A, 2-A, or 2.5-A option.
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Electrical Characteristics (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.7
6
UNIT
DCDC2 (INVERTING BUCK-BOOST REGULATOR)
VIN
PG
VOUT
Input voltage range
Fraction of nominal output voltage
Power good time-out
Not tested in production
50
Output current
RDS(ON)
MOSFET ON-resistance
–4.5%
VIN = 3.7 V
350
Inductor
Nominal output capacitor
ESR
Capacitor ESR
–30%
A
30%
4.7
Capacitor tolerance ±10%
1
mA
mΩ
1.5 (1)
Switch current accuracy
CDCDC1
V
4.5%
250
Switch current limit
LDCDC1
ms
–16
DC set tolerance
V
90%
Output voltage range
IOUT
ILIMIT
3
Power good threshold
µH
3x4.7
µF
20
mΩ
LDO1 (VPOS)
VPOS_IN
Input voltage range
15.2
16
16.8
Power good threshold
Fraction of nominal output voltage
Power good time-out
Not tested in production
VSET
Output voltage set value
VIN = 16 V,
VSET[2:0] = 0x3h to 0x6h
VINTERVAL
Output voltage set resolution
VIN = 16 V
VOUTTOL
Output tolerance
VSET = 15 V, ILOAD = 20 mA
VDROPOUT
Dropout voltage
ILOAD = 120 mA
250
VLOADREG
Load regulation – DC
ILOAD = 10% to 90%
1%
ILOAD
Load current range
ILIMIT
Output current limit
CLDO1
Nominal output capacitor
PG
50
14.25
15
ms
15
250
–1%
1%
120
1
V
mV
120
Capacitor tolerance ±10%
V
90%
mV
mA
mA
4.7
µF
LDO2 (VNEG)
VNEG_IN
Input voltage range
16.8
16
–15.2
Power good threshold
Fraction of nominal output voltage
Power good time-out
Not tested in production
VSET
Output voltage set value
VIN = –16 V
VSET[2:0] = 0x3h to 0x6h
VINTERVAL
Output voltage set resolution
VIN = –16 V
VOUTTOL
Output tolerance
VSET = –15 V, ILOAD = –20 mA
VDROPOUT
Dropout voltage
ILOAD = 120 mA
250
VLOADREG
Load regulation – DC
ILOAD = 10% to 90% of ILOAD,MAX
1%
ILOAD
Load current range
ILIMIT
Output current limit
CLDO2
Nominal output capacitor
PG
50
–15
–15
ms
–14.25
250
–1%
mV
120
1
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mV
mA
mA
4.7
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V
1%
120
Capacitor tolerance ±10%
V
90%
µF
7
TPS65186
SLVSB04A – JULY 2011 – REVISED AUGUST 2015
www.ti.com
Electrical Characteristics (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LD01 (POS) AND LDO2 (VNEG) TRACKING
VDIFF
Difference between VPOS and VNEG
VSET = ±15 V,
ILOAD = ±20 mA, 0°C to 60°C
–50
50
mV
VCOM DRIVER
IVCOM
Drive current
Allowed operating range
Accuracy
VCOM
15
mA
Outside this range VCOM is shut down
and VCOMF interrupt is set
–5.5
1
VCOM[8:0] = 0x07Dh
(–1.25 V), VIN = 3.4 V to 4.2 V, no load
–0.8%
0.8%
VCOM[8:0] = 0x07Dh
(–1.25 V), VIN = 3 V to 6 V, no load
–1.5%
1.5%
Output voltage range
–5.11
Resolution
1LSB
Max number of EEPROM writes
VCOM calibration
ROUT
Output impedance
VCOM_CTRL = high, Hi-Z = 0
RIN
Input impedance, HiZ state
HiZ = 1
150
CVCOM
Nominal output capacitor
Capacitor tolerance ±10%
3.3
0
10
V
V
mV
100
Ω
5
MΩ
4.7
µF
CP1 (VDDH) CHARGE PUMP
VDDH_IN
PG
Input voltage range
15.2
Power good threshold
Fraction of nominal output voltage
Power good time-out
Not tested in production
16.8
50
Feedback voltage
VFB
16
ms
0.998
Accuracy
ILOAD = 2 mA
VDDH_OUT
Output voltage range
VSET = 22 V, ILOAD = 2 mA
ILOAD
Load current range
fSW
Switching frequency
CD
Driver capacitor
CO
Output capacitor
V
90%
–2%
21
V
2%
22
23
10
1
V
mA
560
kHz
10
nF
2.2
µF
CP2 (VEE) NEGATIVE CHARGE PUMP
VEE_IN
Input voltage range
PG
16.8
Power good threshold
Fraction of nominal output voltage
Power good time-out
Not tested in production
ILOAD = 2 mA
VEE_OUT
Output voltage range
VSET = –20 V, ILOAD = 3 mA
ILOAD
Load current range
fSW
Switching frequency
CD
Driver capacitor
CO
Nominal output capacitor
–2%
–21
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1
V
2%
–20
560
Capacitor tolerance ±10%
V
ms
–0.994
Accuracy
8
–15.2
50
Feedback voltage
VFB
–16
90%
–19
V
12
mA
kHz
10
nF
2.2
µF
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Product Folder Links: TPS65186
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SLVSB04A – JULY 2011 – REVISED AUGUST 2015
Electrical Characteristics (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN3P3 TO V3P3 SWITCH
RDS(ON)
RDIS
MOSFET ON-resistance
Discharge impedance to ground
VIN3P3 = 3.3 V, ID = 10 mA
Over full temperature range
10.5
VIN3P3 = 2.7 V, ID = 10 mA
Over full temperature range
12.3
V3P3EN = 0
Ω
800
1000
Ω
1200
THERMISTOR MONITOR (2)
ATMS
Temperature to voltage ratio
Not tested in production
OffsetTMS
Offset
Temperature = 0°C
1.575
V
VTMS_HOT
Temp hot trip voltage (T = 50°C)
TEMP_HOT_SET = 0x8C
0.768
V
TEMP_COOL_SET = 0x82
0.845
V
VTMS_COOL Temp hot escape voltage (T = 45°C)
VTMS_MAX
Maximum input level
RNTC_PU
Internal pullup resistor
RLINEAR
External linearization resistor
ADCRES
ADC resolution
Not tested in production, 1 bit
ADCDEL
ADC conversion time
Not tested in production
TMSTTOL
Accuracy
Not tested in production
–0.0161
V/°C
2.25
V
7.307
kΩ
43
kΩ
16.1
mV
19
–1
µs
1
LSB
LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, nINT, PWR_GOOD, PWRUP)
IO = 3 mA, sink current
(SDA, nINT, PWR_GOOD)
VOL
Output low threshold level
VIL
Input low threshold level
VIH
Input high threshold level
I(bias)
Input bias current
VIO = 1.8 V
Deglitch time, WAKEUP pin
Not tested in production
500
Deglitch time, PWRUP pin
Not tested in production
400
tdeglitch
fSCL
V
0.4
V
1
µA
1.2
V
SCL clock frequency
I2C slave address
0.4
µs
400
kHz
0 × 48h (3)
7-bit address
OSCILLATOR
fOSC
Oscillator frequency
Frequency accuracy
9
TA = –40°C to 85°C
–10%
MHz
10%
THERMAL SHUTDOWN
TSHTDWN
Thermal trip point
Thermal hysteresis
(2)
(3)
150
°C
20
°C
10-kΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43 kΩ, 1%) are used at TS pin for panel
temperature measurement.
Contact TI for alternate address of 0 × 68h.
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7.6 Timing Requirements: Data Transmission
VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted)
MIN
f(SCL)
Serial clock frequency
tHD;STA
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
MAX
UNIT
400
kHz
100
tLOW
LOW period of the SCL clock
tHIGH
HIGH period of the SCL clock
tSU;STA
Setup time for a repeated START condition
tHD;DAT
NOM
Data hold time
tSU;DAT
Data setup time
tr
Rise time of both SDA and SCL signals
tf
Fall time of both SDA and SCL signals
tSU;STO
Setup time for STOP condition
tBUF
Bus Free Time Between Stop and Start Condition
tSP
Pulse width of spikes that must be suppressed by
the input filter
Cb
Capacitive load for each bus line
SCL = 100 kHz
4
µs
SCL = 400 kHz
600
ns
SCL = 100 kHz
4.7
SCL = 400 kHz
1.3
µs
SCL = 100 kHz
4
µs
SCL = 400 kHz
600
ns
SCL = 100 kHz
4.7
µs
SCL = 400 kHz
600
SCL = 100 kHz
0
3.45
µs
SCL = 400 kHz
0
900
ns
SCL = 100 kHz
250
SCL = 400 kHz
100
ns
ns
SCL = 100 kHz
1000
SCL = 400 kHz
300
SCL = 100 kHz
300
SCL = 400 kHz
300
ns
ns
SCL = 100 kHz
4
µs
SCL = 400 kHz
600
ns
SCL = 100 kHz
4.7
SCL = 400 kHz
1.3
SCL = 100 kHz
n/a
n/a
SCL = 400 kHz
0
50
µs
SCL = 100 kHz
400
SCL = 400 kHz
400
ns
pF
SDA
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL
tHD;STA
S
tHD;DAT tHIGH
tSU;STA
tSU;STO
Sr
tf
P
S
Figure 1. I2C Data Transmission Timing
10
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VIN
I2C
1.8ms
PWRUP
SLEEP
WAKEUP
STANDBY
ACTIVE
ACTIVE
50ms
VN
VB
DDLY4
UDLY1
UDLY1
VNEG
UDLY2
UDLY2
VEE
DDLY3
UDLY3
UDLY3
VPOS
DDLY2
UDLY4
UDLY4
VDDH
DDLY1
PWR _GOOD
300us (max)
300us (max)
Minimum delay time between WAKEUP rising edge and IC ready to accept I2C transaction.
In this example, the first power-up sequence is started by pulling the PWRUP pin high (rising edge). Power-down is
initiated by pulling the WAKEUP pin low (device enters sleep mode). The second power-up sequence is initiated by
pulling the WAKEUP pin high while the PWRUP pin is also high (power up from sleep to active).
Figure 2. Power-Up and Power-Down Timing Diagram
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7.7 Typical Characteristics
Figure 3. Default Power-Up Sequence
VIN = 3.7 V
Figure 4. Default Power-Down Sequence
CIN = 100 µF
VIN = 5 V
Figure 5. Inrush Current
VIN = 3 V
RLOAD, VPOS = 330 Ω
No Load on VDDH, VEE
Figure 6. Inrush Current
RLOAD,
VNEG
= 330 Ω
VIN = 3 V
Figure 7. Switching Waveforms, VN
12
CIN = 100 µF
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RLOAD, VPOS = 330 Ω
No Load on VDDH, VEE
RLOAD,
VNEG
= 330 Ω
Figure 8. Switching Waveforms, VB
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Typical Characteristics (continued)
RLOAD, VPOS = 330 Ω
No Load on VDDH, VEE
VIN = 3.7 V
RLOAD,
VNEG
= 330 Ω
RLOAD, VPOS = 330 Ω
No Load on VDDH, VEE
VIN = 3.7 V
Figure 9. Switching Waveforms, VN
RLOAD, VPOS = 330 Ω
No Load on VDDH, VEE
VIN = 5 V
RLOAD,
VNEG
= 330 Ω
Figure 10. Switching Waveforms, VB
VNEG
= 330 Ω
RLOAD, VPOS = 330 Ω
No Load on VDDH, VEE
VIN = 5 V
Figure 11. Switching Waveforms, VN
RLOAD,
VNEG
= 330 Ω
Figure 12. Switching Waveforms, VB
50
25
IPO S = INE G
40
IPO S s we ep, IN E G= 15m A
30
20
VPOS + VNEG[mV]
R[W], (VIN3p3-V3P3)/10mA
RLOAD,
15
10
5
IPO S = 15m A , IN EG s w eep
20
10
0
-1 0
-2 0
-3 0
-4 0
0
-5 0
1
1.5
2
2.5
3
3.5
4
0
25
VIN3P3[V]
VIN = 3.7 V
ILOAD,
V3p3
50
75
100
125
1 50
1 75
C u rre n t [m A]
= 10 mA
VIN = 3.7 V
Figure 13. 3p3V Switch Impedance
Figure 14. Source Driver Supply Tracking
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Typical Characteristics (continued)
5
0.2
4
0 .15
3
0.1
DNL[LSB]
INL [mV]
2
1
0
-1
0 .05
0
-0 .05
-2
-0.1
-3
-0 .15
-4
-0.2
-5
0
64
128
192
25 6
320
384
44 8
0
512
64
12 8
1 92
VIN = 3.7 V
RLOAD,
VCOM
2 56
3 20
384
448
512
V CO M C OD E
VC O M C OD E
= 1 kΩ
VIN = 3.7 V
Figure 15. VCOM Integrated Non-Linearity
RLOAD,
VCOM
= 1 kΩ
Figure 16. VCOM Differential Non-Linearity
2
Measurementerror [LSB]
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
640 12 80 192 0 2560 3200 3840 44 80 512 0
F o rce d Kick ba c k Vo lta g e [m V]
VIN = 3.7 V
VIN = 3.7 V
AVG[1:0] = 00 (Single Measurement)
Time from ACQ Bit Set to ACQC Interrupt Received
Figure 17. Kickback Voltage Measurement Error
Figure 18. Kickback Voltage Measurement Timing
VIN = 3.7 V
AVG[1:0] = 11 (Eight Measurements)
Time from ACQ Bit Set to ACQC Interrupt Received
Figure 19. Kickback Voltage Measurement Timing
14
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8 Detailed Description
8.1 Overview
The TPS65186 device provides two adjustable LDOs, inverting buck-boost converter, boost converter, thermistor
monitoring, and flexible power-up and power-down sequencing. The system can be supplied by a regulated input
voltage ranging from 3 V to 6 V. The device is characterized across a –10°C to 85°C temperature range, best
suited for personal electronic applications.
The I2C interface provides comprehensive features for using the TPS65186. All rails can be enabled or disabled.
Power-up and power-down sequences can also be programmed through the I2C interface, as well as thermistor
configuration and interrupt configuration. Voltage adjustment can also be controlled by the I2C interface.
The adjustable LDOs can supply up to 120 mA of current. The default output voltages for each LDO can be
adjusted through the I2C interface. LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of
opposite sign but same magnitude. The sum of VLDO1 and VLOD2 is guaranteed to be less than 50 mV.
There are two charge pumps: VDDH and VEE 10 mA and 12 mA respectively. These charge pumps boost the
DC-DC boost converters ±16-V rails to provide a gate channel supply.
The power good functionality is open-drain output, if any of the four power rails (CP1, CP2, LDO1, LDO2) are not
in regulation, encounters a fault, or is disabled the pin is pulled low. PWR_GOOD remains low if one of the rails
is not enabled by the host and only after all rails are in regulation PWR_GOOD is released to Hi-Z state (pulled
up by external resistor).
The TPS65186 provides circuitry to bias and measure an external NTC to monitor the display panel temperature
in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C to 50°C. Temperature measurement are
triggered by the controlling host and the last temperature reading is always stored in the TMST_VALUE register.
Interrupts are issued when the temperature exceeds the programmable HOT, or drops below the programmable
COLD threshold, or when the temperature has changed by more than a user-defined threshold from the baseline
value.
This device is offered in a 48-Pin, 0.5-mm Pitch, 7 mm × 7 mm × 0.9 mm (VQFN) RGZ package.
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8.2 Functional Block Diagram
10uF
10uF
VIN_P
2.2uH
VB_SW
From Battery
(3.0V-6.0V)
From Battery
(3.0V-6.0V)
4.7uH
4.7uF
PGND1
DCDC1
VN_SW
DCDC2
VB
VN
VEE_IN
VDDH_IN
100n
100n
VDDH_D
VDDH (22V)
VDDH_DRV
1M
2.2uF
10nF
VDDH_FB
VEE_D
VDDH
CHARGE
PUMP
VEE
CHARGE
PUMP
PGND2
VEE_FB
PGND2
PGND2
VDDH_EN
4.7uF
VEE_EN
1M
10nF
2.2uF
52.3k
4.7uF
VPOS_IN
VPOS
VEE (-20V)
VEE_DRV
47.5k
VPOS (15V)
4.7uF
VNEG_IN
LDO1
VNEG
LDO2
VNEG (-15V)
4.7uF
4.7uF
VPOS_EN
VNEG_EN
10k NTC
PBKG
TS
AGND2
43k
TEMP
SENSOR
ADC
VIN
From Input Supply
(3.0V-6.0V)
PowerPad®
TMST_VALUE[7:0]
INT_LDO
INT_LDO
4.7uF
VREF
10uF
VREF
4.7uF
AGND1
4.7uF
VCOM
To panel back -plane
(0 to -5.11 V)
VCOM_CTRL
From uC
DAC
VCOM[8:0]
4.7uF
VCOM_PWR
VIN3P3
V3P3_EN
GATE DRIVER
3.3V supply from system
V3P3
To EPD panel
1k
VIO 10k
From uC
From/to uC or DSP
From uC
From uC
16
VIO 10k
SDA
SCL
PWRUP
WAKEUP
INT
DIGITAL
CORE
PWR_GOOD
10k VIO
10k VIO
To uC
To uC
DGND
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8.3 Feature Description
8.3.1 Wake-Up and Power-Up Sequencing
The power-up and power-down order and timing is defined by user register settings. The default settings support
the E Ink Vizplex panel and typically do not need to be changed.
In SLEEP mode the TPS65186 is completely turned off, the I2C registers are reset, and the device does not
accept any I2C transaction. Pull the WAKEUP pin high with the PWRUP pin low and the device enters STANDBY
mode that enables the I2C interface. Write to the UPSEQ0 register to define the order in which the output rails
are enabled at power-up and to the UPSEQ1 registers to define the power-up delays between rails. Finally, set
the ACTIVE bit in the ENABLE register to 1 to execute the power-up sequence and bring up all power rails.
Alternatively, pull the PWRUP pin high (rising edge).
After the ACTIVE bit has been set, the negative boost converter (VN) is powered up first, followed by the positive
boost (VB). The positive boost enable is gated by the internal power-good signal of the negative boost. Once VB
is in regulation, it issues an internal power-good signal and after delay time UDLY1 has expired, STROBE1 is
issued. The rail assigned to STROBE1 will power up next and after its power-good signal has been asserted and
delay time UDLY2 has expired, STROBE2 is issued. The sequence continues until STROBE4 has occurred and
the last rail has been enabled.
To power down the device, set the STANDBY bit of the ENABLE register to 1 or pull the PWRUP pin low (falling
edge) and the TPS65186 will power down in the order defined by DWNSEQx registers. The delay times DDLY2,
DDLY3, and DDLY4 are weighted by a factor of DFCTR which allows the user to space out the power down of
the rails to avoid crossing during discharge. DFCTR is located in register DWNSEQ1. The positive boost (VB) is
shut down together with the last rail at STROBE4. However, the negative boost (VN) remains up and running for
another 50 ms. Then VN is powered down and the device enters STANDBY or SLEEP mode, depending on the
WAKEUP pin.
If either the ACTIVE bit is set or the PWRUP pin is pulled high while the device is powering down, the powerdown sequence (STROBE1-4) is completed first, followed by a power-up sequence. VB and VN may or may not
be powered down and depending on the relative timing of STROBE4 to the new power-up event.
During power-up, if the STANDBY bit is set or the PWRUP pin is pulled low, the power-up sequence is aborted
and the power-down sequence starts immediately.
8.3.2 Dependencies Between Rails
Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and
several dependencies exist that affect the power-up sequencing. These dependencies are the following:
• Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled.
Internally, DCDC1 enable is gated by DCDC2 power good.
• Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable
is gated DCDC1 power good.
• Positive boost (DCDC1) must be in regulation before VCOM can be enabled. Internally VCOM enable is
gated by DCDC1 power good.
• Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally
CP2 enable is gated by DCDC1 power good.
• Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally
CP1 enable is gated by DCDC1 power good.
• LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power
good.
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Feature Description (continued)
VN PG
VN
powers up
VB PG
VB
powers up
STROBE 1
STROBE 2
STROBE 3
STROBE 4
PG4
UDLY1
ACTIVE bit
or
WAKEUP high
STROBE 1
DDLY1
UDLY2
UDLY3
UDLY4
1st rail
powers up
2 nd rail
powers up
3 nd rail
powers up
STROBE 2
DDLY2
1st rail
powers down
STROBE 3
DDLY3
2 nd rail
powers down
4 th rail
powers up
STROBE 4
DDLY4
3 nd rail
powers down
4 th rail
powers down
50ms
VB
powers down
STANDBY bit
or
WAKEUP low
VN
powers down
TOP: Power-up sequence is defined by assigning strobes to individual rails. STROBE1 is the first strobe to occur after
ACTIVE bit is set and STROBE4 is the last event in the sequence. Strobes are assigned to rails in UPSEQ0 register
and delays between STROBES are defined in UPSEQ1 register.
BOTTOM: Power-down sequence is independent of power-up sequence. Strobes and delay times for power down
sequence are set in DWNSEQ0 and DWNSEQ1 register.
Figure 20. Power-Up and Power-Down Sequence
8.3.3 Soft Start
TPS65186 supports soft start for all rails, that is, inrush current is limited during startup of DCDC1, DCDC2,
LDO1, LDO2, CP1, and CP2. If DCDC1 or DCDC2 are unable to reach power-good status within 50 ms, the
corresponding UV flag is set in the interrupt registers, the interrupt pin is pulled low, and the device enters
STANDBY mode. LDO1, LDO2, positive and negative charge pumps also have a 50-ms power-good time-out
limit. If either rail is unable to power up within 50 ms after it has been enabled, the corresponding UV flag is set
and the interrupt pin is pulled low. However, the device will remain in ACTIVE mode in this case.
8.3.4 VPOS/VNEG Supply Tracking
LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude.
The sum of VLDO1 and VLOD2 is guaranteed to be less than 50 mV.
18
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Feature Description (continued)
8.3.5 V3P3 Power Switch
The integrated power switch is used to cut the 3.3-V supply to the EPD panel and is controlled through the
V3P3_EN pin of the ENABLE register. In SLEEP mode the switch is automatically turned off and its output is
discharged to ground. The default power-up state is OFF. To turn the switch ON, set the V3P3_ENbit to 1.
8.3.6 VCOM Adjustment
VCOM is the output of a power-amplifier with an output voltage range of 0 V to –5.11 V, adjustable in 10-mV
steps. In a typical application VCOM is connected to the VCOM terminal of the EPD panel and the amplifier is
controlled through the VCOM_CTRL pin. With VCOM_CTRL high, the amplifier drives the VCOM pin to the
voltage specified by the VCOM1 and VCOM2 register.
For ease of design, the VCOM_CTRL pin may also be tied to the battery or IO supply. In this case, VCOM is
enabled with STROBE4 during the power-up sequence and disabled on STROBE1 of the power-down sequence.
Therefore VCOM is the last rail to be enabled and the first to be disabled.
8.3.6.1 Kick-Back Voltage Measurement
TPS65186 can perform a voltage measurement on the VCOM pin to deter87/mine the kick-back voltage of the
panel. This allows in-system calibration of VCOM. To perform a kick-back voltage measurement, follow these
steps:
• Pull the WAKEUP pin and the PWRUP pin high to enable all output rails.
• Set the Hi-Z bit in the VCOM2 register. This puts the VCOM pin in a high-impedance state.
• Drive the panel with the Null waveform. Refer to E-Ink specification for detail.
• Set the ACQ bit in the VCOM2 register to 1. This starts the measurement routine.
• When the measurement is complete, the ACQC (Acquisition Complete) bit in the INT1 register is set and the
nINT pin is pulled low.
• The measurement result is stored in the VCOM[8:0] bits of the VCOM1 and VCOM2 register.
The measurement result is not automatically programmed into nonvolatile memory. Changing the power-up
default is described in Storing the VCOM Power-Up Default Value in Memory.
8.3.6.2 Storing the VCOM Power-Up Default Value in Memory
The power-up default value of VCOM can be user-set and programmed into nonvolatile memory. To do so, write
the default value to the VCOM[8:0] bits of the VCOM1 and VCOM2 register, then set the PROG bit in VCOM2
register to 1. First, all power rails are shut down, then the VCOM[8:0] value is committed to nonvolatile memory
such that it becomes the new power-up default. Once programming is complete, the PRGC bit in the INT1
register is set and the nINT pin is pulled low. To verify that the new value has been saved properly, first write the
VCOM[8:0] bits to 0x000h, then pull the WAKEUP pin low. After the WAKEUP pin is pulled back high, read the
VCOM[8:0] bits to verify that the new default value is correct.
VIN
From Input Supply
(3.0 V-6.0 V)
INT_LDO
4.7uF
10uF
4.7uF
To panel back-plane
(-0.5 V to -5.0 V, 15 mA)
From uC
INT_LDO
VREF
VREF
AGND1
4.7uF
VCOM
VCOM_CTRL
DAC
4.7uF
VCOM[8:0]
VCOM_PWR
From VN (-17V)
Figure 21. Block Diagram of VCOM Circuit
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Feature Description (continued)
SETUP
Pull WAKEUP = HIGH
Pull PWRUP= HIGH
Write HiZ = 1
Device enters ACTIVE mode
All power rails are up except VCOM
VCOM pin is in HiZ state
Processor drives panel with NULL waveform
MEASUREMENT
Write ACQ = 1
Wait for ACQC interrupt
Read result from VCOM1/2
registers
VERIFICATION
PROGRAMMING
Pull PWRUP= LOW
Write HiZ = 0
Write PROG= 1
Wait for PRGC interrupt
Starts A/D conversion
Indicates A/D conversion is complete
If AVG[1:0] is 00, interrupt is issed
after all conversions are complete and
average has been calcutated.
Check result and decide to keep the
value or repeat measurment.
Device enters STANDBY mode
Starts the EEPROM programming cycle
.
Power must not be interrupted.
Indicates programming is complete
Pull WAKEUP = LOW
Device enters SLEEP mode
Pull WAKEUP = HIGH
Device enters STANDBY mode
Read VCOM[8:0]
Compare against written value to
confirm new default has been
programmed correctly.
Figure 22. VCOM Calibration Flow
20
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Feature Description (continued)
8.3.7 Fault Handling and Recovery
The TPS65186 monitors input/output voltages and die temperature; the device will take action if operating
conditions are outside normal limits when the following are encountered:
• Thermal Shutdown (TSD)
• Positive Boost Undervoltage (VB_UV)
• Inverting Buck-Boost Undervoltage (VN_UV)
• Input Undervoltage Lockout (UVLO)
The TPS65186 shuts down all power rails and enters STANDBY mode. Shutdown follows the order defined by
DWNSEQx registers. The exception is VCOM fault witch leads to immediate shutdown of all rails. Once a fault is
detected, the PWR_GOOD and nINT pins are pulled low and the corresponding interrupt bit is set in the interrupt
register. Power rails cannot be re-enabled unless the interrupt bits have been cleared by reading the INT1 and
INT2 register. Alternatively, toggling the WAKEUP pin also resets the interrupt bits. As the PWRUP input is edge
sensitive, the host must toggle the PWRUP pin to re-enable the rails through GPIO control, that is, it must bring
the PWRUP pin low before asserting it again. Alternatively rails can be re-enbled through the I2C interface.
Whenever the TPS65186 encounters undervoltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV),
or VDDH (VDDH_UV), rails are not shut down but the PWR_GOOD and nINT is pulled low with the
corresponding interrupt bit set. The device remains in ACTIVE mode and recovers automatically once the fault
has been removed.
8.3.8 Power Good Pin
The power good pin (PWR_GOOD) is an open-drain output that is pulled high (by an external pullup resistor)
when all four power rails (CP1, CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails
encounters a fault or is disabled. PWR_GOOD remains low if one of the rails is not enabled by the host and only
after all rails are in regulation PWR_GOOD is released to Hi-Z state (pulled up by external resistor).
8.3.9 Interrupt Pin
The interrupt pin (nINT) is an open-drain output that is pulled low whenever one or more of the INT1 or INT2 bits
are set. The nINT pin is released (returns to Hi-Z state) and fault bits are cleared once the register with the set bit
has been read by the host. If the fault persists, the nINT pin will be pulled low again after a maximum of 32 µs.
Interrupt events can be masked by re-setting the corresponding enable bit in the INT_EN1 and INT_EN2 register,
that is, the user can determine which events cause the nINT pin to be pulled low. The status of the enable bits
affects the nINT pin only and has no effect on any of the protection and monitoring circuits or the INT1/INT2 bits
themselves.
Persisting faults such as thermal shutdown can cause the nINT pin to be pulled low for an extended period of
time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not desired, set the
corresponding mask bit after receiving the interrupt and keep polling the INT1/INT2 register to see when the fault
condition has disappeared. After the fault is resolved, unmask the interrupt bit again.
8.3.10 Panel Temperature Monitoring
The TPS65186 provides circuitry to bias and measure an external Negative Temperature Coefficient Resistor
(NTC) to monitor the display panel temperature in a range from –10°C to 85°C with and accuracy of ±1°C from
0°C to 50°C. Temperature measurement must be triggered by the controlling host and the last temperature
reading is always stored in the TMST_VALUE register. Interrupts are issued when the temperature exceeds the
programmable HOT, or drops below the programmable COLD threshold, or when the temperature has changed
by more than a user-defined threshold from the baseline value. Details are explained under Hot, Cold, and
Temperature-Change Interrupts.
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Feature Description (continued)
8.3.10.1 NTC Bias Circuit
Figure 23 shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an
internally generated 2.25-V reference voltage through an integrated 7.307-kΩ bias resistor. A 43-kΩ resistor is
connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a
nominal 10-kΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is
digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1.
Table 1. ADC Output Value vs Temperature
TEMPERATURE
TMST_VALUE[7:0]
< –10°C
1111 0110
–10°C
1111 0110
–9°C
1111 0111
...
...
–2°C
1111 1110
–1°C
1111 1111
0°C
0000 0000
1°C
0000 0001
2°C
0000 0010
...
...
25°C
0001 1001
...
85°C
0101 0101
> 85°C
0101 0101
2.25V
7.307k
10
Digital
ADC
TS
43k
10k NTC
AGND2
Figure 23. NTC Bias and Measurement Circuit
A temperature measurement is triggered by setting the READ_THERM bit of the TMST1 register to 1.During the
A/D conversion the CONV_END bit of the TMST1 register reads 0, otherwise it reads 1. At the end of the A/D
conversion the EOC bit in the INT2 register is set and the temperature value is available in the TMST_VALUE
register.
22
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8.3.10.2 Hot, Cold, and Temperature-Change Interrupts
Each temperature acquisition is compared against the programmable TMST_HOT and TMST_COLD thresholds
and to the baseline temperature, to determine if the display is within allowed operating temperature range and if
the temperature has changed by more than a user-defined threshold since the last update. The first temperature
reading after the WAKEUP pin has been pulled high automatically becomes the baseline temperature. Any
subsequent reading is compared against the baseline temperature. If the difference is equal or greater than the
threshold value, an interrupt is issued (DTX bit in register INT1 is set to 1) and the latest value becomes the new
baseline. If the difference is less than the threshold value, no action is taken. The threshold value is defined by
DT[1:0] bits in the TMST1 register and has a default value of ±2°C. In summary:
• When the temperature is equal or less than the TMST_COLD[3:0] threshold, the TMST_COLD interrupt bit of
the INT1 register is set, and the nINT pin is pulled low.
• When the temperature is greater than TMST_COLD but lower then TMST_HOT, no action is taken.
• When the temperature is equal or greater than the TMST_HOT[3:0] threshold, the TMST_HOT interrupt bit of
the INT1 register is set, and the nINT pin is pulled low.
• If the last temperature is different from the baseline temperature by ±2°C (default) or more, the DTX interrupt
bit of the INT1 register is set. The latest temperature becomes the new baseline temperature. By default the
DTX interrupt is disabled, that is, the nINT pin is not pulled low unless the DTX_EN bit was previously set
high.
• If the last temperature change is less than ±2°C (default), no action is taken.
8.3.10.3 Typical Application of the Temperature Monitor
In a typical application the temperature monitor and interrupts are used in the following manner:
• After the WAKEUP pin has been pulled high, the Application Processor (AP) writes 0x80h to the TMST1
register (address 0x0Dh). This starts the temperature measurement.
• The AP waits for the EOC interrupt. Alternatively the AP can poll the CONV_END bit in register TMST1. This
will notify the AP that the A/D conversion is complete and the new temperature reading is available in the
TMST_VALUE register (address (0x00h).
• The AP reads the temperature value from the TMST_VALUE register (address (0x00h).
• If the temperature changes by ±2°C (default) or more from the first reading, the processor is notified by the
DTX interrupt. The A/P may or may not decide to select a different set of waveforms to drive the panel.
• If the temperature is outside the allowed operating range of the panel, the processor is notified by the THOT
and TCOLD interrupts, respectively. The processor may or may not decide to continue with the page update.
• When an overtemperature or undertemperature has been detected, the AP must reset the TMST_HOT_EN or
TMST_COLD_EN bits, respectively, to avoid the nINT pin to be continuously pulled low. The TMST_HOT and
TMST_COLD interrupt bits then must be polled continuously, to determine when the panel temperature
recovers to the normal operating range. Once the temperature has recovered, the TMST_HOT_EN or
TMST_COLD_EN bits must be set to 1 again and normal operation can resume.
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8.4 Device Functional Modes
The TPS65186 has three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the lowestpower mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the device
is ready to accept commands through the I2C interface. In ACTIVE mode one or more power rails are enabled.
8.4.1 SLEEP
This is the lowest power mode of operation. All internal circuitry is turned off, registers are reset to default values
and the device does not respond to I2C communications. TPS65186 enters SLEEP mode whenever WAKEUP
pin is pulled low.
8.4.2 STANDBY
In STANDBY all internal support circuitry is powered up and the device is ready to accept commands through the
I2C interface but none of the power rails are enabled. The device enters STANDBY mode when the WAKEUP pin
is pulled high and either the PWRUP pin is pulled low or the STANDBY bit is set. The device also enters
STANDBY mode if input undervoltage lockout (UVLO), positive boost undervoltage (VB_UV), or inverting buckboost undervoltage (VN_UV) is detected, thermal shutdown occurs, or the PROG bit is set (see Figure 22)
8.4.3 ACTIVE
The device is in ACTIVE mode when any of the output rails are enabled and no fault condition is present. This is
the normal mode of operation while the device is powered up.
8.4.4 Mode Transitions
8.4.4.1 SLEEP → ACTIVE
WAKEUP pin is pulled high with PWRUP pin high. Rails come up in the order defined by the UPSEQx registers
(OK to tie WAKEUP and PWRUP pin together).
8.4.4.2 SLEEP → STANDBY
WAKEUP pin is pulled high with PWRUP pin low. Rails will remain powered down.
8.4.4.3 STANDBY → ACTIVE
WAKEUP pin is high and PWRRUP pin is pulled high (rising edge) or the ACTIVE bit is set. Output rails will
power up in the order defined by the UPSEQx registers.
8.4.4.4 ACTIVE → STANDBY
WAKEUP pin is high and STANDBY bit is set or PWRUP pin is pulled low (falling edge). Rails are shut down in
the order defined by DWNSEQx registers. Device also enters STANDBY in the event of thermal shutdown (TSD),
undervoltage lockout (UVLO), positive boost or inverting buck-boost undervoltage (UV), VCOM fault (VCOMF), or
when the PROG bit is set (see Figure 22).
8.4.4.5 STANDBY → SLEEP
WAKEUP pin is pulled low while none of the output rails are enabled.
8.4.4.6 ACTIVE → SLEEP
WAKEUP pin is pulled low while at least one output rail is enabled. Rails are shut down in the order defined by
DWNSEQx registers.
24
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Device Functional Modes (continued)
POWER DOWN
All rails
= OFF
V3P3 switch = OFF
I2C
= NO
Registers à default
SLEEP
WAKEUP = high &
PWRUP= low
WAKEUP = low
WAKEUP = low
All rails
I2C
STANDBY
WAKEUP = high &
(STANDBY bit = 1||
PWRUP(¯) || FAULT )
= OFF
= YES
WAKEUP = high &
(ACTIVE bit = 1 || PWRUP( ) )
¯
WAKEUP = high & PWRUP = high
Battery removed
ACTIVE
Rails
I2C
= ON
= YES
NOTES:
||, & = logic OR, and AND.
(↑), (↓) = rising edge, falling edge
UVLO = Undervoltage Lockout
TSD = Thermal Shutdown
UV = Undervoltage
FAULT = UVLO || TSD || BOOST UV || VCOM fault
Figure 24. Global State Diagram
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8.5 Programming
8.5.1 I2C Bus Operation
The TPS65186 hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment
addressing and is compliant to I2C standard 3.0.
Slave Address + R/nW
Reg Address
S
A6 A5 A4 A3 A2 A1 A0
S
Start Condition
A
Acknowledge
A6 ... A0 Device Address
Read / not Write
P
Stop Condition
S7 ... S0 Sub-Address
R/nW
R/nW
A
Data
S7 S6 S5 S4 S3 S2 S1 S0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
D7 ... D0 Data
Figure 25. Subaddress in I2C Transmission
The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wire bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bidirectional for data communication between
the controller and the slave terminals. Each device has an open drain output to transmit data on the serial data
line. An external pullup resistor must be placed on the serial data line to pull the drain output high during data
transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 27. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate slave address bits are set for the device, then the device will issue an
acknowledge pulse and prepare to receive the register address. Depending on the R/nW bit, the next byte
received from the master is written to the addressed register (R/nW = 0) or the device responds with 8-bit data
from the register (R/nW = 1). Data transmission is completed by either the reception of a stop condition or the
reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the
SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the
low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and
data words. The I2C interfaces will auto-sequence through register addresses, so that multiple data words can be
sent for a given I2C transmission. See Figure 26 and Figure 27 for details.
S
SLAVE ADDRESS
W A
REG ADDRESS
A
DATA REGADDR
A
DATA SUBADDR +n
A
DATA SUBADDR +n+1
Ā P
A S
SLAVE ADDRESS
R A
DATA REGADDR +n
A
n bytes + ACK
S
SLAVE ADDRESS
W A
REG ADDRESS
DATA REGADDR
DATA REGADDR + n+1
A
Ā P
n bytes + ACK
From master to slave
R Read (high)
S Start
Ā Not Acknowlege
From slave to master
W Write (low)
P Stop
A Acknowlege
TOP: Master writes data to slave.
BOTTOM: Master reads data from slave.
Figure 26. I2C Data Protocol
26
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Programming (continued)
SDA
SCL
1-7
8
9
ADDRESS
R/W
ACK
1-7
8
9
1-7
8
9
S
START
P
DATA
ACK
DATA
ACK/
nACK
STOP
Figure 27. I2C Start/Stop/Acknowledge Protocol
8.6 Register Maps
REGISTER
ADDRESS (HEX)
NAME
DESCRIPTION
0
0x00
TMST_VALUE
Thermistor value read by ADC
1
0x01
ENABLE
Enable/disable bits for regulators
2
0x02
VADJ
VPOS/VNEG voltage adjustment
3
0x03
VCOM1
Voltage settings for VCOM
4
0x04
VCOM2
Voltage settings for VCOM + control
5
0x05
INT_EN1
Interrupt enable group1
6
0x06
INT_EN2
Interrupt enable group2
7
0x07
INT1
Interrupt group1
8
0x08
INT2
Interrupt group2
9
0x09
UPSEQ0
Power-up strobe assignment
10
0x0A
UPSEQ1
Power-up sequence delay times
11
0x0B
DWNSEQ0
Power-down strobe assignment
12
0x0C
DWNSEQ1
Power-down sequence delay times
13
0x0D
TMST1
Thermistor configuration
14
0x0E
TMST2
Thermistor hot temp set
15
0x0F
PG
Power good status each rails
16
0x10
REVID
Device revision ID information
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8.6.1 Thermistor Readout (TMST_VALUE)
Address – 0x00h
DATA BIT
D7
D6
D5
FIELD NAME
D4
D3
D2
D1
D0
TMST_VALUE[7:0]
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FIELD NAME
BIT DEFINITION
Temperature read-out
1111 0110 – < -10°C
1111 0110 – -10°C
1111 0111 – -9°C
...
1111 1110 – -2°C
1111 1111 – -1 °C
TMST_VALUE[7:0]
0000 0000 – 0 °C
0000 0001 – 1°C
0000 0010 – 2°C
...
0001 1001 – 25°C
...
0101 0101 – 85°C
0101 0101 – > 85°C
28
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8.6.2 Enable (ENABLE)
Address – 0x01h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
ACTIVE
STANDBY
V3P3_EN
VCOM_EN
VDDH_EN
VPOS_EN
VEE_EN
VNEG_EN
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
BIT DEFINITION (1)
FIELD NAME
STANDBY to ACTIVE transition bit
ACTIVE
1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by UPSEQx registers
0 – no effect
NOTE: After transition bit is cleared automatically
STANDBY to ACTIVE transition bit
STANDBY
1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by DWNSEQx registers
0 – no effect
NOTE: After transition bit is cleared automatically. STANDBY bit has priority over AVTIVE.
VIN3P3 to V3P3 switch enable
V3P3_EN
1 – switch is ON
0 – switch is OFF
VCOM buffer enable
VCOM_EN
1 – enabled
0 – disabled
VDDH charge pump enable
VDDH_EN
1 – enabled
0 – disabled
VPOS LDO regulator enable
VPOS_EN
1 – enabled
0 – disabled
NOTE: VPOS cannot be enabled before VNEG is enabled.
VEE charge pump enable
VEE_EN
1 – enabled
0 – disabled
VNEG LDO regulator enable
VNEG_EN
1 – enabled
0 – disabled
NOTE: When VNEG is disabled VPOS will also be disabled.
(1)
Enable bits always reflect actual status of the corresponding rail.
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8.6.3 Voltage Adjustment Register (VADJ)
Address – 0x02h
DATA BIT
D7
D6
D5
D4
D3
FIELD NAME
not used
not used
not used
not used
not used
READ/WRITE
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
RESET VALUE
0
0
1
0
0
0E2
1E2
1E2
D2
D1
D0
R/W
R/W
R/W
R/W
1
1
0
1
FIELD NAME
D2
D1
D0
VSET[2:0]
BIT DEFINITION
not used
N/A
not used
N/A
not used
N/A
not used
N/A
not used
N/A
VPOS and VNEG voltage setting
000 - not valid
001 - not valid
010 - not valid
VSET[2:0]
011 - ±15.000 V
100 - ±14.750 V
101 - ±14.500 V
110 - ±14.250 V
111 - reserved
8.6.4 VCOM 1 (VCOM1)
Address – 0x03h
DATA BIT
D7
D6
D5
D4
FIELD NAME
READ/WRITE
RESET VALUE
R/W
E2
0
FIELD NAME
VCOM[7:0]
30
D3
VCOM [7:0]
R/W
E2
1
R/W
E2
1
R/W
E2
1
BIT DEFINITION
VCOM voltage, least significant byte. See VCOM 2 (VCOM2) for details.
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8.6.5 VCOM 2 (VCOM2)
Address – 0x04h
DATA BIT
D7
D6
D5
FIELD NAME
ACQ
PROG
HiZ
READ/WRITE
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
FIELD NAME
D4
D3
D2
D1
D0
not used
not used
VCOM[8]
R/W
R/W
R/W
R/W
0
1
0
0E2
AVG[1:0]
BIT DEFINITION
Kick-back voltage acquisition bit
1 – starts kick-back voltage measurement routine
ACQ
0 – no effect
NOTE: After measurement is complete bit is cleared automatically and measurement result is
reflected in VCOM[8:0] bits.
VCOM programming bit
PROG
1 – VCOM[8:0] value is committed to nonvolatile memory and becomes new power-up default
0 – no effect
NOTE: After programming bit is cleared automatically and TPS65186 will enter STANDBY mode.
VCOM HiZ bit
HiZ
1 – VCOM pin is placed into hi-impedance state to allow VCOM measurement
0 – VCOM amplifier is connected to VCOM pin
Number of acquisitions that is averaged to a single kick-back voltage measurement
00 – 1x
01 – 2x
AVG[1:0]
10 – 4x
11 – 8x
NOTE: When the ACQ bit is set, the state machine repeat the A/D conversion of the kick-back
voltage AVD[1:0] times and returns a single, averaged, value to VCOM[8:0]
not used
N/A
not used
N/A
VCOM voltage adjustment
VCOM = VCOM[8:0] x -10 mV in the range from 0 mV to –5.110 V
0x000h – 0 0000 0000 – –0 mV
0x001h – 0 0000 0001 – –10 mV
VCOM[8:0]
0x002h – 0 0000 0010 – –20 mV
...
0x07Dh - 0 0111 1101 – –1250 mV
...
0x1FEh – 1 1111 1110 – –5100 mV
0x1FFh – 1 1111 1111 – –5110 mV
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8.6.6 Interrupt Enable 1 (INT_EN1)
Address – 0x05h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
TMST_COLD
_EN
UVLO_EN
ACQC_EN
PRGC_EN
FIELD NAME
DTX_EN
TSD_EN
HOT_EN
TMST_HOT
_EN
READ/WRITE
R
R/W
R/W
R/W
R/W
R/W
R
R
RESET VALUE
0
1
1
1
1
1
1
1
BIT DEFINITION (1)
FIELD NAME
Panel temperature-change interrupt enable
DTX_EN
1 – enabled
0 – disabled
Thermal shutdown interrupt enable
TSD_EN
1 – enabled
0 – disabled
Thermal shutdown early warning enable
HOT_EN
1 – enabled
0 – disabled
Thermistor hot interrupt enable
TMST_HOT_EN
1 – enabled
0 – disabled
Thermistor cold interrupt enable
TMST_COLD_EN
1 – enabled
0 – disabled
VIN undervoltage detect interrupt enable
UVLO_EN
1 – enabled
0 – disabled
VCOM acquisition complete interrupt enable
ACQC_EN
1 – enabled
0 – disabled
VCOM programming complete interrupt enable
PRGC_EN
1 – enabled
0 – disabled
(1)
32
Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
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8.6.7 Interrupt Enable 2 (INT_EN2)
Address – 0x06h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
VBUVEN
VDDHUVEN
VNUV_EN
VPOSUVEN
VEEUVEN
VCOMFEN
VNEGUVEN
EOCEN
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1
1
1
1
1
1
1
1
BIT DEFINITION (1)
FIELD NAME
Positive boost converter undervoltage detect interrupt enable
VBUVEN
1 – enabled
0 – disabled
VDDH undervoltage detect interrupt enable
VDDHUVEN
1 – enabled
0 – disabled
Inverting buck-boost converter undervoltage detect interrupt enable
VNUVEN
1 – enabled
0 – disabled
VPOS undervoltage detect interrupt enable
VPOSUVEN
1 – enabled
0 – disabled
VEE undervoltage detect interrupt enable
VEEUVEN
1 – enabled
0 – disabled
VCOM FAULT interrupt enable
VCOMFEN
1 – enabled
0 – disabled
VNEG undervoltage detect interrupt enable
VNEGUVEN
1 – enabled
0 – disabled
Temperature ADC end of conversion interrupt enable
EOCEN
1 – enabled
0 – disabled
(1)
Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
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8.6.8 Interrupt 1 (INT1)
Address – 0x07h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
DTX
TSD
HOT
TMST_HOT
TMST_COLD
UVLO
ACQC
PRGC
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
N/A
N/A
N/A
N/A
N/A
0
0
FIELD NAME
BIT DEFINITION
Panel temperature-change interrupt
DTX
1 – temperature has changed by 3 deg or more over previous reading
0 – no significance
Thermal shutdown interrupt
TSD
1 – chip is in overtemperature shutdown
0 – no fault
Thermal shutdown early warning
HOT
1 – chip is approaching overtemperature shutdown
0 – no fault
Thermistor hot interrupt
TMST_HOT
1 – thermistor temperature is equal or greater than TMST_HOT threshold
0 – no fault
Thermistor cold interrupt
TMST_COLD
1 – thermistor temperature is equal or less than TMST_COLD threshold
0 – no fault
VIN undervoltage detect interrupt
UVLO
1 – input voltage is below UVLO threshold
0 – no fault
VCOM acquisition complete
ACQC
1 – VCOM measurement is compete
0 – no significance
VCOM programming complete
PRGC
1 – VCOM programming is complete
0 – no significance
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8.6.9 Interrupt 2 (INT2)
Address – 0x08h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
VB_UV
VDDH_UV
VN_UV
VPOS_UV
VEE_UV
VCOMF
VNEG_UV
EOC
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FIELD NAME
BIT DEFINITION
Positive boost converter undervoltage detect interrupt
VB_UV
1 – under-voltage on DCDC1 detected
0 – no fault
VDDH undervoltage detect interrupt
VDDH_UV
1 – undervoltage on VDDH charge pump detected
0 – no fault
Inverting buck-boost converter undervoltage detect interrupt
VN_UV
1 – undervoltage on DCDC2 detected
0 – no fault
VPOS undervoltage detect interrupt
VPOS_UV
1 – undervoltage on LDO1(VPOS) detected
0 – no fault
VEE undervoltage detect interrupt
VEE_UV
1 – undervoltage on VEE charge pump detected
0 – no fault
VCOM fault detection
VCOMF
1 – fault on VCOM detected (VCOM is outside normal operating range)
0 – no fault
VNEG undervoltage detect interrupt
VNEG_UV
1 – undervoltage on LDO2(VNEG) detected
0 – no fault
ADC end of conversion interrupt
EOC
1 – ADC conversion is complete (temperature acquisition is complete)
0 – no significance
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8.6.10 Power Up Sequence Register 0 (UPSEQ0)
Address – 0x09h
DATA BIT
D7
FIELD NAME
D6
VDDH_UP[1:0]
D5
D4
D3
VPOS_UP[1:0]
D2
VEE_UP[1:0]
D1
D0
VNEG_UP[1:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1E2
1E2
1E2
0E2
0E2
1E2
0E2
0E2
FIELD NAME
BIT DEFINITION
VDDH power-up order
00 – power up on STROBE1
VDDH_UP[1:0]
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
VPOS power-up order
00 – power up on STROBE1
VPOS_UP[1:0]
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
VEE power-up order
00 – power up on STROBE1
VEE_UP[1:0]
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
VNEG power-up order
00 – power up on STROBE1
VNEG_UP[1:0]
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
6ms
6ms
6ms
6ms
6ms
48ms
VDDH
VPOS
VNEG
VEE
Figure 28. Default Power-Up/Power-Down Sequence
36
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8.6.11 Power Up Sequence Register 1 (UPSEQ1)
Address – 0x0Ah
DATA BIT
FIELD NAME
D7
D6
UDLY4[1:0]
D5
D4
UDLY3[1:0]
D3
D2
UDLY2[1:0]
D1
D0
UDLY1[1:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0E2
1E2
0E2
1E2
0E2
1E2
0E2
1E2
FIELD NAME
BIT DEFINITION
DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power up.
00 – 3 ms
UDLY4[1:0]
01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power up.
00 – 3 ms
UDLY3[1:0]
01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power up.
00 – 3 ms
UDLY2[1:0]
01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY1 delay time set; defines the delay time from VN_PG high to STROBE1 during power up.
00 – 3 ms
UDLY1[1:0]
01 – 6 ms
10 – 9 ms
11 – 12 ms
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8.6.12 Power Down Sequence Register 0 (DWNSEQ0)
Address – 0x0Bh
DATA BIT
D7
D6
D5
D4
D3
D2
D0
VDDH_DWN[1:0]
VPOS_DWN[1:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0E2
0E2
0E2
1E2
1E2
1E2
1E2
0E2
FIELD NAME
VEE_DWN[1:0]
D1
FIELD NAME
VNEG_DWN[1:0]
BIT DEFINITION
VDDH power-down order
00 – power down on STROBE1
VDDH_DWN[1:0]
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
VPOS power-down order
00 – power down on STROBE1
VPOS_DWN[1:0]
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
VEE power-down order
00 – power down on STROBE1
VEE_DWN[1:0]
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
VNEG power-down order
00 – power down on STROBE1
VNEG_DWN[1:0]
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
38
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8.6.13 Power Down Sequence Register 1 (DWNSEQ1)
Address – 0x0Ch
DATA BIT
FIELD NAME
D7
D6
DDLY4[1:0]
D5
D4
DDLY3[1:0]
D3
D2
DDLY2[1:0]
D1
D0
DDLY1
DFCTR
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1E2
1E2
1E2
0E2
0E2
0E2
0E2
0E2
FIELD NAME
BIT DEFINITION
DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power down.
00 – 6 ms
DDLY4[1:0]
01 – 12 ms
10 – 24 ms
11 – 48 ms
DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power down.
00 – 6 ms
DDLY3[1:0]
01 – 12 ms
10 – 24 ms
11 – 4 8ms
DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power down.
00 – 6 ms
DDLY2[1:0]
01 – 12 ms
10 – 24 ms
11 – 48 ms
DLY2 delay time set; defines the delay time from WAKEUP low to STROBE1 during power down.
DDLY1
0 – 3 ms
1 – 6 ms
At power-down delay time DLY2[1:0], DLY3[1:0], DLY4[1:0] are multiplied with DFCTR[1:0]
DFCTR
0 – 1×
1 – 16×
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8.6.14 Thermistor Register 1 (TMST1)
Address – 0x0Dh
DATA BIT
D7
D6
D5
D4
D3
D2
FIELD NAME
READ_THERM
not used
CONV_END
not used
not used
not used
READ/WRITE
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
1
0
0
0
0
0
FIELD NAME
D1
D0
DT[1:0]
BIT DEFINITION
Read thermistor value
READ_THERM
1 – initiates temperature acquisition
0 – no effect
NOTE: Bit is self-cleared after acquisition is completed
not used
N/A
ADC conversion done flag
CONV_END
1 – conversion is finished
0 – conversion is not finished
not used
N/A
not used
N/A
Panel temperature-change interrupt threshold
00 – 2°C
01 – 3°C
DT[1:0]
10 – 4°C
11 – 5°C
DTX interrupt is issued when difference between most recent temperature reading and baseline
temperature is equal to or greater than threshold value. See Hot, Cold, and Temperature-Change
Interrupts for details.
40
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8.6.15 Thermistor Register 2 (TMST2)
Address – 0x0Eh
DATA BIT
D7
FIELD NAME
D6
D5
D4
D3
TMST_COLD[3:0]
D2
D1
D0
TMST_HOT[3:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
1
1
1
1
0
0
0
FIELD NAME
BIT DEFINITION
Thermistor COLD threshold
0000 – -7°C
0001 – -6°C
0010 – -5°C
0011 – -4°C
0100 – -3°C
0101 – -2°C
0110 – -1°C
TMST_COLD [3:0]
0111 – 0°C
1000 – 1°C
1001 – 2°C
1010 – 3°C
1011 – 4°C
1100 – 5°C
1101 – 6°C
1110 – 7°C
1111 – 8°C
NOTE: An interrupt is issued when thermistor temperature is equal or less than COLD threshold
Thermistor HOT threshold
0000 – 42°C
0001 – 43°C
0010 – 44°C
0011 – 45°C
0100 – 46°C
0101 – 47°C
0110 – 48°C
TMST_HOT [3:0]
0111 – 49°C
1000 – 50°C
1001 – 51°C
1010 – 52°C
1011 – 53°C
1100 – 54°C
1101 – 55°C
1110 – 56°C
1111 – 57°C
NOTE: An interrupt is issued when thermistor temperature is equal or greater than HOT threshold
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8.6.16 Power Good Status (PG)
Address – 0x0Fh
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
VB_PG
VDDH_PG
VN_PG
VPOS_PG
VEE_PG
not used
VNEG_PG
not used
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
0
0
0
0
0
0
0
BIT DEFINITION (1)
FIELD NAME
Positive boost converter power good
VB_PG
1 – DCDC1 is in regulation
0 – DCDC1 is not in regulation or turned off
VDDH power good
VDDH_PG
1 – VDDH charge pump is in regulation
0 – VDDH charge pump is not in regulation or turned off
Inverting buck-boost power good
VN_PG
1 – DCDC2 is in regulation
0 – DCDC2 is not in regulation or turned off
VPOS power good
VPOS_PG
1 – LDO1(VPOS) is in regulation
0 – LDO1(VPOS) is not in regulation or turned off
VEE power good
VEE_PG
1 – VEE charge pump is in regulation
0 – VEE charge pump is not in regulation or turned off
not used
N/A
VNEG power good
VNEG_PG
1 – LDO2(VNEG) is in regulation
0 – LDO2(VNEG) is not in regulation or turned off
not used
(1)
42
N/A
PG pin is pulled hi (Hi-Z state) when VDDH_PG = VPOS_PG = VEE_PG = VNEG_PG = 1
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8.6.17 Revision and Version Control (REVID)
Address – 0x10h
DATA BIT
D7
D6
D5
D4
FIELD NAME
D3
D2
D1
D0
REVID[7:0]
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
1
0
0
0E2
1E2
0E2
1E2
FIELD NAME
BIT DEFINITION
REVID[7:6]
MJREV
REVID[5:4]
MNREV
REVID[3:0]
VERSION
0100 0101 - TPS65186 1p0
REVID [7:0]
0101 0101 – TPS65186 1p1
0110 0101 – TPS65186 1p2
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS65186 is used to power display screens in E-book applications, specifically E-Ink Vizplex display, by
connecting the screen to the positive and negative charge pump, LDOs 1 and 2, and VCOM rails. The display
screens size that can be supported up to 9.7 inches.
9.2 Typical Application
VIN
From Input Supply
(3. 0 V-6. 0 V)
TS
TEMP
SENSOR
VN _SW
VDDH_D
VDDH_ DRV
VDDH_FB
POSITIVE
CHARGE
PUMP
VPOS
LDO1
DCDC2
VN
VCOM
VCOM
VB_SW
From Input Supply
(3. 0 V-6. 0 V)
VCOM_ PANEL
DCDC1
VB
VNEG
LDO2
I/ O Control
VCOM
VEE_D
VEE_ DRV
VEE_FB
NEGATIVE
CHARGE
PUMP
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
VOLTAGE
SEQUENCE (STROBE)
VNEG (LDO2)
–15 V
1
VEE (Charge pump 2)
–20 V
2
VPOS (LDO1)
15 V
3
VDDH (Charge pump 1)
22 V
4
44
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9.2.2 Detailed Design Procedure
Table 3. Recommended External Components
PART NUMBER
VALUE
SIZE
MANUFACTURER
LQH44PN4R7MP0
4.7 µH
4 mm × 4 mm × 1.65 mm
Murata
NR4018T4R7M
4.7 µH
4 mm × 4 mm × 1.8 mm
Taiyo Yuden
VLS252015ET-2R2M
2.2 µH
2 mm × 2.5 mm × 1.5 mm
TDK
NR4012T2R2M
2.2 µH
4 mm × 4 mm × 1.2 mm
Taiyo Yuden
GRM21BC81E475KA12L
4.7 µF, 25 V, X6S
805
Murata
GRM32ER71H475KA88L
4.7 µF, 50 V, X7R
1210
Murata
X5R or better
—
—
BAS3010
—
SOD-323
Infineon
MBR130T1
—
SOD-123
ON-Semi
BAV99
—
SOT-23
Fairchild
10 kΩ
603
Murata
INDUCTORS
CAPACITORS
All other capacitors
DIODES
THERMISTOR
NCP18XH103F03RB
100
100
90
90
80
80
70
70
60
V IN= 3. 5
50
V IN= 5V
Efficiency [%]
Efficiency [%]
9.2.3 Application Curves
40
60
VIN= 3. 5
50
VIN= 5V
40
30
30
20
20
10
10
0
0
0
25
50
75
100
125
150
0
175
25
50
T = 25°C
100
125
150
175
T = 25°C
Figure 29. VN DCDC Efficiency
Figure 30. VB DCDC Efficiency
100
100
90
90
VIN=5V
VIN=5V
80
80
VIN=3.5V
VIN=3. 5
70
Efficiency [%]
70
Efficiency [%]
75
Output Current [m A]
Output Current [m A]
60
50
40
60
50
40
30
30
20
20
10
10
0
0
0
2
4
6
8
10
12
0
Output Current [mA]
2
4
6
8
10
12
Output Current [mA]
T = 25°C
T = 25°C
Figure 31. VEE Charge Pump Efficiency
Figure 32. VDDH Charge Pump Efficiency
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10 Power Supply Recommendations
The device is designed to operate with an input voltage supply range from 3 V to 6 V. This input supply can be
from an externally regulated supply. If the input supply is located more than a few inches from the TPS65186,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 10 µF is a typical choice.
11 Layout
11.1 Layout Guidelines
1. PBKG (Die substrate) must connect to VN (–16 V) with short, wide trace. Wide copper trace will improve
heat dissipation.
2. PowerPad is internally connected to PBKG and must not be connected to ground, but connected to VN with
a short wide copper trace.
3. Inductor traces must be kept on the PCB top layer free of any vias.
4. Feedback traces must be routed away from any potential noise source to avoid coupling.
5. Output caps must be placed immediately at output pin.
6. Vin pins must be bypassed to ground with low ESR ceramic bypass capacitors.
11.2 Layout Example
Figure 33. Layout Diagram
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
OMAP, E2E are trademarks of Texas Instruments.
Vizplex is a trademark of E Ink Corporation.
E Ink is a registered trademark of E Ink Corporation.
EPSON is a registered trademark of Seiko Epson Corporation.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65186RGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS65186
TPS65186RGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS65186
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of