TPS736xx-Q1
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SLVSC36 – JUNE 2013
Capacitance-Free NMOS 400-mA Low-Dropout Regulator
Check for Samples: TPS736xx-Q1
•
•
•
2
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following
Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Stable with No Output Capacitor—Any Value
or Type of Capacitor
Input Voltage Range of 1.7 to 5.5 V
Ultra-Low Dropout Voltage: 75 mV typ
Excellent Load-Transient Response—With or
Without Optional Output Capacitor
New NMOS Topology Delivers Low ReverseLeakage Current
Low Noise: 30 μVRMS typ (10 Hz to 100 kHz)
0.5% Initial Accuracy
1% Overall Accuracy Over Line, Load, and
Temperature
Less Than 1 μA max IQ in Shutdown Mode
Thermal Shutdown and Specified Min and Max
Current Limit Protection
Optional
VIN
Optional
IN
VOUT
OUT
TPS736xx-Q1
EN
GND
APPLICATIONS
•
•
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry such as VCOs
DESCRIPTION
The TPS736xx-Q1 family of low-dropout (LDO) linear
voltage regulators uses a new topology: an NMOS
pass element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
The topology also provides high reverse blockage
(low reverse current) and ground pin current that is
nearly constant over all values of output current.
The TPS736xx-Q1 uses an advanced BiCMOS
process to yield high precision while delivering very
low dropout voltages and low ground pin current.
Current consumption, when not enabled, is under 1
μA and ideal for portable applications. The extremely
low output noise (30 μVRMS with 0.1 μF CNR) is ideal
for powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
For all other packages, please contact TI Sales.
DRB PA CKAG E
3mmx 3mm SON
(TOP VIEW)
OUT 1
NR
ON
OFF
Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.2 to 5 V
– Custom Outputs Available
DBV PACKAGE
SOT23
(TOP VIEW)
8 IN
N/C 2
7 N/C
IN
1
NR 3
GND 4
6 N/C
GND
2
EN
3
5 EN
5
OUT
4
NR
Optional
Typical Application Circuit for Fixed-Voltage Versions
DCQ PACKAGE
SOT223
(TOP VIEW)
TAB IS GND
6
1
IN
2
3
4
5
GND
EN
OUT
NR
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2013, Texas Instruments Incorporated
PRODUCT PREVIEW
FEATURES
1
TPS736xx-Q1
SLVSC36 – JUNE 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TPS736xx-Q1
PARAMETER
UNIT
MIN
MAX
VIN range
–0.3
6
V
VEN range
–0.3
6
V
VOUT range
–0.3
5.5
V
VNR range
–0.3
6
V
Peak output current
Internally limited
Output short-circuit duration
Indefinite
Continuous total power dissipation
See Thermal Information Table
PRODUCT PREVIEW
Ambient temperature range, TA
–40
125
°C
Junction temperature range, TJ
–55
150
°C
Storage temperature range
–65
150
°C
2
kV
750
V
Electrostatic discharge
(1)
2
Human body model (HBM)
Charged device model (CDM)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
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SLVSC36 – JUNE 2013
THERMAL INFORMATION
TPS736xx-Q1 (3)
Junction-to-ambient thermal resistance (4)
θJA
(5)
DRB
DCQ
DBV
8 PINS
6 PINS
5 PINS
47.8
70.4
180
64
θJCtop
Junction-to-case (top) thermal resistance
83
70
θJB
Junction-to-board thermal resistance (6)
N/A
N/A
35
ψJT
Junction-to-top characterization parameter (7)
2.1
6.8
N/A
ψJB
Junction-to-board characterization parameter (8)
17.8
30.1
N/A
θJCbot
Junction-to-case (bottom) thermal resistance (9)
12.1
6.3
N/A
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
. ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
. iii. DBV: There is no exposed pad with the DBV package.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
. ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
. iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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PRODUCT PREVIEW
THERMAL METRIC
(1) (2)
TPS736xx-Q1
SLVSC36 – JUNE 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TA = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V (1), IOUT = 10 mA, VEN = 1.7 V, and
COUT = 0.1 μF, unless otherwise noted. Typical values are at TA = +25°C.
PARAMETER
TEST CONDITIONS
VIN
Input voltage range (1) (2)
VREF
Internal reference
Nominal
MIN
TYP
1.7
TA = +25°C
1.198
TA = +25°C
–0.5
1.2
Accuracy (1) (3) over VIN, IOUT,
and T
VOUT + 0.5 V ≤ VIN ≤ 5.5 V;
10 mA ≤ IOUT ≤ 400 mA
ΔVOUT%/ΔVIN
Line regulation
VO(nom) + 0.5 V ≤ VIN ≤ 5.5 V
0.01
1 mA ≤ IOUT ≤ 400 mA
0.002
10 mA ≤ IOUT ≤ 400 mA
0.0005
ΔVOUT%/ΔIOUT Load regulation
VDO
Dropout voltage
(VIN = VOUT(nom) – 0.1 V)
IOUT = 400 mA
ZO(DO)
Output impedance in dropout
1.7 V ≤ VIN ≤ VOUT + VDO
UNIT
5.5
V
1.21
V
+0.5
VOUT
–1
MAX
±0.5
75
+1
%/V
%/mA
200
mV
800
mA
800
mA
Ω
0.25
VOUT = 0.9 × VOUT(nom)
400
3.6 V ≤ VIN ≤ 4.2 V, 0°C ≤ TA ≤ +70°C
500
650
%
PRODUCT PREVIEW
ICL
Output current limit
ISC
Short-circuit current
VOUT = 0 V
450
IREV
Reverse leakage current (4) (–IIN)
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
0.1
IGND
GND pin current
IOUT = 10 mA (IQ)
400
550
IOUT = 400 mA
800
1000
ISHDN
Shutdown current (IGND)
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5,
–40°C ≤ TJ ≤ +100°C
0.02
1
PSRR
Power-supply rejection ratio
(ripple rejection)
f = 100 Hz, IOUT = 400 mA
58
f = 10 kHz, IOUT = 400 mA
37
VN
Output noise voltage
BW = 10 Hz – 100 kHz
COUT = 10 μF, No CNR
27 × VOUT
COUT = 10 μF, CNR = 0.01 μF
8.5 × VOUT
tSTR
Startup time
VEN(HI)
EN pin high (enabled)
1.7
VIN
VEN(LO)
EN pin low (shutdown)
0
0.5
V
IEN(HI)
EN pin current (enabled)
0.1
μA
TSD
Thermal shutdown temperature
TA
Ambient operating temperature
(1)
(2)
(3)
(4)
4
VOUT = 3 V, RL = 30 Ω COUT = 1 μF,
CNR = 0.01 μF
mA
10
0.02
Shutdown, temperature increasing
+160
Reset, temperature decreasing
+140
–40
μA
μA
dB
μVRMS
μs
600
VEN = 5.5 V
μA
V
°C
+125
°C
Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
For VOUT(nom) < 1.6 V, when VIN ≤ 1.6 V, the output will lock to VIN and may result in a damaging overvoltage level on the output. To
avoid this situation, disable the device before powering down the VIN.
Tolerance of external resistors not included in this specification.
Fixed-voltage versions only; refer to APPLICATION INFORMATION section for more information.
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SLVSC36 – JUNE 2013
FUNCTIONAL BLOCK DIAGRAMS
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27kΩ
Bandgap
Error
Amp
Current
Limit
OUT
8kΩ
GND
R1 + R2 = 80kΩ
PRODUCT PREVIEW
R1
R2
NR
Figure 1. Fixed-Voltage Version
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PIN CONFIGURATIONS
IN
1
GND
2
EN
3
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
DCQ PACKAGE
SOT223
(TOP VIEW)
DBV PACKAGE
SOT23
(TOP VIEW)
5
6
OUT
4
TAB IS GND
NR
1
IN
2
3
4
OUT
1
8
IN
N/C
2
7
N/C
NR
GND
3
6
N/C
4
5
EN
5
GND
EN
OUT
NR
PIN DESCRIPTIONS
PRODUCT PREVIEW
6
NAME
SOT23
(DBV)
PIN NO.
SOT223
(DCQ)
PIN NO.
3 × 3 SON
(DRB)
PIN NO.
IN
1
1
8
GND
2
3, 6
4, Pad
DESCRIPTION
Input supply
Ground
EN
3
5
5
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the
regulator into shutdown mode. Refer to the ENABLE PIN AND SHUTDOWN
section under APPLICATION INFORMATION for more details. Connect EN to IN
when not in use.
NR
4
4
3
Fixed voltage versions only—connecting an external capacitor to this pin bypasses
noise generated by the internal bandgap, reducing output noise to very low levels.
OUT
5
2
1
Output of the Regulator. There are no output capacitor requirements for stability.
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TYPICAL CHARACTERISTICS
For all voltage versions, at TA = +25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless
otherwise noted.
LOAD REGULATION
LINE REGULATION
0.20
0.5
Referred to IOUT = 10mA
−40_C
+25_C
+125_ C
0.2
0.1
0
−0.1
−0.2
−0.3
0.10
0
−0.05
−40_ C
−0.10
−0.15
−0.4
−0.20
−0.5
0
50
100
150
200
250
300
350
0
400
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN − VOUT (V)
IOUT (mA)
Figure 2.
Figure 3.
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
100
100
DBV
DBV
IOUT = 400mA
+125° C
80
80
60
VDO(mV)
VDO(mV)
+25_ C
+125_C
0.05
PRODUCT PREVIEW
Change in VOUT (%)
0.3
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
0.15
Change in VOUT (%)
0.4
+25° C
40
─ 40° C
20
60
40
20
0
0
0
50
100
150
200
250
300
350
- 50
400
-25
0
25
50
IOUT(mA)
Temperature (° C)
Figure 4.
Figure 5.
OUTPUT-VOLTAGE ACCURACY HISTOGRAM
75
100
125
OUTPUT-VOLTAGE DRIFT HISTOGRAM
30
18
IOUT = 10mA
16
25
IOUT = 10mA
All Voltage Versions
Percent of Units (%)
Percent of Units (%)
14
20
15
10
12
10
8
6
4
5
2
0
−1.0
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
100
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/_C)
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TA = +25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless
otherwise noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
900
900
800
800
700
700
600
600
I GND (µA)
1000
IGND (µA)
1000
500
400
300
IOUT = 400mA
500
400
300
VIN = 5.5V
VIN = 4V
VIN = 2V
200
100
100
0
0
100
200
300
VIN = 5.5V
VIN = 3V
VIN = 2V
200
0
−50
400
−25
0
IOUT (mA)
50
75
PRODUCT PREVIEW
Figure 8.
Figure 9.
GROUND PIN CURRENT in SHUTDOWN
vs TEMPERATURE
CURRENT LIMIT vs VOUT
(FOLDBACK)
1
100
125
800
VENABLE = 0.5V
VIN = VO + 0.5V
700
Output Current (mA)
IGND (µA)
25
Temperature (_C)
0.1
ICL
600
500
ISC
400
300
200
100
0.01
−50
−25
0
25
50
75
100
0
-0.5
125
0
0.5
Figure 10.
2.0
2.5
3.0
3.5
CURRENT LIMIT vs TEMPERATURE
800
800
750
750
700
700
Current Limit (mA)
Current Limit (mA)
1.5
Figure 11.
CURRENT LIMIT vs VIN
650
600
550
500
450
650
600
550
500
450
400
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
400
−50
VIN (V)
−25
0
25
50
75
100
125
Temperature (_C)
Figure 12.
8
1.0
Output Voltage (V)
Temperature (_C)
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TA = +25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless
otherwise noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN – VOUT
90
40
35
30
IOUT = 1mA
COUT = 10µF
60
50
IO = 100mA
CO = 1µF
IOUT = 1mA
C OUT = Any
40
25
PSRR (dB)
Ripple Rejection (dB)
70
IOUT = 1mA
COUT = 1µF
20
15
30
20
IOUT = Any
COUT = 0µF
10
VIN = VOUT + 1V
0
10
100
1
1k
10k
Frequency = 10kHz
COUT = 10mF
VOUT = 2.5V
IOUT = 100mA
10
I OUT = 100mA
COUT = 10µF
5
0
100k
1M
0
10M
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Frequency (Hz)
VIN - VOUT (V)
Figure 14.
Figure 15.
NOISE SPECTRAL DENSITY
CNR = 0 μF
NOISE SPECTRAL DENSITY
CNR = 0.01 μF
1.8
2.0
PRODUCT PREVIEW
IOUT = 100mA
COUT = Any
80
1
COUT = 0µF
0.1
COUT = 10µF
eN (µV/√Hz)
eN (µV/√Hz)
C OUT = 1µF
COUT = 1µF
0.1
COUT = 0µF
COUT = 10µF
IOUT = 150mA
IOUT = 150mA
0.01
0.01
10
100
1k
10k
100k
10
1k
Frequency (Hz)
Figure 16.
Figure 17.
RMS NOISE VOLTAGE vs COUT
60
100
Frequency (Hz)
10k
100k
RMS NOISE VOLTAGE vs CNR
140
VOUT = 5.0V
50
120
VOUT = 5.0V
100
30
VN (RMS)
VN (RMS)
40
VOUT = 3.3V
80
VOUT = 3.3V
60
20
40
VOUT = 1.5V
10
0
20
CNR = 0.01µF
10Hz < Frequency < 100kHz
0.1
0
1
10
VOUT = 1.5V
COUT = 0µF
10Hz < Frequency < 100kHz
1p
COUT (µF)
10p
100p
1n
10n
CNR (F)
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TA = +25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless
otherwise noted.
TPS736xx-Q1
LOAD-TRANSIENT RESPONSE
VIN = 3.8V
TPS736xx-Q1
LINE-TRANSIENT RESPONSE
COUT = 0µF
100mV/tick
IOUT = 400mA
VOUT
COUT = 0µF
50mV/div
COUT = 1µF
50mV/tick
COUT = 10µF
20mV/tick
VOUT
VOUT
VOUT
COUT = 100µF
50mV/div
VOUT
dVIN
5.5V
400mA
IOUT
50mA/tick
10mA
1V/div
VIN
10µs/div
10µs/div
Figure 20.
Figure 21.
TPS736xx-Q1
TURNON RESPONSE
TPS736xx-Q1
TURNOFF RESPONSE
PRODUCT PREVIEW
RL = 1kΩ
CO UT = 0µF
R L = 20Ω
C OUT = 10µF
VOUT
RL = 20Ω
COUT = 1µF
1V/div
R L = 20Ω
C OUT = 1µF
1V/div
R L = 1kΩ
C OUT = 0µF
RL = 20Ω
COUT = 10µF
VOUT
2V
2V
VEN
1V/div
1V/div
0V
0V
VEN
100µs/div
100µs/div
Figure 22.
Figure 23.
TPS736xx-Q1
POWER UP / POWER DOWN
5
4
IENABLE vs TEMPERATURE
10
6
VIN
VOUT
IENABLE (nA)
3
Volts
= 0.5V/µs
dt
4.5V
2
1
1
0.1
0
−1
−2
50ms/div
0.01
−50
−25
0
25
50
75
100
125
Temperature (_ C)
Figure 24.
10
Figure 25.
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APPLICATION INFORMATION
The TPS736xx-Q1 belongs to a family of new-generation LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse current blockage, and freedom from output-capacitor constraints.
These features, combined with low noise and an enable input, make the TPS736xx-Q1 ideal for portable
applications. This regulator family offers a wide selection of fixed-output-voltage versions. All versions have
thermal and over-current protection, including foldback current limit. Figure 26 shows the basic circuit
connections for the fixed-voltage models.
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
Optional output capacitor.
May improve load transient,
noise, or PSRR.
IN
OUT
VOUT
TPS736xx-Q1
EN
GND
NR
ON
OFF
Optional bypass
capacitor to reduce
output noise.
INPUT AND OUTPUT CAPACITOR REQUIREMENTS
Although an input capacitor is not required for stability, connecting a 0.1- to 1-μF low-ESR capacitor across the
input supply near the regulator is good analog-design practice. This connection counteracts reactive input
sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be
necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the
power source.
The TPS736xx-Q1 does not require an output capacitor for stability, and has maximum phase margin with no
capacitor. The device is designed to be stable for all available types and values of capacitors. In applications
where multiple low-ESR capacitors are in parallel, ringing may occur when the product of COUT and total ESR
drops below 50 nΩF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket,
and solder-joint resistance. In most applications, the sum of capacitor ESR and trace resistance meets this
requirement.
OUTPUT NOISE
A precision band-gap reference generates the internal reference voltage, VREF. This reference is the dominant
noise source within the TPS736xx-Q1 and it generates approximately 32 μVRMS (10 Hz to 100 kHz) at the
reference output (NR). The regulator control-loop gains up the reference noise with the same gain as the
reference voltage, so that the noise voltage of the regulator is approximately given by Equation 1.
VOUT
(R1 ) R2)
V N + 32mVRMS
+ 32mVRMS
R2
VREF
(1)
Since the value of VREF is 1.2 V, this relationship reduces to that shown in Equation 2 for the case of no CNR.
ǒmVV Ǔ
RMS
V N(mVRMS) + 27
V OUT(V)
(2)
An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF,
the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the
approximate relationship as shown in Equation 3 for CNR = 10nF.
ǒmVV Ǔ
V N(mVRMS) + 8.5
RMS
V OUT(V)
(3)
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11
PRODUCT PREVIEW
Figure 26. Typical Application Circuit for Fixed-Voltage Versions
TPS736xx-Q1
SLVSC36 – JUNE 2013
www.ti.com
This noise reduction effect is shown as RMS Noise Voltage vs CNR in the TYPICAL CHARACTERISTICS
section.
Connecting a capacitor, CNR, from the output to the NR pin reduces output noise and improves load transient
performance.
The TPS736xx-Q1 uses an internal charge pump to develop an internal supply voltage sufficient enough to drive
the gate of the NMOS pass element above VOUT. The charge pump generates approximately 250 μV of switching
noise at approximately 4 MHz; however, charge-pump noise contribution is negligible at the output of the
regulator for most values of IOUT and COUT.
BOARD LAYOUT RECOMMENDATION TO IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output noise, and transient response, TI recommends that the board
be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND
pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND
pin of the device.
INTERNAL CURRENT LIMIT
The TPS736xx-Q1 internal current limit helps protect the regulator during fault conditions. Foldback-current limit
helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when
VOUT drops below 0.5 V. See Figure 11 in the TYPICAL CHARACTERISTICS section.
PRODUCT PREVIEW
Note from Figure 11 that approximately –0.2 V of VOUT results in a current limit of 0 mA. Therefore, if OUT is
forced below –0.2 V before EN goes high, the device may not start up. In applications that work with both a
positive and negative voltage supply, the TPS736xx-Q1 must be enabled first.
ENABLE PIN AND SHUTDOWN
The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5 V (max)
turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to shutdown the
regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated VOUT
(see Figure 22).
When shutdown capability is not required, connect EN to VIN. However, the pass gate may not be discharged
using this configuration, and the pass transistor may be left on (enhanced) for a significant time after VIN has
been removed. This scenario results in reverse current flow (if the IN pin is low impedance) and faster ramp
times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output may overshoot
upon power-up.
Note that currentlimit foldback prevents device start-up under some conditions. See the INTERNAL CURRENT
LIMIT section for more information.
DROPOUT VOLTAGE
The TPS736xx-Q1 uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less
than the dropout voltage (VDO), the NMOS pass device is in the linear region of operation and the input-to-output
resistance is the RDS-ON of the NMOS pass element.
For large-step changes in load current, the TPS736xx-Q1 requires a larger voltage drop from VIN to VOUT to avoid
degraded transient response. The boundary of this transient dropout region is approximately twice the dc
dropout. Values of VIN – VOUT above this line ensure normal transient response.
Operating in the transient dropout region causes an increase in recovery time. The time required to recover from
a load transient is a function of the magnitude of the change in load-current rate, the rate-of-change in load
current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale
instantaneous load change with (VIN – VOUT) close to dc dropout levels], the TPS736xx-Q1 takes a couple of
hundred microseconds to return to the specified regulation accuracy.
12
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TPS736xx-Q1
www.ti.com
SLVSC36 – JUNE 2013
TRANSIENT RESPONSE
The low open-loop output impedance provided by the NMOS pass element in a voltage-follower configuration
allows operation without an output capacitor for many applications. As with any regulator, the addition of a
capacitor (nominal value 1 μF) from the OUT pin to ground reduces undershoot-magnitude but increase the
duration. The addition of a capacitor, CNR, from the OUT pin to the NR pin also improves the transient response.
The TPS736xx-Q1 does not have active pull-down when the output is over-voltage which allows applications that
connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output
overshoot of several percent if load current quickly drops to zero when a capacitor is connected to the output.
The duration of overshoot is reduced by adding a load resistor. The overshoot decays at a rate determined by
output capacitor COUT and the internal/external load resistance. The rate of decay is given by Equation 4.
(Fixed Voltage Version)
dVńdt +
C OUT
VOUT
80kW ø R LOAD
(4)
REVERSE CURRENT
After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that
reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There
is additional current flowing into the OUT pin due to the 80-kΩ internal resistor-divider to ground (see Figure 1).
THERMAL PROTECTION
Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing
the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, junction temperature must be limited to +125°C maximum. To estimate the
margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must
trigger at least +35°C above the maximum expected ambient condition of your application which produces a
worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS736xx-Q1 is designed to protect against overload conditions. The
device is not intended to replace proper heat sinking. Continuously running the TPS736xx-Q1 into thermal
shutdown degrades device reliability.
POWER DISSIPATION
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Thermal
Information table. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heat-sink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current times the voltage drop across the output pass element (VIN to VOUT):
P D + (VIN * VOUT) I OUT
(5)
Using the lowest possible input voltage necessary to assure the required output voltage minimizes power
dissipation.
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13
PRODUCT PREVIEW
The NMOS pass element of the TPS736xx-Q1 provides inherent protection against current flow from the output
of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed
from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is
not done, the pass element may be left on due to stored charge on the gate.
TPS736xx-Q1
SLVSC36 – JUNE 2013
www.ti.com
PACKAGE MOUNTING
Solder pad footprint recommendations for the TPS736xx-Q1 are presented in Application Bulletin Solder Pad
Recommendations for Surface-Mount Devices (SBFA015), available from the Texas Instruments Web site at
www.ti.com.
PRODUCT PREVIEW
14
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Product Folder Links: TPS736xx-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS73618QDCQRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOT-223
DCQ
6
2500
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
CU NIPDAU
Level-3-260C-168 HR
(4/5)
-40 to 125
73618Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73618-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2013
• Catalog: TPS73618
• Enhanced Product: TPS73618-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS73618QDCQRQ1
Package Package Pins
Type Drawing
SPQ
SOT-223
2500
DCQ
6
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
7.1
B0
(mm)
K0
(mm)
P1
(mm)
7.45
1.88
8.0
W
Pin1
(mm) Quadrant
12.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS73618QDCQRQ1
SOT-223
DCQ
6
2500
358.0
335.0
35.0
Pack Materials-Page 2
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