TPS7B8450QDCYRQ1M3

TPS7B84-Q1 TPS7B84-Q1 SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 www.ti.com TPS7B84-Q1 150-mA, 40-V, Adjustable, Low-Dropout Regulator 1 Features 3 Description • The TPS7B84-Q1 is a low-dropout linear regulator designed to connect to the battery in automotive applications. The device has an input voltage range extending to 40 V, which allows the device to withstand transients (such as load dump) that are anticipated in automotive systems. With only an 18-µA quiescent current, the device is an optimal solution for powering always-on components such as microcontrollers (MCUs) and controller area network (CAN) transceivers in standby systems. AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA – Junction temperature: –40°C to +150°C, TJ Input voltage range: 3 V to 40 V (42 V max) Output voltage range: – Adjustable output: 1.2 V to 18 V – Fixed output: 3.3 V and 5 V Output current: up to 150 mA Output voltage accuracy: ±0.75% (max) Low dropout voltage: – 225 mV (max) at 150 mA (VOUT ≥ 3.3 V) Low quiescent current: – 18 µA (typ) – 4 µA (max) when disabled Excellent line transient response: – ±2% VOUT deviation during cold-crank – ±2% VOUT deviation (1-V/µs VIN slew rate) Stable with a 2.2-µF or larger capacitor Functional Safety-Capable – Documentation available to aid functional safety system design Package options: – DRB (8-pin VSON), RθJA: 50.8°C/W – DCY (4-pin SOT-223), RθJA: 85.5°C/W • • • • • • • • • • 2 Applications Reconfigurable instrument clusters Body control modules (BCM) Always-on battery-connected applications: – Automotive gateways – Remote keyless entries (RKE) Input Voltage (V) 45 PART NUMBER TPS7B84-Q1 40 35 0.15 30 0.1 25 0.05 20 0 15 -0.05 10 -0.1 5 -0.15 0 500 1000 1500 Time (Ps) 2000 2500 The device is available in both a SOT223 package and a small VSON package with wettable flanks that facilitates a compact printed circuit board (PCB) design. The low thermal resistance enables sustained operation despite significant dissipation across the device. Device Information (1) 0.25 VIN VOUT 0.2 0 The device has state-of-the-art transient response that allows the output to quickly react to changes in load or line (for example, during cold-crank conditions). Additionally, the device has a novel architecture that minimizes output overshoot when recovering from dropout. During normal operation, the device has a tight DC accuracy of ±0.75% over line, load, and temperature. (1) -0.2 3000 PACKAGE BODY SIZE (NOM) VSON (8) 3.00 mm × 3.00 mm SOT-223 (4) 6.50 mm × 3.50 mm For all available packages, see the orderable addendum at the end of the data sheet. IN Output Voltage (V) • • • The TPS7B84-Q1 has both fixed and adjustable output types. The wide output voltage range allows the device to generate the bias voltage for silicon carbide (SiC) gate drivers and microphones as well as power MCUs and processors. EN OUT TPS7B84-Q1 FB GND Typical Application Schematic Line Transient Response (3-V/µs VIN Slew Rate) An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2020 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: TPS7B84-Q1 1 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings ....................................... 4 6.2 ESD Ratings .............................................................. 4 6.3 Recommended Operating Conditions ........................4 6.4 Thermal Information ...................................................5 6.5 Electrical Characteristics ............................................5 6.6 Typical Characteristics................................................ 7 7 Detailed Description......................................................13 7.1 Overview................................................................... 13 7.2 Functional Block Diagrams ...................................... 13 7.3 Feature Description...................................................14 7.4 Device Functional Modes..........................................16 8 Application and Implementation.................................. 17 8.1 Application Information............................................. 17 8.2 Typical Application.................................................... 22 9 Power Supply Recommendations................................23 10 Layout...........................................................................24 10.1 Layout Guidelines................................................... 24 10.2 Layout Examples ................................................... 25 11 Device and Documentation Support..........................26 11.1 Device Support........................................................26 11.2 Receiving Notification of Documentation Updates.. 26 11.3 Support Resources................................................. 26 11.4 Trademarks............................................................. 26 11.5 Electrostatic Discharge Caution.............................. 26 11.6 Glossary.................................................................. 26 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (April 2020) to Revision A (November 2020) Page • Changed document status from advance information to production data.......................................................... 1 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 5 Pin Configuration and Functions IN 1 EN 2 4 GND OUT 1 FB/NC 2 8 IN 7 EN Thermal pad OUT 3 NC 3 6 NC NC 4 5 GND Not to scale Figure 5-1. DCY Package, 4-Pin SOT-223, Top View Not to scale Figure 5-2. DRB Package, 8-Pin VSON, Top View Table 5-1. Pin Functions PIN NAME DCY DRB TYPE(1) DESCRIPTION Enable pin. The device is disabled when the enable pin becomes lower than the enable logic input low level (VIL). To ensure the device is enabled, the EN pin must be driven above the logic high level (VIH). This pin should not be left floating as this pin is high impedance if it is left floating the part may enable or disable. EN 2 7 I GND 4 5 G Ground pin. Connect this pin to the thermal pad with a low-impedance connection. Feedback pin when using an external resistor divider or an NC pin when using the device with a fixed output voltage. When using the adjustable device this pin must be connected through a resistor divider to the output for the device to function. FB/NC — 2 I NC __ 3, 4, 6 __ IN 1 8 No internal connection. Connect these pins to GND for the best thermal performance. I Input power-supply voltage pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground as listed in the Recommended Operating Conditions table and the Input Capacitor section. Place the input capacitor as close to the input of the device as possible. OUT 3 1 O Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground; see the Recommended Operating Conditions table and the Output Capacitor section. Place the output capacitor as close to output of the device as possible. If using a high ESR capacitor, decouple the output with a 100-nF ceramic capacitor. Thermal pad — Pad — Thermal pad. Connect the pad to GND for the best possible thermal performance. See the Layout section for more information. (1) I = input; O = output; G = ground. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 3 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT IN Unregulated input –0.3 42 V EN Enable input –0.3 42 V 0.3(2) V V OUT Regulated output –0.3 FB Feedback –0.3 20 TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) (2) VIN + Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions isnot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability. The absolute maximum rating is VIN + 0.3 V or 20 V, whichever is smaller. 6.2 ESD Ratings VALUE Human-body model (HBM), per AEC V(ESD) (1) Electrostatic discharge Q100-002(1) Charged-device model (CDM), per AEC Q100-011 UNIT ±2000 All pins ±500 Corner pins ±750 V AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN Input voltage 3 40 V VOUT Output voltage 1.2 18 V 0 150 mA 5 kHz IOUT Output current FEN Enable pin frequency(1) VEN High voltage (I/O) COUT Output capacitor(3) ESR Output capacitor ESR requirements(4) CIN Input capacitor(2) 0.1 TJ Operating junction temperature –40 (1) (2) (3) (4) 4 TYP 0 40 V 2.2 220 µF 0.001 2 1 Ω µF 150 °C Minimum pulse time on the EN pin is 100 µs. For robust EMI performance the minimum input capacitance is 500 nF. Effective output capacitance of 1 µF minimum required for stability. If using a large ESR capacitor it is recommended to decouple this with a 100-nF ceramic capacitor to improve transient performance. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 6.4 Thermal Information TPS7B84-Q1 THERMAL METRIC(1) (2) Unit DRB (VSON) DCY 8 PINS 4 PINS Junction-to-ambient thermal resistance(3) 50.8 85.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 55.6 46.6 °C/W RθJB Junction-to-board thermal resistance 22.9 11.3 °C/W ψJT Junction-to-top characterization parameter 1.2 4.9 °C/W ψJB Junction-to-board characterization parameter 22.9 11 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.5 11 °C/W RθJA (1) (2) (3) The thermal data is based on the JEDEC standard high K profile,JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper. The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated. For more information about traditional and new thermal metrics,see the Semiconductor and IC PackageThermal Metrics application report. The 1s0p RθJA is 212.7℃/W for the DRB package and 168.8℃/W for the DCY package. 6.5 Electrical Characteristics specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN = 2 V (unless otherwise noted); typical values are at TJ = 25°C PARAMETER VOUT Regulated output accuracy TEST CONDITIONS VIN = VOUT + 500 mV to 40 V, IOUT = 100 µA to 150 mA (2) TJ = 25ºC VIN = VOUT + 500 mV to 40 V, IOUT = 100 µA to 150 mA (2) (1) VOUT Regulated output accuracy DCY (1) –0.75 0.75 TJ = 25ºC –0.75 0.75 –1 1 TJ = –40°C to +150ºC ΔVOUT(ΔIOUT) ΔVOUT(ΔIOUT) UNIT % % 0.2 % Load regulation Change in percent of output voltage VIN = VOUT + 500 mV, IOUT = 100 µA to 150 mA, VOUT ≥ 3.3 V 0.2 Load regulation (Adjustable output only) VIN = VOUT + 500 mV, Change in percent of output IOUT = 100 µA to 150 voltage mA, VOUT < 3.3 V 0.3 % 100 µs Load transient response settling time(4) (5) IQ MAX TJ = –40°C to +150ºC VIN = VOUT + 500 mV Change in percent of output to 40 V, voltage IOUT = 100 µA ΔVOUT TYP 0.5 Line regulation ΔVOUT(ΔVIN) MIN –0.5 Load transient response overshoot, undershoot(5) Quiescent current COUT = 10 µF COUT = 10 µF VIN = VOUT + 500 mV to 40 V, IOUT = 0 mA (2) IOUT = 500 µA (2) ISHUTDOWN Shutdown supply current (IGND) VDO Dropout voltage (DCY package) VEN = 0 V IOUT = 45 mA to 105 mA –2% IOUT = 0 mA to 150 mA –10% TJ = 25ºC 10% %VOUT 18 21 TJ = –40°C to +150ºC 26 TJ = –40°C to +150ºC 35 TJ = 25ºC 2.5 TJ = –40°C to +150ºC 4 IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95 µA µA 47 IOUT = 105 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 130 180 IOUT = 150 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 160 230 mV Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 5 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 6.5 Electrical Characteristics (continued) specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN = 2 V (unless otherwise noted); typical values are at TJ = 25°C PARAMETER Dropout voltage (fixed output DRB package) VDO TEST CONDITIONS MIN TYP IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95 Dropout voltage adjustable output VFB Feedback voltage IOUT = 105 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 125 175 IOUT = 150 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 155 225 IOUT = 150 mA, VIN = 3 V, VFB = 0.61 V(3) 0.645 Feedback current VUVLO(RISING) Rising input supply UVLO VIN rising 2.6 VUVLO(FALLING) Falling input supply UVLO VIN falling 2.38 VUVLO hysteresis VIL Enable logic input low level Enable logic input high level IEN EN pin current VEN = VIN = 13.5 V ICL Output current limit VIN = VOUT(nom) + 1 V, VOUT short to 90% x VOUT(NOM) PSRR Power-supply ripple rejection VIN - VOUT = 500 mV, frequency = 1 kHz, IOUT = 150 mA Vn Output noise voltage VOUT = 3.3 V, BW = 10 Hz to 100 kHz (1) (2) (3) (4) (5) 245 0.655 V 10 nA 2.7 2.82 V 2.5 2.6 0.7 Hysteresis of thermal shutdown V mV 2 180 mV 175 230 VIH TSD(HYST) 195 0.65 -10 TSD(SHUTDOWN) Junction shutdown temperature 6 140 IFB VUVLO(HYST) mV 43 IOUT = 105 mA, VIN = 3 V, VFB = 0.61 V(3) Reference voltage for FB UNIT 43 Dropout voltage adjustable output IOUT ≤ 1 mA, VIN = 3 V, VFB = 0.61 V(3) DRB package VDO MAX V V 220 50 nA 260 mA 55 dB 280 µVRMS 175 °C 20 °C Power dissipation is limited to 2W for IC production testing purposes. The power dissipation can be higher during normal operation. Please see the thermal dissipation section for more information on how much power the device can dissipate while maintaining a junction temperature below 150℃. For adjustable devices this parameter is tested in unity gain, so resistor divider tolerances and current is not included. Dropout is not measured for VIN ≤ 3 V. The settling time is measured from when IOUT is stepped from 45mA to 105 mA to when the output voltage recovers to VOUT = VOUT(nom) - 5 mV. This specification is specified by design. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 6.6 Typical Characteristics specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN = 2 V (unless otherwise noted) 5.015 0.1 150 mA 100 PA 0.05 0 0qC 25qC 85qC 125qC 150qC 5.005 Output Voltage (V) Accuracy (%) -55qC -40qC 5.01 -0.05 -0.1 -0.15 -0.2 5 4.995 4.99 4.985 -0.25 4.98 -0.3 -60 -40 -20 0 20 40 60 80 Temperature (qC) 4.975 100 120 140 160 5 10 15 20 25 Input Voltage (V) 30 35 40 VOUT = 5 V, IOUT = 150 mA Figure 6-1. Accuracy vs Temperature Figure 6-2. Line Regulation vs VIN 5.015 5.015 -55qC -40qC 5.01 0qC 25qC 85qC 125qC 150qC 5 4.995 4.99 85qC 125qC 150qC 5 4.995 4.99 4.985 4.985 4.98 4.98 4.975 4.975 5 10 15 20 25 Input Voltage (V) 30 35 40 5 10 VOUT = 5 V, IOUT = 5 mA 15 20 25 Input Voltage (V) 30 35 40 VOUT = 5 V, IOUT = 1 mA Figure 6-3. Line Regulation vs VIN Figure 6-4. Line Regulation vs VIN 5.015 5.01 -55qC -40qC 5.01 0qC 25qC 85qC 125qC -40 qC 25 qC 85 qC 150qC 5.0075 5.005 Output Voltage (V) 5.005 Output Voltage (V) 0qC 25qC 5.005 Output Voltage (V) 5.005 Output Voltage (V) -55qC -40qC 5.01 5 4.995 4.99 5.0025 5 4.9975 4.995 4.985 4.9925 4.98 4.99 4.975 0 25 50 75 100 Output Current (mA) 125 150 0 5 10 15 20 25 Input Voltage (V) 30 35 40 COUT = 10 µF VOUT = 5 V Figure 6-5. Load Regulation vs IOUT Figure 6-6. Line Regulation at 50 mA Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 7 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 6.6 Typical Characteristics (continued) specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN = 2 V (unless otherwise noted) 275 5.01 -40 qC 25 qC 85 qC 5.0075 Dropout Voltage (mV) 5.0025 5 4.9975 4.995 150 125 100 75 50 25 0 0 5 10 15 20 25 Input Voltage (V) 30 35 0 40 30 100 90 90 80 70 60 50 40 30 IOUT = 150 mA IOUT = 100 mA IOUT = 50 mA 0 10 100 1k 10k 100k Frequency (Hz) IOUT = 10 mA IOUT = 1mA 1M Power Supply Rejection Ratio (dB) 100 10 70 60 50 40 30 20 2 1 0.5 Noise (PV/—Hz) 2 1 0.5 0.2 0.1 0.05 IOUT 10 mA, 252.5 PVRMS 150 mA, 267.6 PVRMS 10k 100k Frequency (Hz) 1k 10k 100k Frequency (Hz) 1M 10M Figure 6-10. PSRR vs Frequency and VIN 10 5 1k 100 VIN = 10 V VIN = 13.5 V COUT = 10 µF (X7R 50 V), IOUT = 150 mA, VOUT = 5 V 10 5 100 VIN = 5.5 V VIN = 6 V VIN = 7 V 10 Figure 6-9. PSRR vs Frequency and IOUT 0.002 0.001 10 150 80 0 10 10M COUT = 10 µF (X7R 50 V), VOUT = 5 V 0.02 0.01 0.005 120 Figure 6-8. Dropout Voltage (VDO) vs IOUT Figure 6-7. Line Regulation at 100 mA 20 60 90 Output Current (mA) VIN = 3 V COUT = 10 µF Power Supply Rejection Ratio (dB) 150qC 175 4.99 Noise (PV/—Hz) 85qC 125qC 200 4.9925 1M 10M 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10 VOUT = 3.3 V, COUT = 10 µF IOUT 10 mA, 364.8 PVRMS 150 mA, 391.4 PVRMS 100 1k 10k 100k Frequency (Hz) 1M 10M VOUT = 5 V, COUT = 10 µF Figure 6-11. Noise vs Frequency at 3.3 V 8 0qC 25qC 225 5.005 Output Voltage (V) -55qC -40qC 250 Figure 6-12. Noise vs Frequency at 5.0 V Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 6.6 Typical Characteristics (continued) 0.25 VIN VOUT 0.2 35 0.15 0.1 25 0.05 20 0 15 -0.05 10 5 0 500 1000 1500 Time (Ps) 2000 2500 300 VIN VOUT 240 6 180 4 120 2 60 0 0 -2 -60 -4 -120 -0.1 -6 -180 -0.15 -8 -240 -10 -300 500 -0.2 3000 0 -40qC 25qC 150qC IOUT 0 0 -50 -100 -100 -200 -150 AC Coupled Output Voltage (mV) 200 100 -300 1.5 2 2.5 3 Time (ms) 3.5 4 4.5 IOUT 10 60 0 0 -10 -60 -20 -120 -30 -180 -40 -240 -50 -300 80 120 160 Time (Ps) 200 240 280 VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs, VEN = 3.3 V, COUT = 10 µF Figure 6-17. Load Transient, 45 mA to 105 mA 0 -50 -100 -100 -200 20 40 60 80 100 120 Time (Ps) 140 160 180 -300 200 Figure 6-16. Load Transient, No Load to 100-mA Rising Edge 40 120 40 0 50 20 0 100 240 180 IOUT 50 300 30 150qC VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs, VEN = 3.3 V, COUT = 10 µF 200 -40qC AC Coupled Output Voltage (mV) 150qC 25qC 200 0 Output Current (mA) AC Coupled Output Voltage (mV) 50 25qC 450 -150 Figure 6-15. Load Transient, No Load to 100 mA -40qC 400 100 5 VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs, VEN = 3.3 V, COUT = 10 µF 40 350 300 -40qC 50 1 200 250 300 Time (Ps) 150 Output Current (mA) AC Coupled Output Voltage (mV) 300 0.5 150 Figure 6-14. Line Transients at 5.5 V to 6.5 V Figure 6-13. Line Transients at 13.5 V to 40 V 150 0 100 VOUT = 5 V, VIN = 5.5 V to 6.5 V, trise = 1 µs, COUT = 10 µF VOUT = 5 V, IOUT = 1 mA, VIN = 13.5 V to 40 V, slew rate = 2.7 V/µs, VEN = 3.3 V, COUT = 10 µF 100 50 Output Current (mA) 0 8 25qC 150qC IOUT 150 30 100 20 50 10 0 0 -50 -10 -100 -20 -150 -30 -200 -40 0 20 40 60 80 100 120 Time (Ps) 140 160 180 Output Current (mA) 30 10 Input Voltage (V) 40 Output Voltage (V) Input Voltage (V) 45 AC Coupled Output Voltage (mV) specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN = 2 V (unless otherwise noted) -250 200 VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs, VEN = 3.3 V, COUT = 10 µF Figure 6-18. Load Transient, 45-mA to 105-mA Rising Edge Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 9 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 6.6 Typical Characteristics (continued) specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN = 2 V (unless otherwise noted) 200 50 100 0 0 -50 -100 -100 -200 -150 -300 0 0.25 0.5 0.75 1 1.25 Time (ms) 1.5 1.75 300 -40qC AC Coupled Output Voltage (mV) 100 150 150qC IOUT 100 200 50 100 0 0 -50 -100 -100 -200 -150 2 0 VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs, VEN = 3.3 V, COUT = 10 µF 25qC 20 40 60 80 100 120 Time (Ps) 140 160 180 Output Current (mA) 300 -40qC 25qC 150qC IOUT Output Current (mA) AC Coupled Output Voltage (mV) 150 -300 200 VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs, VEN = 3.3 V, COUT = 10 µF Figure 6-19. Load Transient, No Load to 150 mA Figure 6-20. Load Transient, No Load to 150-mA Rising Edge 40 228 -55qC -40qC 227 35 226 0qC 25qC 85qC 125qC 150qC 30 224 Iq (PA) IOUT (mA) 225 223 222 221 25 20 220 219 15 Current Limit 218 -75 -45 -15 15 45 75 Temperature (qC) 105 135 10 5 10 VIN = VOUT + 1 V, VOUT = 90% × VOUT(NOM) 15 20 25 Input Voltage (V) 30 35 40 VOUT = 5 V Figure 6-21. Output Current Limit vs Temperature Figure 6-22. Quiescent Current (IQ) vs VIN 175 450 Iq (PA) 125 125qC 150qC -55 qC -40 qC 0 qC 400 350 Ground Current (PA) -55qC -40qC 0qC 25qC 85qC 150 100 75 50 25 qC 85 qC 125 qC 150 qC 300 250 200 150 100 25 50 0 0 0 5 10 15 20 25 Input Voltage (V) 30 35 40 0 25 50 75 100 Output Current (mA) 125 150 VOUT = 5 V Figure 6-23. Quiescent Current (IQ) vs VIN 10 Figure 6-24. Ground Current (IGND) vs IOUT Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 6.6 Typical Characteristics (continued) specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN = 2 V (unless otherwise noted) 26 281 280 25 Ground Current (PA) Ground Current (PA) 279 278 277 276 275 274 273 24 23 22 272 -50 -25 0 25 50 75 Temperature (qC) 100 125 21 -75 150 -50 -25 0 25 50 75 Ambient Temperature (qC) IOUT = 100 mA 2.8 Falling Threshold Rising Threshold UVLO Threshold (V) EN Threshold (V) 1.32 1.3 1.28 1.26 2.7 2.65 2.6 2.55 2.5 1.24 2.45 1.22 -20 0 20 40 60 80 Temperature (qC) 2.4 -60 100 120 140 160 15 400 Input Voltage Output Voltage Inrush Current 300 10 200 5 100 0 0 -5 200 300 400 500 600 Time (Ps) 700 -100 900 1000 800 -20 0 20 40 60 80 Temperature (qC) 100 120 140 160 20 200 Input Voltage Output Voltage Output Current 15 Inrush Current (mA) Voltage (V) 20 -40 Figure 6-28. Undervoltage Lockout (UVLO) Threshold vs Temperature Voltage (V) -40 Figure 6-27. EN Threshold vs Temperature 100 Falling Threshold Rising Threshold 2.75 1.34 0 150 Figure 6-26. Ground Current 1.38 1.2 -60 125 IOUT = 500 µA Figure 6-25. Ground Current 1.36 100 10 150 100 5 50 0 0 -5 0 1 VIN = 13.5 V, COUT = 10 µF 2 3 4 5 6 Time (ms) 7 8 9 Output Current (mA) 271 -75 -50 10 COUT = 10 µF Figure 6-29. Startup Plot With EN Figure 6-30. Startup Plot Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 11 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 6.6 Typical Characteristics (continued) specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN = 2 V (unless otherwise noted) 20 18 OFF Output voltage (V) 16 14 12 10 ON 8 6 4 0.2 0.4 0.6 0.8 1 1.2 Injected current (mA) 1.4 1.6 1.8 -50 -25 25 50 75 100 125 Temperature (qC) 150 175 200 xx xxx xxxx xxx xxxx xx xxx xxxx xxx xxxx xxx xx xxx xxxx xxx xxxx xxx xx xxx xxxx xxx xxxx xxx xx Figure 6-32. Thermal Shutdown Figure 6-31. Output Voltage vs Injected Current 10 5 2 1 0.5 ESR (:) 0 x 0.2 0.1 0.05 x Stable region 0.02 0.01 0.005 0.002 0.001 0.0005 x 0.0002 0.0001 1 2 3 4 5 6 78 10 20 30 50 70 100 COUT (PF) 200 300 500 Figure 6-33. Stability ESR vs COUT 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 7 Detailed Description 7.1 Overview The TPS7B84-Q1 is a low-dropout linear regulator (LDO) designed to connect to the battery in automotive applications. The device has an input voltage range extending to 40 V, which allows the device to withstand transients (such as load dumps) that are anticipated in automotive systems. With only a 18-µA quiescent current at light loads, the device is an optimal solution for powering always-on components. The device has a state-of-the-art transient response that allows the output to quickly react to changes in the load or line (for example, during cold-crank conditions). Additionally, the device has a novel architecture that minimizes output overshoot when recovering from dropout. During normal operation, the device has a tight DC accuracy of ±0.75% over line, load, and temperature. 7.2 Functional Block Diagrams IN OUT Current Limit ± + Thermal Shutdown UVLO EN FB Bandgap GND Figure 7-1. Adjustable Output Block Diagram IN OUT Current Limit R1 ± + Thermal Shutdown UVLO R2 EN Bandgap GND Figure 7-2. Fixed Output Block Diagram Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 13 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 7.3 Feature Description 7.3.1 Enable (EN) The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the enable pin to the input of the device. 7.3.2 Undervoltage Lockout The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table. 7.3.3 Thermal Shutdown The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (T J) of the pass transistor rises to T SD(shutdown) (typical). Thermal shutdown hysteresis assures that the device resets (turns on) when the temperature falls to TSD(reset) (typical). The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high from large V IN – V OUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before startup completes. For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating Conditions table. Operation above this maximum temperature causes the device to exceed its operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. 7.3.4 Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brickwall current limit, the pass transistor dissipates power [(V IN – V OUT) × I CL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application report. 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 Figure 7-3 shows a diagram of the current limit. VOUT Brickwall VOUT(NOM) IOUT 0V 0 mA IRATED ICL Figure 7-3. Current Limit Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 15 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 7.4 Device Functional Modes 7.4.1 Device Functional Mode Comparison The Device Functional Mode Comparison table shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table for parameter values. Table 7-1. Device Functional Mode Comparison PARAMETER OPERATING MODE VIN VEN IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown) VIN < VUVLO VEN < VEN(LOW) Not applicable TJ > TSD(shutdown) Disabled (any true condition disables the device) 7.4.2 Normal Operation The device regulates to the nominal output voltage when the following conditions are met: • • • The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) • The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to less than the enable falling threshold 7.4.3 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, V IN < V OUT(NOM) + V DO, directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (V OUT(NOM) + V DO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. 7.4.4 Disabled The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Input and Output Capacitor Selection The TPS7B84-Q1 requires an output capacitor of 2.2 µF or larger (1 µF or larger capacitance) for stability and an equivalent series resistance (ESR) between 0.001 Ω and 2 Ω. For the best transient performance, use X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the maximum recommended output capacitance is 220 µF. Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several inches from the input power source. 8.1.2 Adjustable Device Feedback Resistor Selection The adjustable-version device requires external feedback divider resistors to set the output voltage. V OUT is set using the feedback divider resistors, R1 and R2, according to the following equation: VOUT = VFB × (1 + R1 / R2) (1) To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100x the FB pin current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series resistance, as shown in the following equation: R1 + R2 ≤ VOUT / (IFB × 100) (2) 8.1.3 Feed-Forward Capacitor (CFF) For the adjustable-voltage version device, a feed-forward capacitor (C FF) can be connected from the OUT pin to the FB pin. C FF improves transient, noise, and PSRR performance, but is not required for regulator stability. Recommended C FF values are listed in the Recommended Operating Conditions table. A higher capacitance C FF can be used; however, the startup time increases. For a detailed description of C FF tradeoffs, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report. C FF and R 1 form a zero in the loop gain at frequency f Z, while C FF, R 1, and R 2 form a pole in the loop gain at frequency fP. CFF zero and pole frequencies can be calculated from the following equations: fZ = 1 / (2 × π × CFF × R1) (3) fP = 1 / (2 × π × CFF × (R1 || R2)) (4) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 17 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 8.1.4 Dropout Voltage Dropout voltage (V DO) is defined as the input voltage minus the output voltage (V IN – V OUT) at the rated output current (I RATED), where the pass transistor is fully on. I RATED is the maximum I OUT listed in the Recommended Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. RDS(ON) = VDO IRATED (5) 8.1.5 Reverse Current Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. • • • If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, external protection is recommended to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. 8.1.6 Power Dissipation (PD) Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT (6) Note Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. 18 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 The maximum power dissipation determines the maximum allowable ambient temperature (T A) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (R θJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) (7) Thermal resistance (R θJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. 8.1.6.1 Thermal Performance Versus Copper Area The most used thermal resistance parameter, R θJA, is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The R θJA recorded in the Thermal Information table in the Specifications section is determined by the JEDEC standard (see Figure 8-1), PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, R θJA is actually the sum of the package junction-to-case (bottom) thermal resistance (R θJCbot) plus the thermal resistance contribution by the PCB copper. Wire Die Mold Compound Die Attach 2oz Signal Trace Internal Signal or power plane 1oz copper Lead Frame Internal GND plane 1oz copper Thermal Vias Bottom Relief 2oz copper Thermal Pad or Tab of the LDO Figure 8-1. JEDEC Standard 2s2p PCB Figure 8-2 through Figure 8-4 depict the functions of R θJA and ψ JB versus copper area and thickness. These plots are generated with a 101.6-mm x 101.6-mm x 1.6-mm PCB of two and four layers. For the four-layer board, the inner planes use a 1-oz copper thickness. Outer layers are simulated with both a 1-oz and 2-oz copper thickness. A 4 x 4 array of thermal vias of 300-µm drill diameter and 25-µm Cu plating is located beneath the thermal pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper plane of equal area. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS7B84-Q1 19 TPS7B84-Q1 www.ti.com SBVS361A – APRIL 2020 – REVISED NOVEMBER 2020 26 4 4 2 2 105 95 Layer Layer Layer Layer PCB, PCB, PCB, PCB, 1 2 1 2 oz oz oz oz copper copper copper copper 85 75 65 55 45 35 Thermal Resistance -