TPS84320RUQR

Product Folder Order Now Support & Community Tools & Software Technical Documents TPS84320 SLUSAH7B – SEPTEMBER 2011 – REVISED APRIL 2018 TPS84320 4.5-V to 14.5-V Input, 3-A Synchronous Buck, Integrated Power Solution 1 FEATURES 3 DESCRIPTION • The TPS84320RUQ is an easy-to-use integrated power solution that combines a 3-A DC/DC converter with power MOSFETs, an inductor, and passives into a low profile, BQFN package. This total power solution allows as few as 3 external components and eliminates the loop compensation and magnetics design process. 1 • • • • • • • • • • • • • • • • Complete Integrated Power Solution Allows Small Footprint, Low-Profile Design Efficiencies Up To 95% Wide-Output Voltage Adjust 0.8 V to 5.5 V, with 1% Reference Accuracy Optional Split Power Rail Allows Input Voltage Down to 1.6 V Adjustable Switching Frequency (330 kHz to 780 kHz) Synchronizes to an External Clock Adjustable Slow-Start Output Voltage Sequencing / Tracking Power Good Output Programmable Undervoltage Lockout (UVLO) Overcurrent Protection - Hiccup-Mode Over Temperature Protection Pre-bias Output Start-up Operating Temperature Range: –40°C to 85°C Enhanced Thermal Performance: 13°C/W Meets EN55022 Class B Emissions For Design Help Including SwitcherPro™ visit http://www.ti.com/TPS84320 2 APPLICATIONS 100 95 90 85 80 75 70 65 60 55 50 45 40 The TPS84320 offers the flexibility and the featureset of a discrete point-of-load design and is ideal for powering performance DSPs and FPGAs. Advanced packaging technology afford a robust and reliable power solution compatible with standard QFN mounting and testing techniques. SIMPLIFIED APPLICATION PVIN PWRGD VIN VIN CIN TPS84320 VOUT VOUT Broadband & Communications Infrastructure Automated Test and Medical Equipment Compact PCI / PCI Express / PXI Express DSP and FPGA Point of Load Applications High Density Distributed Power Systems Efficiency (%) • • • • • The 9×15×2.8 mm BQFN package is easy to solder onto a printed circuit board and allows a compact point-of-load design with up to 95% efficiency and excellent power dissipation with a thermal impedance of 13°C/W junction to ambient. The device delivers the full 3-A rated output current at 85°C ambient temperature without airflow. RT/CLK SENSE+ INH/UVLO SS/TR COUT VADJ RSET STSEL AGND PGND UDG-10082 VIN = PVIN = 5 V, VOUT = 3.3V, fSW = 630 kHz VIN = PVIN = 12 V, VOUT = 3.3V, fSW = 630 kHz 0 0.5 1 1.5 2 Output Current (A) 2.5 3 G000 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS84320 SLUSAH7B – SEPTEMBER 2011 – REVISED APRIL 2018 www.ti.com Table 1. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com. 4 Specifications 4.1 ABSOLUTE MAXIMUM RATINGS (1) over operating temperature range (unless otherwise noted) Input Voltage Output Voltage VALUE UNIT VIN –0.3 to 16 V PVIN –0.3 to 16 V INH/UVLO –0.3 to 6 V VADJ –0.3 to 3 V PWRGD –0.3 to 6 V SS/TR –0.3 to 3 V STSEL –0.3 to 3 V RT/CLK –0.3 to 6 V PH –1 to 20 V PH 10ns Transient –3 to 20 V VDIFF (GND to exposed thermal pad) –0.2 to 0.2 V ±100 µA PH Current Limit A PH Current Limit A PVIN Current Limit A –0.1 to 5 mA –40 to 125 (2) °C –65 to 150 °C 245 °C RT/CLK Source Current Sink Current PWRGD Operating Junction Temperature Storage Temperature Peak Reflow Case Temperature (3) (4) Maximum Number of Reflows Allowed (3) (4) 3 Mechanical Shock Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted Mechanical Vibration Mil-STD-883D, Method 2007.2, 20-2000Hz (1) (2) (3) (4) 1500 G 20 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. See the temperature derating curves in the Typical Characteristics section for thermal information. For soldering specifications, refer to the Soldering Requirements for BQFN Packages application note. Devices with a date code prior to week 14 2018 (1814) have a peak reflow case temperature of 240°C with a maximum of one reflow. 4.2 THERMAL INFORMATION TPS84320 THERMAL METRIC (1) RUQ47 UNIT 47 PINS θJA Junction-to-ambient thermal resistance (2) 13 (3) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (4) (1) (2) (3) (4) 2 2.5 °C/W 5 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm double-sided PCB with 1 oz. copper and natural convection cooling. Additional airflow reduces θJA. The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1mm from the device. Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated Product Folder Links: TPS84320 TPS84320 www.ti.com SLUSAH7B – SEPTEMBER 2011 – REVISED APRIL 2018 4.3 PACKAGE SPECIFICATIONS TPS84320 Weight Flammability MTBF Calculated reliability UNIT 1.26 grams Meets UL 94 V-O Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign 40.1 MHrs Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated Product Folder Links: TPS84320 3 TPS84320 SLUSAH7B – SEPTEMBER 2011 – REVISED APRIL 2018 4.4 www.ti.com ELECTRICAL CHARACTERISTICS Over -40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 3A, CIN1 = 2x 22 µF ceramic, CIN2 = 68 µF poly-tantalum, COUT1 = 4x 47 µF ceramic (unless otherwise noted) PARAMETER TEST CONDITIONS IOUT Output current TA = 85°C, natural convection VIN Input bias voltage range PVIN Input switching voltage range UVLO VIN Undervoltage lockout VOUT(adj) VOUT A 4.5 14.5 V Over IOUT range 1.6 (1) 14.5 V VIN = increasing 4.0 3.5 Output voltage adjust range Over IOUT range 0.8 Set-point voltage tolerance TA = 25°C, IOUT = 0A Temperature variation -40°C ≤ TA ≤ +85°C, IOUT = 0A ±0.3% Line regulation Over PVIN range, TA = 25°C, IOUT = 0A ±0.1% Load regulation Over IOUT range, TA = 25°C ±0.1% Total output voltage variation Includes set-point, line, load, and temperature variation PVIN = VIN = 5 V IO = 1.5 A VINH-H VINH-L II(stby) Inhibit Control VOUT = 3.3V, fSW = 630kHz 89.0 % VOUT = 2.5V, fSW = 480kHz 86.9 % VOUT = 1.8V, fSW = 480kHz 85.2 % VOUT = 1.2V, fSW = 480kHz 82.1 % VOUT = 0.8V, fSW = 330kHz 78.7 % VOUT = 3.3V, fSW = 630kHz 93.3 % VOUT = 2.5V, fSW = 480kHz 91.4 % VOUT = 1.8V, fSW = 480kHz 88.8 % VOUT = 1.2V, fSW = 480kHz 85.2 % VOUT = 0.8V, fSW = 330kHz 81.8 % 1.0 A/µs load step from 50 to 100% IOUT(max) A VOUT over/undershoot 35 –0.3 -1.15 INH > 1.26 V -3.4 Input standby current INH pin to AGND 2 VOUT falling Over VIN and IOUT ranges, RT/CLK pin OPEN fCLK Synchronization frequency VCLK-H CLK High-Level Threshold VCLK-L CLK Low-Level Threshold DCLK CLK Duty cycle CLK Control Good 94% Fault 109% Fault 91% Good 106% Thermal shutdown hysteresis V μA μA 4 µA 0.3 V 390 kHz 330 780 kHz 2.0 5.5 V 0.8 V 270 330 20% Thermal shutdown (3) 1.05 INH < 1.1 V PWRGD Thresholds mV Open INH Hysteresis current I(PWRGD) = 2 mA mVPP µs 1.30 Switching frequency 4 (2) 190 Inhibit Low Voltage PWRGD Low Voltage (3) ±1.5% V Recovery time Inhibit High Voltage fSW (1) (2) (2) 35 INH Input current Thermal Shutdown ±1.0% V 5.8 VOUT rising Power Good 5.5 91.5 % 20 MHz bandwith 4.5 3.85 VOUT = 5V, fSW = 780kHz Overcurrent threshold Transient response UNIT Over IOUT range VIN = decreasing Output voltage ripple MAX 3 Efficiency ILIM TYP 0 PVIN = VIN = 12 V IO = 1.5 A η MIN 160 80% 175 °C 10 °C The minimum PVIN voltage is 1.6V or (VOUT+ 0.7V) , whichever is greater. VIN must be greater than 4.5V. The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor. This control pin has an internal pullup. If this pin is left open circuit, the device operates when input power is applied. A small lowleakage ( 4.5 V VIN PVIN RUVLO1 INH/UVLO RUVLO2 Figure 42. Adjustable PVIN Undervoltage Lockout, (VIN ≥4.5 V) Table 11. Standard Resistor Values for Adjusting PVIN UVLO, (VIN ≥4.5 V) PVIN UVLO (V) 24 2.0 2.5 3.0 3.5 4.0 4.5 RUVLO1 (kΩ) 68.1 68.1 68.1 68.1 68.1 68.1 RUVLO2 (kΩ) 95.3 60.4 44.2 34.8 28.7 24.3 Hysteresis (mV) 300 315 335 350 365 385 Submit Documentation Feedback For higher PVIN UVLO voltages see Table UV for resistor values Copyright © 2011–2018, Texas Instruments Incorporated Product Folder Links: TPS84320 TPS84320 www.ti.com SLUSAH7B – SEPTEMBER 2011 – REVISED APRIL 2018 9.16 Thermal Shutdown The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C typically. 9.17 Layout Considerations To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 43, shows a typical PCB layout. Some considerations for an optimized layout are: • Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress. • Place ceramic input and output capacitors close to the module pins to minimize high frequency noise. • Locate additional output capacitors between the ceramic capacitor and the load. • Place a dedicated AGND copper area beneath the TPS84320. • Isolate the PH copper area from the VOUT copper area using the AGND copper area. • Connect the AGND and PGND copper area at one point; near the output capacitors. • Place RSET, RRT, and CSS as close as possible to their respective pins. • Use multiple vias to connect the power planes to internal layers. VOUT SENSE+ Via COUT2 COUT1 PGND RRT CIN1 CIN2 AGND PH RSET VIN/PVIN SENSE+ Via CSS Figure 43. Typical Recommended Layout Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated Product Folder Links: TPS84320 25 TPS84320 SLUSAH7B – SEPTEMBER 2011 – REVISED APRIL 2018 www.ti.com 9.18 EMI The TPS84320 is compliant with EN55022 Class B radiated emissions. Figure 44 and Figure 45 show typical examples of radiated emissions plots for the TPS84320 operating from 5V and 12V respectively. Both graphs include the plots of the antenna in the horizontal and vertical positions. Figure 44. Radiated Emissions 5-V Input, 1.2-V Output, 3-A Load (EN55022 Class B) 26 Figure 45. Radiated Emissions 12-V Input, 1.2-V Output, 3A Load (EN55022 Class B) Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated Product Folder Links: TPS84320 TPS84320 www.ti.com SLUSAH7B – SEPTEMBER 2011 – REVISED APRIL 2018 10 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (June 2017) to Revision B • Page Increased the peak reflow temperature and maximum number of reflows to JEDEC specification for improved manufacturability..................................................................................................................................................................... 2 Changes from Original (September 2011) to Revision A • Page Added peak reflow and maximum number of reflows information ........................................................................................ 2 Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated Product Folder Links: TPS84320 27 TPS84320 SLUSAH7B – SEPTEMBER 2011 – REVISED APRIL 2018 www.ti.com 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks SwitcherPro, E2E are trademarks of Texas Instruments. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated Product Folder Links: TPS84320 TPS84320 www.ti.com SLUSAH7B – SEPTEMBER 2011 – REVISED APRIL 2018 12.1 Tape and Reel Information REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TPS84320RUQR B1QFN RUQ 47 500 330.0 24.4 9.35 15.35 3.1 16.0 24.0 Q1 TPS84320RUQT B1QFN RUQ 47 250 330.0 24.4 9.35 15.35 3.1 16.0 24.0 Q1 Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated Product Folder Links: TPS84320 29 TPS84320 SLUSAH7B – SEPTEMBER 2011 – REVISED APRIL 2018 www.ti.com TAPE AND REEL BOX DIMENSIONS Width (mm) L W 30 H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS84320RUQR B1QFN RUQ 47 500 383.0 353.0 58.0 TPS84320RUQT B1QFN RUQ 47 250 383.0 353.0 58.0 Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated Product Folder Links: TPS84320 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPS84320RUQR ACTIVE B1QFN RUQ 47 500 RoHS Exempt & Green NIPDAU Level-3-245C-168 HR -40 to 85 TPS84320 TPS84320RUQT ACTIVE B1QFN RUQ 47 250 RoHS Exempt & Green NIPDAU Level-3-245C-168 HR -40 to 85 TPS84320 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of