TPSM82864A, TPSM82866A
SLUSEF1B – SEPTEMBER 2021 – REVISED NOVEMBER 2022
TPSM82864A, TPSM82866A 2.4-V to 5.5-V Input, 4-A/6-A Step-Down Power Module
with an Integrated Inductor in a 3.5-mm × 4.0-mm Thin Overmolded QFN Package
1 Features
3 Description
•
•
•
•
•
•
•
•
The TPSM8286xA device family consists of 4-A and
6-A step-down converter power modules optimized
for small solution size and high efficiency. The
power modules integrate a synchronous step-down
converter and an inductor to simplify design, reduce
external components, and save PCB area. The lowprofile and compact solution is suitable for automated
assembly by standard surface mount equipment.
2 Applications
•
•
•
•
•
•
Core supply for FPGAs, CPUs, ASICs
Optical modules
Medical imaging
Industrial transport
Factory automation and control
Aerospace and defense
Tight output voltage accuracy, even with small
output capacitors, is achieved though the DCSControl architecture and its excellent load transient
performance. At medium-to-heavy loads, the
converter operates in PWM mode and automatically
enters Power save mode operation at light load to
maintain high efficiency over the entire load current
range. The devices can also be forced in PWM mode
operation for the smallest output voltage ripple.
The EN and PG pins, which support sequencing
configurations, bring a flexible system design. An
integrated soft start reduces the inrush current
required from the input supply. Overtemperature
protection and hiccup short-circuit protection deliver
a robust and reliable solution.
Device Information
PART
NUMBER
4A
TPSM82866A
6A
(1)
VIN
2.4 V to 5.5 V
C1
22 µF
EN
VPG
PG
VSET/
MODE
AGND
PGND
RDJ or RDM
(B0QFN, 23)
3.50 mm ×
4.00 mm
95
90
C2
2 × 22 µF or
1 × 47 µF
VOS
FB
BODY SIZE
(NOM)
100
VOUT
R3
PACKAGE(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
VOUT
1.8 V
VIN
OUTPUT
CURRENT
TPSM82864A
85
Efficiency (%)
•
•
•
•
•
•
•
•
•
•
•
Up to 96% efficiency
Excellent thermal performance
CISPR-11 class-B compliant
1% output voltage accuracy
DCS-Control topology for fast transient response
1.4-mm or 1.8-mm ultra-low profile QFN package
2.4-V to 5.5-V input voltage range
Same device part number provides either:
– 0.6-V to VIN adjustable output voltage
– 13 integrated fixed output voltage options
Power-good indicator with window comparator
2.4-MHz switching frequency
Forced PWM or power save mode
4-µA operating quiescent current
Output voltage discharge
100% duty cycle mode
Hiccup short-circuit protection
Thermal shutdown
–40°C to 125°C operating temperature range
3.5-mm × 4.0-mm QFN package with 0.5-mm pitch
35-mm2 solution size
80
75
70
65
60
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
55
R4
133 kΩ
50
45
40
100u
Typical Application Schematic – Fixed Output
Voltage Option
FPWM
PSM
1m
10m
100m
Output Current (A)
1
6
TPSM82866AA0HRDMR – Efficiency Versus Output
Current; VIN = 5.0 V
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPSM82864A, TPSM82866A
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SLUSEF1B – SEPTEMBER 2021 – REVISED NOVEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes..........................................12
9 Application and Implementation.................................. 14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
9.3 Power Supply Recommendations.............................21
9.4 Layout....................................................................... 21
10 Device and Documentation Support..........................24
10.1 Device Support....................................................... 24
10.2 Documentation Support.......................................... 24
10.3 Receiving Notification of Documentation Updates..24
10.4 Support Resources................................................. 24
10.5 Trademarks............................................................. 24
10.6 Electrostatic Discharge Caution..............................24
10.7 Glossary..................................................................24
11 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2021) to Revision B (November 2022)
Page
• Added TPSM8286xAA0HRDM to the data sheet............................................................................................... 3
Changes from Revision * (September 2021) to Revision A (December 2021)
Page
• Changed document status from Advance Information to Production Data.........................................................1
2
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5 Device Options
ORDERABLE PART NUMBER
DEVICE HEIGHT
TPSM82864AA0SRDJR
1.4 mm
TPSM82864AA0HRDMR
1.8 mm
TPSM82866AA0SRDJR
1.4 mm
TPSM82866AA0HRDMR
1.8 mm
OUTPUT CURRENT
4A
6A
6 Pin Configuration and Functions
VOUT
14
Exposed
Thermal
Pad
10
11
6
PGND
PGND
6
5
PGND
PGND
5
Exposed
Thermal
Pad
VOUT
14
VOUT
VOS
PG
PG
2
17
EN
EN
1
22
21
20
19
PGND
1
VSET/MODE
EN
22
VOUT
16
EN
21
15
3
PGND
2
20
4
VIN
17
19
PGND
VIN
VSET/MODE
FB
VIN
VOS
VIN
PGND
3
PGND
4
16
PGND
15
AGND
13
23
VOUT
18
12
VOUT
23
AGND
VOUT
9
18
FB
AGND
AGND
13
8
SW
SW
VOUT
PGND
7
7
PGND
8
PGND
9
SW
PGND
10
VOUT
PGND
PGND
11
SW
PGND
12
BOTTOM VIEW
PGND
VOUT
TOP VIEW
Figure 6-1. TPSM82864A, TPSM82866A - QFN (23 Pin)
Table 6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
AGND
18
P
Analog ground pin. Must be connected to a common GND plane.
EN
1
I
Device enable pin. To enable the device, this pin must be pulled high. Pulling this pin low
disables the device. Do not leave floating.
FB
17
I
Voltage feedback input. Connect the output voltage resistor divider to this pin. When using a
fixed output voltage, connect directly to VOUT.
PG
2
O
Power-good open-drain output pin. The pullup resistor can be connected to voltages up to 5.5 V.
If unused, leave this pin floating. This pin is pulled to GND when the device is in shutdown.
PGND
4, 5, 6, 8, 9,
10, 11, 19, 20
P
Power ground pin. Must be connected to common GND plane.
SW
7
O
Switch pin of the power stage. This pin can be left floating.
VIN
21, 22
P
Power supply input voltage pin
VOS
16
I
Output voltage sense pin. This pin must be directly connected to the output capacitor.
VOUT
12, 13, 14, 15
P
Output voltage pin
VSET/MODE
3
I
Connecting a resistor to GND selects one of the fixed output voltages. Tying the pin high or
low selects an adjustable output voltage. After the device has started up, the pin operates as a
MODE input. Applying a high level selects forced PWM mode operation and a low level selects
power save mode operation.
Exposed
Thermal Pad
23
P
Internally connected to PGND. Must be soldered to achieve appropriate power dissipation and
mechanical reliability. Must be connected to common GND plane.
(1)
I = Input, O = Output, P = Power
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
Voltage(2)
VIN, EN, VOS, FB, PG, VSET/MODE
– 0.3
6
SW (DC), VOUT
– 0.3
VIN + 0.3
– 2.5
10
SW (AC, less than
10ns)(3)
ISINK_PG
Sink current at PG
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
MAX
UNIT
V
2
mA
– 40
125
°C
– 40
125
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltage values are with respect to network ground terminal.
While switching.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
UNIT
Supply Voltage Range
2.4
5.5
VOUT
Output Voltage Range
0.6
VIN
V
tF_VIN
Falling transition time at VIN (1)
10
mV/µs
Output current, TPSM82864A
4
Output current, TPSM82866A
6
IOUT
Nominal resistance range for external voltage selection resistor (E96
resistor series)
RVSET
10
External voltage selection resistor tolerance
(1)
Junction temperature
249
V
A
kΩ
1%
External voltage selection resistor temperature coefficient
TJ
4
MAX
VIN
– 40
±200
ppm/°C
125
°C
The falling slew rate of VIN should be limited if VIN goes below VUVLO (see Power Supply Recommendations).
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7.4 Thermal Information
TPSM8286x
23 PINS
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
UNIT
RDM
JEDEC 51-5
RDJ
JEDEC 51-5
RDJ
EVM
RDM
EVM
43.2
43.3
25.4
25.9
°C/W
n/a(2)
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.5
34.3
n/a(2)
RθJB
Junction-to-board thermal resistance
14.9
10.8
n/a(2)
n/a(2)
°C/W
ΨJT
Junction-to-top characterization parameter
6.8
3.6
2.4
3.7
°C/W
ΨJB
Junction-to-board characterization parameter
14.8
10.7
10.9
12.7
°C/W
(1)
(2)
For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
Not applicable to an EVM.
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7.5 Electrical Characteristics
TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
UNIT
SUPPLY
IQ_VIN
Quiescent current into VIN pin
EN = High, no load, device not switching
4
IQ_VOS
Quiescent current into VOS pin
EN = High, no load, device not switching,
VVOS = 1.8 V
8
ISD
Shutdown current
EN = Low, TJ = -40℃ to 85℃
VUVLO
Under voltage lock out threshold
TJSD
µA
µA
0.24
1
µA
VIN rising
2.2
2.3
2.4
V
VIN falling
2.1
2.2
2.3
V
Thermal shutdown threshold
TJ rising
150
°C
Thermal shutdown hysteresis
TJ falling
20
°C
LOGIC INTERFACE
VIH
High-level input threshold voltage at EN
and VSET/MODE
VIL
Low-level input threshold voltage at
EN and VSET/MODE
IEN,LKG
Input leakage current into EN pin
1.0
V
0.4
V
0.01
0.1
µA
START-UP, POWER GOOD
tDelay
Enable delay time
Time from EN high to device starts switching
with a 249-kΩ resistor connected between VSET/
MODE and GND
420
650
1100
µs
tRamp
Output voltage ramp time
Time from device starts switching to power good
0.8
1
1.5
ms
VPG(low)
Power good lower threshold
VFB referenced to VFB(nominal)
85
91
96
%
VPG(high) Power good upper threshold
VFB referenced to VFB(nominal)
103
111
120
%
VPG,OL
Low-level output voltage
Isink = 1 mA
IPG,LKG
Input leakage current into PG pin
VPG = 5.0 V
tPG,DLY
Power good delay
Rising and falling edges
Output voltage accuracy
Fixed voltage operation, FPWM, no load, TJ =
0°C to 85°C
–1
1
%
Fixed voltage operation, FPWM, no load
–2
2
%
594
0.01
0.4
V
0.1
µA
34
µs
OUTPUT
VOUT
VFB
Feedback voltage
Adjustable voltage operation
600
606
mV
IFB,LKG
Input leakage into FB pin
Adjustable voltage operation, VFB = 0.6 V
0.01
0.4
µA
RDIS
Output discharge resistor at VOS pin
3.5
Ω
VOUT = 1.2 V, FPWM
0.04
%/A
Load regulation
POWER SWITCH
RDP
Dropout resistance
High-side FET forward current limit
ILIM
Low-side FET forward current limit
TPSM8286xAA0SRDJ
100% mode. VIN = 3.3 V, TJ = 25°C
28
TPSM8286xAA0HRDM
100% mode. VIN = 3.3 V, TJ = 25°C
24
6
PWM switching frequency
mΩ
mΩ
TPSM82864A
5
5.5
6
A
TPSM82866A
7
7.9
8.5
A
TPSM82864A
4.5
A
TPSM82866A
6.5
A
-3
A
2.4
MHz
Low-side FET negative current limit
fSW
35
IOUT = 1 A, VOUT = 1.2 V
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7.6 Typical Characteristics
1.5
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
9
8
7
6
5
1.1
0.9
0.7
0.5
0.3
4
3
2.4
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
1.3
Shutdown current ISD (uA)
Quiescent current I Q_VIN (uA)
10
2.8
3.2
3.6
4
4.4
Input Voltage (V)
4.8
5.2
0.1
2.4
5.5
Dropout Resistance R DP (mOhms)
Output Discharge Resistance R DIS (Ohms)
8
7
6
5
4
3
2
2.4
2.8
3.2
3.6
4
4.4
Input Voltage (V)
4.8
5.2
3.6
4
4.4
Input Voltage (V)
4.8
50
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
9
3.2
5.2
5.5
Figure 7-2. Shutdown Current ISD
Figure 7-1. Quiescent Current into VIN IQ_VIN
10
2.8
5.5
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
45
40
35
30
25
20
15
2.4
2.8
3.2
Figure 7-3. Output Discharge Resistance RDIS
3.6
4
4.4
Input Voltage (V)
4.8
5.2
5.5
TPSM8286xAA0SRDJ
Figure 7-4. Dropout Resistance RDP
Dropout Resistance RDP (mOhms)
50
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
45
40
35
30
25
20
15
2.4
2.8
3.2
3.6
4
4.4
Input Voltage (V)
4.8
5.2
5.5
TPSM8286xAA0HRDM
Figure 7-5. Dropout Resistance RDP
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8 Detailed Description
8.1 Overview
The TPSM8286xA synchronous step-down converter power module is based on DCS-Control (Direct Control
with Seamless transition into power save mode). This is an advanced regulation topology that combines the
advantages of hysteretic, voltage, and current mode control. The DCS-Control topology operates in PWM (pulse
width modulation) mode for medium-to-heavy load conditions and in PSM (power save mode) at light load
currents. In PWM, the converter operates with its nominal switching frequency of 2.4 MHz, having a controlled
frequency variation over the input voltage range. As the load current decreases, the converter enters power
save mode, reducing the switching frequency and minimizing the quiescent current of the IC to achieve high
efficiency over the entire load current range. DCS-Control supports both operation modes using a single building
block and, therefore, has a seamless transition from PWM to PSM without effects on the output voltage. The
TPSM8286xA offers excellent DC voltage regulation and load transient regulation, combined with low output
voltage ripple, minimizing interference with RF circuits.
8.2 Functional Block Diagram
PG
VPG(high)
EN
Control Logic
UVLO
Thermal Shutdown
Start-up Ramp
VSET/
MODE
VFB
VPG(low)
VSW
+
–
VIN
PG
delay
+
–
HS-FET
Forward Current Limit
TON
VIN
VSW
VREF
selection
HICCUP
Direct Control
and
Compensation
220 nH
VOUT
Modulator
+
_EA
FB
Gate
Drive
SW
Comparator
VOS
LS-FET
Forward Current Limit
Zero Current Detect
Negative Current Limit
RDIS
AGND
PGND
8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the device seamlessly enters power save mode (PSM) operation. In PSM,
the converter operates with a reduced switching frequency and a minimum quiescent current to maintain high
efficiency. Power save mode is based on a fixed on-time architecture, as shown in Equation 1.
tON
VOUT
VIN
˜ 416ns
(1)
8
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The switching frequency in PSM is estimated as:
(2)
The load current at which PSM is entered is at one half of the ripple current of the inductor and it can be
estimated as:
(3)
In power save mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized
by increasing the output capacitance.
8.3.2 Forced PWM Mode
After the device has powered up and ramped up VOUT, the VSET/MODE pin acts as a digital input. With a
high level on the VSET/MODE pin, the device enters forced PWM (FPWM) mode and operates with a constant
switching frequency over the entire load range, even at very light loads. This reduces the output voltage ripple
and allows simple filtering of the switching frequency for noise-sensitive applications but lowers efficiency at light
loads.
8.3.3 Optimized Transient Performance from PWM to PSM Operation
For most converters, the load transient response in PWM mode is improved compared to PSM, because the
converter reacts faster on the load step and actively sinks energy on the load release. As an additional feature,
the TPSM8286xA automatically stays in PWM mode for 128 cycles after a heavy load release to bring the output
voltage back to the regulation level faster. After these 128 cycles of PWM mode, it automatically returns to PSM
(if VSET/MODE is low). See Figure 8-1. Without this optimization, the output voltage overshoot is higher.
VOUT
FPWM mode for
128 switching cycles
PSM
mode
PSM
mode
Device operates in PWM
because of high load current
IOUT
Figure 8-1. Optimized Transient Performance from PWM to PSM
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8.3.4 Low Dropout Operation (100% Duty Cycle)
The device offers a low dropout operation by entering 100% duty cycle mode if the input voltage comes close to
the target output voltage. In this mode, the high-side MOSFET switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage to maintain a minimum output voltage is given by:
VIN (min) = VOUT (min) + IOUT (max) × RDP
(4)
where
•
•
•
VOUT (min) = Minimum output voltage the load can accept
IOUT (max) = Maximum output current
RDP = Resistance from VIN to VOUT (high-side RDS(on) + RDC of the inductor)
8.3.5 Soft Start
After enabling the device, there is a 650-µs enable delay (tDelay) before the device starts switching. The tDelay
time varies with the VSET/MODE resistor used and is longest with a resistance of 249 k or higher. After the
enable delay, an internal soft-start circuit ramps up the output voltage in 1 ms (tRamp). This action avoids
excessive inrush current and creates a smooth output voltage ramp up. This action also prevents excessive
voltage drops of batteries that have a high internal impedance. Figure 8-2 shows the start-up sequence.
VIN
EN
VOUT
tDelay
tRamp
tStart-up
Figure 8-2. Start-Up Sequence
The device is able to start into a pre-biased output capacitor. The device starts with the applied bias voltage and
ramps the output voltage to its nominal value.
8.3.6 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current can occur with a heavy load or shorted output circuit condition.
If the inductor current reaches the threshold ILIM, cycle by cycle, the high-side MOSFET is turned off and the
low-side MOSFET is turned on until the inductor current ramps down to the low-side MOSFET current limit.
When the high-side MOSFET current limit is triggered 256 times, the device stops switching. The device then
automatically re-starts with soft start after a typical delay time of 16 ms has passed. The device repeats
this mode until the high load condition disappears. This HICCUP short-circuit protection reduces the current
consumed from the input supply because the device only draws input current approximately 10% of the time
during an overload condition. Figure 9-29 shows the hiccup short-circuit protection.
The low-side MOSFET also contains a negative current limit to prevent excessive current from flowing back
through the inductor to the input. If the low-side sinking current limit is exceeded, the low-side MOSFET is turned
off. In this scenario, both MOSFETs are off until the start of the next cycle. The negative current limit is only
active in forced PWM mode.
10
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8.3.7 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, undervoltage lockout (UVLO) disables the device
when the input voltage is lower than VUVLO. When the input voltage recovers, the device automatically returns to
operation with soft start.
8.3.8 Thermal Shutdown
When the junction temperature exceeds TJSD, the device goes into thermal shutdown, stops switching, and
activates the output voltage discharge. When the device temperature falls below the threshold by the hysteresis,
the device returns to normal operation automatically with soft start.
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8.4 Device Functional Modes
8.4.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic high. Accordingly, shutdown mode is forced if the EN pin is
pulled low. In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An
internal switch smoothly discharges the output through the VOS pin in shutdown mode. Do not leave the EN pin
floating.
The typical enable threshold value of the EN pin is 0.66 V for rising input signals and the typical shutdown
threshold is 0.52 V for falling input signals.
8.4.2 Output Discharge
The purpose of the output discharge function is to ensure a defined down-ramp of the output voltage when the
device is disabled and to keep the output voltage close to 0 V. The output discharge is active when the EN pin
is set to a logic low and during thermal shutdown. The discharge is active down to an input voltage of 1.6 V
(typical).
8.4.3 Power Good (PG)
The device has an open-drain power-good pin, which is specified to sink up to 2 mA. The power-good output
requires a pullup resistor connected to any voltage rail less than 5.5 V. The PG signal can be used for
sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin unconnected
when not used. Table 8-1 shows the typical PG pin logic.
Table 8-1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH IMPEDANCE
0.9 × VOUT_NOM ≤ VVOUT ≤ 1.1 × VOUT_NOM
Enable
LOW
√
VVOUT < 0.9 × VOUT_NOM or VVOUT > 1.1 × VOUT_NOM
√
Shutdown
EN = low
√
Thermal shutdown
TJ > TJSD
√
UVLO
1.8 V < VIN < VUVLO
√
Power supply removal VIN < 1.8 V
undefined
The PG pin has a 34-μs delay time on the falling edge and a 34-μs delay before PG goes high. See Figure 8-3.
VPG(high)
VO
VPG(low)
PG
tPG,DLY
tPG,DLY
tPG,DLY
tPG,DLY
tPG,DLY
tPG,DLY
Figure 8-3. Power-Good Transient and Delay Behavior
12
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8.4.4 Output Voltage and Mode Selection (VSET/MODE)
The TPSM8286xA family devices are configurable as either an adjustable output voltage or a fixed output
voltage, depending on the needs of each individual application. This feature simplifies the logistics during mass
production, as one part number offers several fixed output voltage options as well as an adjustable output
voltage option. During the enable delay (tDelay), the device configuration is set by an external resistor connected
to the VSET/MODE pin through an internal R2D (resistor to digital) converter. This configures the VREF input
to the error amplifier (EA) to be either the VFB voltage (0.6-V typical) or the selected output voltage. Table 8-2
shows the options.
Table 8-2. Output Voltage Selection Table
RESISTOR AT VSET/MODE PIN (E96 SERIES, ±1% ACCURACY,
200 ppm OR BETTER)
FIXED OR ADJUSTABLE OUTPUT VOLTAGE
249 k or logic high
Adjustable (through a resistive divider on the FB pin)
205 k
3.30 V
162 k
2.50 V
133 k
1.80 V
105 k
1.50 V
68.1 k
1.35 V
56.2 k
1.20 V
44.2 k
1.10 V
36.5 k
1.05 V
28.7 k
1.00 V
23.7 k
0.95 V
18.7 k
0.90 V
15.4 k
0.85 V
12.1 k
0.80 V
10 k or logic low
Adjustable (through a resistive divider on the FB pin)
The R2D converter has an internal current source, which applies current through the external resistor, and an
internal ADC, which reads back the resulting voltage level. Depending on the detected resistance, the output
voltage is set. After this R2D conversion is finished, the current source is turned off to avoid current flowing
through the external resistor. Make sure that the additional leakage current path is less than 20 nA and the
capacitance is not greater than 30 pF from this pin to GND during R2D conversion, otherwise a false VOUT
value is set. For more details, refer to the Benefits of a Resistor-to-Digital Converter in Ultra-Low Power Supplies
White Paper. When the device is set to a fixed output voltage, the FB pin must be connected to the output
directly. See Figure 8-4.
VIN
2.4 V to 5.5 V
VOUT
1.8 V
VIN
C1
22 µF
C2
2 × 22 µF or
1 × 47 µF
VOS
EN
R3
VPG
VOUT
FB
PG
VSET/
MODE
AGND
PGND
R4
133 kΩ
Figure 8-4. Fixed Output Voltage Application Circuit
After the start-up period (tStart-up), a different operation mode can be selected. When VSET/MODE is set to high,
the device is in forced PWM mode. Otherwise, the device is in power save mode.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPSM8286xA is a synchronous step-down converter power module family. The following section discusses
the selection of the external components to complete the power supply design. The required power inductor
is integrated inside the TPSM8286xA. The integrated shielded inductor has a value of 0.22 µH with a
±20% tolerance. The TPSM82864A and TPSM82866A are pin-to-pin and BOM-to-BOM compatible. The
TPSM8286xAA0HRDMR devices give a higher efficiency than the TPSM8286xAA0SRDJR devices due to their
increased height. For a given package height (RDM or RDJ), the 4A and 6A version give the same efficiency and
performance and are different only in their rated output current.
9.2 Typical Application
VIN
2.4 V to 5.5 V
VOUT
1.2 V
VIN
C1
22 µF
R3
VOUT
C2
2 × 22 µF or
1 × 47 µF
VOS
EN
R1
FB
VPG
PG
AGND
VSET/
MODE
PGND
R2
Figure 9-1. Typical Application
9.2.1 Design Requirements
For this design example, use Table 9-1 as the input parameters.
Table 9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.4 V to 5.5 V
Output voltage
1.2 V
Maximum output current
6A
Table 9-2 lists the components used for the example.
Table 9-2. List of Components
REFERENCE
(1)
14
DESCRIPTION
MANUFACTURER(1)
C1
22 µF, Ceramic capacitor, 6.3 V, X7R, size 0805, GRM21BZ70J226ME44
C2
47 µF, Ceramic capacitor, 6.3 V, X6S, size 0805, JMK212BC6476MG-T
Murata
R1
Depending on the output voltage, Chip resistor, 1/16 W, 1%
Std
R2
100 kΩ, Chip resistor, 1/16 W, 1%
Std
R3
100 kΩ, Chip resistor, 1/16 W, 1%
Std
Taiyo Yuden
See the Third-party Products disclaimer.
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9.2.2 Detailed Design Procedure
9.2.2.1 Setting The Output Voltage
With the VSET/MODE pin set high or low, an adjustable output voltage is set by an external resistor divider
according to Equation 5:
§V
R1 R2 u ¨ OUT
© VFB
·
1¸
¹
§V
R2 u ¨ OUT
© 0.6V
·
1¸
¹
(5)
To keep the feedback (FB) net robust from noise, set R2 equal to or lower than 100 kΩ to have at least 6 µA
of current in the voltage divider. Lower values of FB resistors achieve better noise immunity but lower light-load
efficiency, as explained in the Design Considerations for a Resistive Feedback Divider in a DC/DC Converter
Technical Brief.
When a fixed output voltage is selected, connect the FB pin directly to the output. R1 and R2 are not needed,
as VOUT is set through a resistor on the VSET/MODE pin. Select the recommended resistor value from the list in
Table 8-2.
9.2.2.2 Input and Output Capacitor Selection
For the best output and input voltage filtering, low-ESR ceramic capacitors are required. The input capacitor
minimizes input voltage ripple, suppresses input voltage spikes, and provides a stable system rail for the device.
The input capacitor must be placed between VIN and PGND as close as possible to those pins. For most
applications, 22 μF is sufficient, though a larger value reduces input current ripple. The input capacitor plays an
important role in the EMI performance of the system as explained in the Simplify Low EMI Design With Power
Modules White Paper.
The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. The capacitor
value can range from 2 × 22 µF up to 150 µF. The recommended typical output capacitors are 2 × 22 µF or 1 ×
47 µF with an X5R or better dielectric. Values over 150 µF can degrade the loop stability of the converter.
Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance.
Choose the right capacitor carefully in combination with considering its package size and voltage rating. Make
sure that the effective input capacitance is at least 10 µF and the effective output capacitance is at least 22 µF.
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9.2.3 Application Curves
100
100
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
VIN = 5.0 V, VOUT = 1.2 V, TA = 25°C, BOM = Table 9-2, unless otherwise noted. Solid lines show the FPWM mode and
dashed lines show PSM.
75
70
65
60
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
55
50
45
40
100u
1m
10m
100m
Output Current (A)
TPSM8286xAA0SRDJ
1
60
40
0
6
100
95
90
90
85
85
80
80
75
70
65
60
40
100u
10m
100m
Output Current (A)
TPSM8286xAA0SRDJ
1
60
0
90
85
85
80
80
Efficiency (%)
95
90
60
TPSM8286xAA0SRDJ
1
1
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
65
60
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
40
Figure 9-6. Efficiency VIN = 2.8 V and TA = 25°C
6
70
45
PSM and FPWM
5.5
75
50
6
5
FPWM
55
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
10m
100m
Output Current (A)
0.5
Figure 9-5. Efficiency VIN = 3.3 V and TA = 85°C
100
1m
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
TPSM8286xAA0SRDJ
65
6
FPWM
40
70
5.5
65
6
75
5
70
95
40
100u
4.5
75
100
45
2.5 3 3.5 4
Output Current (A)
45
Figure 9-4. Efficiency VIN = 3.3 V and TA = 25°C
50
2
50
PSM and FPWM
55
1.5
55
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
1m
1
Figure 9-3. Efficiency VIN = 5.0 V and TA = 85°C
95
45
0.5
TPSM8286xAA0SRDJ
100
50
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
45
Efficiency (%)
Efficiency (%)
65
50
PSM and FPWM
55
Efficiency (%)
70
55
Figure 9-2. Efficiency VIN = 5.0 V and TA = 25°C
16
75
0
0.5
1
1.5
2
2.5 3 3.5 4
Output Current (A)
TPSM8286xAA0SRDJ
4.5
5
5.5
6
FPWM
Figure 9-7. Efficiency VIN = 2.8 V and TA = 85°C
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100
100
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
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75
70
65
60
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
55
50
45
40
100u
1m
10m
100m
Output Current (A)
TPSM8286xAA0HRDM
1
75
70
65
60
50
45
40
0
6
Figure 9-8. Efficiency VIN = 5.0 V and TA = 25°C
90
85
85
80
80
Efficiency (%)
95
90
Efficiency (%)
100
95
75
70
65
60
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
45
40
100u
1m
10m
100m
Output Current (A)
TPSM8286xAA0HRDM
1
85
80
80
Efficiency (%)
Efficiency (%)
90
85
60
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
65
60
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
40
Figure 9-12. Efficiency VIN = 2.8 V and TA = 25°C
6
70
45
PSM and FPWM
5.5
75
50
6
5
FPWM
55
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
TPSM8286xAA0HRDM
1
Figure 9-11. Efficiency VIN = 3.3 V and TA = 85°C
95
1
0.5
TPSM8286xAA0HRDM
90
10m
100m
Output Current (A)
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
0
65
6
60
40
6
70
5.5
FPWM
45
75
5
65
100
1m
4.5
70
95
40
100u
2.5 3 3.5 4
Output Current (A)
75
100
45
2
50
Figure 9-10. Efficiency VIN = 3.3 V and TA = 25°C
50
1.5
55
PSM and FPWM
55
1
Figure 9-9. Efficiency VIN = 5.0 V and TA = 85°C
100
50
0.5
TPSM8286xAA0HRDM
PSM and FPWM
55
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
55
0
0.5
1
1.5
2
2.5 3 3.5 4
Output Current (A)
TPSM8286xAA0HRDM
4.5
5
5.5
6
FPWM
Figure 9-13. Efficiency VIN = 2.8 V and TA = 85°C
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2
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
1
Output Voltage Accuracy (%)
Output Voltage Accuracy (%)
2
0
-1
10u
100u
1m
10m
100m
Output Current (A)
1
1
0
-1
10u
6
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
100u
TA = 25°C
2
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
1
0
1m
10m
100m
Output Current (A)
1
1
0
-1
10u
6
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
100u
TA = 25°C
2
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
6
1
0
1m
10m
100m
Output Current (A)
1
6
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
1
0
-1
10u
100u
TA = 25°C
1m
10m
100m
Output Current (A)
1
6
TA = 25°C
Figure 9-18. Load Regulation VIN = 2.8 V and PSM
18
1
Figure 9-17. Load Regulation VIN = 3.3 V and FPWM
Output Voltage Accuracy (%)
Output Voltage Accuracy (%)
2
100u
1m
10m
100m
Output Current (A)
TA = 25°C
Figure 9-16. Load Regulation VIN = 3.3 V and PSM
-1
10u
6
Figure 9-15. Load Regulation VIN = 5.0 V and FPWM
Output Voltage Accuracy (%)
Output Voltage Accuracy (%)
2
100u
1
TA = 25°C
Figure 9-14. Load Regulation VIN = 5.0 V and PSM
-1
10u
1m
10m
100m
Output Current (A)
Figure 9-19. Load Regulation VIN = 2.8 V and FPWM
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4
3
2
Switching Frequency (MHz)
Switching Frequency (MHz)
4
3
2
1
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
10m
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
100m
Output Current (A)
PSM and FPWM
1
6
1
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
10m
TA = 25°C
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
100m
Output Current (A)
PSM and FPWM
1
6
TA = 25°C
Figure 9-20. Switching Frequency VIN = 5.0 V
Figure 9-21. Switching Frequency VIN = 3.3 V
VIN
VIN
VOUT
VOUT
VSW
VSW
VIN = 5.0 V
VOUT = 1.2 V
TA = 25°C
VIN = 5.0 V
Figure 9-22. FPWM Operation IOUT = 6 A
VOUT
IOUT
IOUT
VOUT = 1.2 V
TA = 25°C
Figure 9-24. Load Transient FPWM IOUT = 0 A → 6 A
TA = 25°C
Figure 9-23. PSM Operation IOUT = 0.1 A
VOUT
VIN = 5.0 V
VOUT = 1.2 V
VIN = 5.0 V
VOUT = 1.2 V
TA = 25°C
Figure 9-25. Load Transient PSM IOUT = 0 A → 6 A
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EN
EN
PG
PG
VOUT
VOUT
VSET / MODE
VSET / MODE
RVSET = 56.2 kΩ
IOUT = 6.0 A
RVSET = 56.2 kΩ
Figure 9-26. Start-Up into Full Load
IOUT = 0 A
Figure 9-27. Start-Up with No Load
PG
VOUT
VOUT
IOUT
IOUT
VOUT = 1.2 V
Figure 9-28. Load Sweep IOUT = 20 mA → 6 A
7
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
6.5
6
Output Current (A)
5.5
5
4.5
4
3.5
3
Figure 9-29. HICCUP Short-Circuit Protection
7
6
5.5
5
4.5
4
3.5
3
2
2
1.5
1.5
1
75
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
6.5
2.5
2.5
80
85
90
95
100 105 110
Ambient Temperature (°C)
RθJA = 25.4°C/W
115
120
TJmax = 125°C
Figure 9-30. Safe Operating Area VIN = 5.0-V
TPSM82866AA0HRDMR
20
RLOAD = 100 mΩ (during overload)
TA = 25°C
Output Current (A)
VIN = 5.0 V
1
75
80
85
90
95
100 105 110
Ambient Temperature (°C)
RθJA = 25.4°C/W
115
120
TJmax = 125°C
Figure 9-31. Safe Operating Area VIN = 3.3-V
TPSM82866AA0HRDMR
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VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
6
Output Current (A)
5.5
5
4.5
4
3.5
3
2.5
7
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
6.5
6
5.5
Output Current (A)
7
6.5
5
4.5
4
3.5
3
2.5
2
2
1.5
1.5
1
75
80
85
90
95
100 105 110
Ambient Temperature (°C)
RθJA = 25.4°C/W
115
120
TJmax = 125°C
Figure 9-32. Safe Operating Area VIN = 5.0-V
TPSM82866AA0SRDJR
1
75
80
85
90
95
100 105 110
Ambient Temperature (°C)
RθJA = 25.4°C/W
115
120
TJmax = 125°C
Figure 9-33. Safe Operating Area VIN = 3.3-V
TPSM82866AA0SRDJR
9.3 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. The average input
current of the TPSM8286xA is calculated as:
(6)
Make sure that the input power supply has a sufficient current rating for the application. The power supply must
avoid a fast ramp down. The falling ramp speed must be slower than 10 mV/μs if the input voltage drops below
VUVLO.
9.4 Layout
9.4.1 Layout Guidelines
A proper layout is critical for the operation of any switched mode power supply, especially at high switching
frequencies. Therefore, the PCB layout of the TPSM8286xA demands careful attention to ensure best
performance. A poor layout can lead to issues like the following:
•
•
•
•
Bad line and load regulation
Instability
Increased EMI radiation
Noise sensitivity
Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter Technical Brief for a detailed
discussion of general best practices. The following are specific recommendations for the TPSM8286xA:
•
•
•
•
•
•
Place the input capacitor as close as possible to the VIN and PGND pins of the device. This placement is
the most critical component placement. Route the input capacitor directly to the VIN and PGND pins avoiding
vias.
Place the output capacitor close to the VOUT and PGND pins and route it directly avoiding vias.
Place the FB resistors R1 and R2 close to the FB and AGND pins and place R4 close to the VSET/MODE pin
to minimize noise pickup.
The sense traces connected to the VOS pin is a signal trace. Take special care to avoid noise being induced.
Keep the trace away from SW.
To improve thermal performance, use GND vias under the exposed thermal pad. Directly connect the AGND
and PGND pins to the exposed thermal pad with copper on the top PCB layer.
Refer to Figure 9-34 for an example of component placement, routing, and thermal design.
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•
The recommended land pattern for the TPSM8286xA is shown at the end of this data sheet. For best
manufacturing results, create the pads as solder mask defined (SMD) when some pins (such as VIN, VOUT,
and PGND) are connected to large copper planes. Using SMD pads keeps each pad the same size and
avoids solder pulling the device during reflow.
PGND
PGND
MODE
R4
PGND
PGND
PGND
VIN
PGND
PGND
PG
PGND
VIN
VSET/
PGND
EN
C1
VIN
VOUT
VOUT
VOUT
VOUT
VOUT
AGND
FB
U1
VOS
GND
R1
R2
C2
9.4.2 Layout Example
GND
SW
35 mm²
Total Solution Size
Figure 9-34. Layout Example
22
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SLUSEF1B – SEPTEMBER 2021 – REVISED NOVEMBER 2022
9.4.2.1 Thermal Considerations
The TPSM8286xA power module temperature must be kept less than the maximum rating of 125°C. The
following are three basic approaches for enhancing thermal performance:
•
•
•
Improve the power dissipation capability of the PCB design.
Improve the thermal coupling of the component to the PCB.
Introduce airflow into the system.
To estimate the approximate module temperature of the TPSM8286xA, apply the typical efficiency stated in this
data sheet to the desired application condition to compute the power dissipation of the module. Then, calculate
the module temperature rise by multiplying the power dissipation by its thermal resistance. Using this method
to compute the maximum device temperature, the Safe Operating Area (SOA) graphs demonstrate the required
derating in maximum output current at high ambient temperatures. For more details on how to use the thermal
parameters in real applications, see the Thermal Characteristics of Linear and Logic Packages Using JEDEC
PCB Designs Application Report and Semiconductor and IC Package Thermal Metrics Application Report.
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
Application Report
Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
Texas Instruments, Benefits of a Resistor-to-Digital Converter in Ultra-Low Power Supplies White Paper
Texas Instruments, Design Considerations for a Resistive Feedback Divider in a DC/DC Converter Technical
Brief
Texas Instruments, Simplify Low EMI Design With Power Modules White Paper
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
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8-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
TPSM82864AA0HRDMR
ACTIVE
B0QFN
RDM
23
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TM864AA0H
Samples
TPSM82864AA0SRDJR
ACTIVE
B0QFN
RDJ
23
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TM864AA0S
Samples
TPSM82866AA0HRDMR
ACTIVE
B0QFN
RDM
23
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TM866AA0H
Samples
TPSM82866AA0SRDJR
ACTIVE
B0QFN
RDJ
23
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TM866AA0S
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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