Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TS3DDR4000
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
TS3DDR4000 12-bits 1:2 high speed DDR2/DDR3/DDR4 switch/multiplexer
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
Wide VDD Range: 2.375 V – 3.6 V
High Bandwidth: 5.6 GHz Typical (single-ended);
6.0 GHz Typical (differential)
Low Switch On-Resistance (RON): 8 Ω Typical
Low Bit-to-Bit Skew: 3ps Typical; 6ps Max across
All Channels
Low Crosstalk: –34 dB Typical at 1067 MHz
Low Operating Current: 40 µA Typical
Low-Power Mode with Low Current Consumption:
2 µA Typical
IOFF Protection Prevents Current Leakage in
Powered Down State (VDD = 0 V)
Supports POD_12, SSTL_12, SSTL_15 and
SSTL_18 Signaling
ESD Performance:
– 3-kV Human Body Model (A114B, Class II)
– 1-kV Charged Device Model (C101)
8 mm x 3 mm 48-balls 0.65-mm Pitch ZBA
Package
NVDIMM Modules
Enterprise Data Systems and Servers
Notebook/Desktop PCs
General DDR3/DDR4 Signal Switching
General High-Speed Signal Switching
3 Description
The TS3DDR4000 is 1:2 or 2:1 high speed
DDR2/DDR3/DDR4 switch that offers 12-bit wide bus
switching. The A port can be switched to the B or C
port for all bits simultaneously. Designed for operation
in DDR2, DDR3 and DDR4 memory bus systems, the
TS3DDR4000 uses a proprietary architecture that
delivers high bandwidth (single-ended –3dB
bandwidth at 5.6 GHz), low insertion loss at low
frequency, and very low propagation delay. The
TS3DDR4000 is 1.8 V logic compatible, and all
switches are bi-directional for added design flexibility.
The TS3DDR4000 also offers a low-power mode, in
which all channels become high-Z and the device
consumes minimal power.
Device Information(1)
PART NUMBER
TS3DDR4000
PACKAGE
NFBGA (48)
BODY SIZE (NOM)
8.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Application Diagram
DIMM Socket
Memory
Controller
TS3DDR4000
NVDIMM Module
Register
& PLL
DRAM
Battery/
Supercapacitor
NVDIMM
controller
NAND
Flash
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3DDR4000
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Static Electrical Characteristics.................................
Dynamic Electrical Characteristics............................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
Changes from Revision B (May 2017) to Revision C
Page
•
Changed the Pin Configuration image.................................................................................................................................... 3
•
Changed VIH From: SEL1m and SEL2 To: SEL0 and SEL1 with a MIN value of 1 V in the Recommended Operating
Conditions............................................................................................................................................................................... 4
•
Changed SEL1 To: SEL0 and SLE2 To: SEL1 in Figure 18 ................................................................................................ 11
•
Changed text 'Standard layout technique for 0.5 mm pitch BGA package" To: "Standard layout technique for 0.65
mm pitch BGA package..." in the Layout Guidelines............................................................................................................ 15
Changes from Revision A (March 2015) to Revision B
Page
•
Changed VDD Max value From: 5.5 V toTo: 4.8 V in the Absolute Maximum Ratings ........................................................... 4
•
Added the Note to the Application and Implementation section........................................................................................... 13
Changes from Original (November 2014) to Revision A
•
2
Page
Updated document to full version. ......................................................................................................................................... 1
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
TS3DDR4000
www.ti.com
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
5 Pin Configuration and Functions
ZBA Package
48-Balls (NFBGA)
Top View
1
2
3
4
A
A0
SEL0
B0
C0
B
A1
GND
B1
C1
C
A2
VDD
B2
C2
D
A3
GND
B3
C3
E
A4
GND
B4
C4
F
A5
GND
B5
C5
G
A6
VDD
B6
C6
H
A7
EN
B7
C7
J
A8
GND
B8
C8
K
A9
VDD
B9
C9
L
A10
GND
B10
C10
M
A11
SEL1
B11
C11
No t to scale
Pin Functions
PINS
TYPE
DESCRIPTION
NAME
NO.
VDD
C2, G2, K2
Power
Power supply
GND
B2, D2, E2, F2, J2, L2
Ground
Ground
A0-A11
A1-M1
I/O
Port A, signal 0-11
B0-B11
A3-M3
I/O
Port B, signal 0-11
C0-C11
A4-M4
I/O
Port C, signal 0-11
SEL0
A2
I
Select control 0
SEL1
M2
I
Select control 1
EN
H2
I
Enable
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
3
TS3DDR4000
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VDD
Voltage range on VDD
-0.3
4.8
V
VIN
Control input voltage range: SEL0, SEL1, and /EN
-0.3
5.5
V
VI/O
Analog voltage range: A0-A11, B0-B11, and C0-C11
-0.3
3.6
V
TA
Operating ambient temperature range
-40
85
°C
Tstg
Storage temperature range
-65
125
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
(1)
Electrostatic Charge device model (CDM)
discharge
Human body model (HBM) on all pins (2)
V(ESD)
(1)
(2)
VALUE
UNIT
±1000
V
±3000
V
Tested in accordance with JEDEC Standard 22, Test Method C101
Tested in accordance with JEDEC Standard 22, Test Method A114
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD
Voltage range on VDD
2.375
3.6
V
VI/O
Analog voltage range: A0-A11, B0-B11, and C0-C11
0
3.3
V
High-level control input voltage threshold (EN)
1.4
VDD
V
High-level control input voltage threshold (SEL0 and SEL1)
1
VDD
V
VIL
Low-level control input voltage threshold (EN, SEL0 and SEL1)
0
0.5
V
TA
Operating ambient temperature range
-40
85
°C
VIH
6.4 Thermal Information
THERMAL METRIC (1)
TS3DDR4000
BGA (48)
RθJA
Junction-to-ambient thermal resistance
92.6
RθJC(top)
Junction-to-case (top) thermal resistance
33.4
RθJB
Junction-to-board thermal resistance
56.2
ψJT
Junction-to-top characterization parameter
1.3
ψJB
Junction-to-board characterization parameter
54.9
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report .
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
TS3DDR4000
www.ti.com
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
6.5 Static Electrical Characteristics
Unless otherwise noted the specification applies over the VDD range and operation junction temp of –40°C ≤ TJ ≤ 85°C.
Typical values are for VDD = 3.3 V and TJ = 25°C.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
–
8.3
11.2
Ω
–
8.3
11.2
Ω
–
0.6
–
Ω
–
0.6
–
Ω
–
0.2
1.0
Ω
–
0.2
1.0
Ω
VDD = 3.6 V, V/EN = 1.4 V
–
–
±1
µA
VDD = 2.375 V, V/EN = 3.3 V
–
–
±1
µA
VDD = 3.6 V, VSEL1 = 1.4 V
–
–
±1
µA
VDD = 2.375 V, VSEL1 = 3.3 V
–
–
±1
µA
VDD = 3.6 V, VSEL2 = 1.4 V
–
–
±1
µA
VDD = 2.375 V, VSEL2 = 3.3 V
–
–
±1
µA
EN
VDD = 3.6 V, V/EN = 0 V
–
–
±0.5
µA
SEL1
VDD = 3.6 V, VSEL1 = 0 V
–
–
±0.5
µA
SEL2
VDD = 3.6 V, VSEL2 = 0 V
–
–
±0.5
µA
VDD = 0 V, V/EN = 0 V, VI/O = 0 V to 3.3 V
–
–
±5
µA
VDD = 0 V, V//EN = 3.6 V, VI/O = 0 V to 3.3 V
–
–
±5
µA
VDD = 0 V, VSEL1 = 0 V, VI/O = 0 V to 3.3 V
–
–
±5
µA
VDD = 0 V, VSEL1 = 3.6 V, VI/O = 0 V to 3.3 V
–
–
±5
µA
VDD = 0 V, VSEL2 = 0 V, VI/O = 0 V to 3.3 V
–
–
±5
µA
VDD = 0 V, VSEL2 = 3.6 V, VI/O = 0 V to 3.3 V
–
–
±5
µA
VDD = 3.6 V, II/O = 0 A, /EN = 0 V, VSEL1 = VSEL2= 0
V
–
28
35
µA
VDD = 3.6 V, II/O = 0 A, /EN = 0 V, VSEL1 = VSEL2=
1.8 V
–
40
48
µA
VDD = 3.6 V, II/O = 0 A, /EN = 0 V, VSEL1 = 0 V,
VSEL2= 1.8 V
–
40
44
µA
VDD = 3.6 V,II/O = 0 A, /EN = 0 V, VSEL1 = 1.8 V,
VSEL2= 0 V
–
40
44
µA
VDD = 3.6 V, II/O = 0 A, /EN = 1.8 V
–
2
5
µA
Port A to B
RON
On-state resistance
RON
On-state resistance flatness for all
I/Os
Port A to B
On-state resistance match between
channels
Port A to B
(FLAT)
∆RON
Port A to C
Port A to C
Port A to C
EN
IIH
Control input high leakage current
SEL1
SEL2
IIL
Control input low leakage current
EN
Leakage under power off condition for
all I/Os
IOFF
SEL1
SEL2
IDD
IDD,
VDD supply current
PD
VDD supply current in power-down mode
VDD = 2.375 V, VI/O = 1.2 V,
II/O = 10 mA
VDD = 2.375 V, VI/O = 1.2 V, II/O = 10 mA
VDD = 2.375 V, VI/O = 1.2 V, II/O = 10 mA
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
5
TS3DDR4000
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
www.ti.com
6.6 Dynamic Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tON
tPD
Switching time between channels for
all I/Os
Singe-ended skew between channels
CIN
Control input capacitance
COFF
CON
Switch off capacitance
Switch on capacitance
XTALK
OISO
Crosstalk between channels
Off-isolation
IL
Insertion loss (channel on)
BWSE
-3 dB bandwidth (Single-ended)
BWDIFF
-3 dB bandwidth (Differential)
6
TYP
MAX
UNIT
–
65
140
µs
EN to C
VDD = 2.375 V, RL = 50 Ω, VAn = 3.3 V, V/EN
= 1.8 V→ 0 V, VSEL1 = VSEL2 = 1.8 V
(See Figure 12)
–
65
140
µs
SEL to B
VDD = 2.375 V, V/EN = 0 V, RL = 50 Ω, VAn =
3.3 V,
(See Figure 13)
–
65
–
ns
SEL to C
VDD = 2.375 V, V/EN = 0 V, RL = 50 Ω, VAn =
3.3 V,
(See Figure 13)
–
50
–
ns
Port A to B
VDD = 2.375 V,
(See Figure 14)
–
85
–
ps
Port A to C
VDD = 2.375 V,
(See Figure 14)
–
85
–
ps
Propagation delay
tSKEW (1)
MIN
EN to B
Switch turn-on time
tSWITCH
(1)
TEST CONDITION
VDD = 2.375 V, RL = 50 Ω, VAn = 3.3 V, V/EN
= 1.8 V→ 0 V, VSEL1 = VSEL2 = 0 V
(See Figure 12)
B0 to B11
VDD = 2.375 V, from any output to any other
output
–
3
8
ps
C0 to C11
–
3
6
ps
EN
f = 1 MHz, VIN= 0 V
–
6
–
pF
SEL1
f = 1 MHz, VIN= 0 V
–
6
–
pF
SEL2
f = 1 MHz, VIN= 0 V
–
6
–
pF
Port A to B
f = 1067 MHz, VI/O = 0 V, VSEL1 = VSEL2 =
1.8V
–
0.5
–
pF
Port A to C
f = 1067 MHz, VI/O = 0 V, VSEL1 = VSEL2 = 0
V
–
0.5
–
pF
Port A to B
f = 1067 MHz, VI/O = 1.2 V, VSEL1 = VSEL2=
0V
–
1.0
–
pF
Port A to C
f = 1067 MHz, VI/O= 1.2 V, VSEL1 = VSEL2 =
1.8V
–
1.0
–
pF
B0 to B11
f = 1067 MHz, VSEL1 = VSEL2 = 0 V, RL = 50
Ω
–
-34
–
dB
C0 to C11
f = 1067 MHz, VSEL1 = VSEL2 = 1.8 V, RL = 50
–
Ω
-31
–
dB
Port A to B
f = 1067 MHz, VSEL1 = VSEL2 = 1.8 V, RL = 50
–
Ω
-21
–
dB
Port A to C
f = 1067 MHz, VSEL1 = VSEL2 = 0 V, RL = 50
Ω
–
-21
–
dB
Port A to B
f = DC, RL = 50 Ω
–
-0.75
-1
dB
Port A to C
f = DC, RL = 50 Ω
–
-0.75
-1
dB
–
5.6
–
–
5.6
–
–
6
–
–
6
–
Port A to B
Port A to C
Port A to B
Port A to C
RL = 50 Ω
RL = 100 Ω
GHz
GHz
Verified by design.
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
TS3DDR4000
www.ti.com
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
0
0
-1
-1
-2
-2
-3
-3
-4
-4
Gain (dB)
Gain (dB)
6.7 Typical Characteristics
-5
-6
-5
-6
-7
-7
-8
-8
-9
-9
-10
-10
1M
10M
100M
Frequency (Hz)
1G
1M
10G
-1
-1
-2
-2
-3
-3
-4
-4
-5
-6
-7
-8
-9
-9
-10
-10
1G
10G
1M
10M
D003
Figure 3. Differential S21 vs Frequence for Port B
D002
100M
Frequency (Hz)
1G
10G
D004
Figure 4. Differential S21 vs Frequence for Port C
0
0
-10
-10
-20
-20
-30
-30
Gain (dB)
Gain (dB)
10G
-6
-8
100M
Frequency (Hz)
1G
-5
-7
10M
100M
Frequency (Hz)
Figure 2. Single-Ended S21 vs Frequency for Port C
0
Gain (dB)
Gain (dB)
Figure 1. Single-Ended S21 vs Frequency for Port B
0
1M
10M
D001
-40
-50
-40
-50
-60
-60
-70
-70
-80
-80
-90
-90
1M
10M
100M
Frequency (Hz)
1G
10G
1M
D005
Figure 5. Crosstalk vs Frequency for Port B
10M
100M
Frequency (Hz)
1G
10G
D006
Figure 6. Crosstalk vs Frequency for Port C
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
7
TS3DDR4000
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
www.ti.com
0
0
-10
-10
-20
-20
-30
-30
-40
-40
Gain (dB)
Gain (dB)
Typical Characteristics (continued)
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
-100
1M
10M
100M
Frequency (Hz)
1G
10G
1M
D007
10M
100M
Frequency (Hz)
1G
10G
D008
Figure 7. Off-Isolation vs Frequency for Port B
Figure 8. Off-Isolation vs Frequency for Port C
Figure 9. Eye Diagram (6 Gbps Data Rate): Through Path
Without Device
Figure 10. Eye Diagram (6 Gbps Data Rate): Port A to Port B
Through TS3DDR4000
Figure 11. Eye Diagram (6 Gbps Data Rate): Port A to Port C Through TS3DDR4000
8
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
TS3DDR4000
www.ti.com
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
7 Parameter Measurement Information
VDD
VDD
Port B
Port B
Port A
Port A
CL
Port C
+
/EN
CL
RL
SEL1/
SEL2
RL
Control
Input
CL
Port C
+
CL
RL
RL
Control
Input
VDD
/EN
0
tON
Switch
Output
SEL1/
SEL2
RL= 50Ÿ
VPORTA= VDD
50%
VDD
0
tON
VOH
Switch
Output
50%
VOL
Figure 12. Switch Turn-on Time (tON) Measurement
VOH
50%
VOL
Figure 13. Switch Switching Time (tSWITCH)
Measurement
VDD
3V
Input 50%
Network Analyzer
50%
0
tPLH
Output
RL= 50Ÿ
VPORTA= VDD
50%
tPLH
50%
RS
RT
VS
RT VOUT
VOH
50%
NC
RT
VOL
SEL
GND
RT
tPD= (tPLH+tPLH)/2
Control
Input
Figure 14. Propagation Delay (tPD) Measurement
Channel ON
SEL = H or L
RS=RT=50Ÿ
VS= -10dBm (200mV at 50Ÿ /RDG)
VDC_BIAS = 0.6V
Figure 15. Crosstalk Measurement
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
9
TS3DDR4000
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
www.ti.com
Parameter Measurement Information (continued)
VDD
VDD
Network Analyzer
VOUT+
RS
RT
VOUT
Network Analyzer
RS
VS
VS
RT
SEL
SEL
GND
RT
Control
Input
RT
Control
Input
Channel ON
SEL = H or L
RS=RT=50Ÿ
VS= -10dBm (200mV at 50Ÿ /RDG)
VDC_BIAS = 0.6V
Channel OFF
SEL = H or L
RS=RT=50Ÿ
VS= -10dBm (200mV at 50Ÿ /RDG)
VDC_BIAS = 0.6V
Figure 16. Off Isolation Measurement
10
GND
Figure 17. Bandwidth Measurement
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
TS3DDR4000
www.ti.com
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
8 Detailed Description
8.1 Overview
The TS3DDR4000 is 1:2 or 2:1 high speed DDR2/DDR3/DDR4 switch that offers 12-bit wide bus switching. The
A port can be routed to the B or C port for all bits simultaneously. Designed for operation in DDR2, DDR3 and
DDR4 memory bus systems that support POD_12, SSTL_12, SSTL_135, SSTL_15, or SSTL_18 signaling, the
TS3DDR4000 uses a proprietary architecture that delivers high bandwidth (differential -3dB bandwidth of up to 6
GHz), and very low propagation delay and skew across all channels. The TS3DDR4000 is 1.8 V logic
compatible, and all switches are bi-directional for added design flexibility. The TS3DDR4000 also offers a lowpower mode, in which all channels become high-Z and the device operates with minimal power.
8.2 Functional Block Diagram
The following diagram (Figure 18) represents the switch function block diagram of the TS3DDR4000. Port A (A0A11) can be routed to either port B (B0-B11) or port C (C0-C11) by configuring the SEL0 and SEL1 pins. The EN
pin can be toggled high to put the device into the low-power mode with minimal power consumption.
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
SEL0
SEL1
EN
Control Logic
Figure 18. TS3DDR4000 Switch Function Block Diagram
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
11
TS3DDR4000
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
www.ti.com
8.3 Feature Description
•
•
IOFF Protection: When no power is provided to the device (VCC = 0 V), the TS3DDR4000 prevents any I/O
signals from back-powering the device. The leakage current is tightly controlled under such condition (refer to
the IOFF in the Specifications section) so it does not cause any system issues.
Low-power mode: The EN pin can be driven high to make the TS3DDR4000 enter the low-power mode.
When in low power mode, all channels are isolated and the device consumes less than 5 µA of current.
8.4 Device Functional Modes
When EN pin is driven high, the TS3DDR4000 enters into the power-down mode, in which all channels are
isolated and the device consumes less than 5 µA of current. When EN pin is driven low, the A port is routed to
either B port or C port depending on the configuration of SEL0 and SEL1 signals. The B and C port can also be
partially turned on when SEL0 and SEL1 are not both high or both low. Refer to Table 1 for the control logic
details.
Table 1. Logic Control Table
CONTROL PINS
EN
SEL0
SEL1
H
X
X
L
L
L
FUNCTION
Power –down mode. All channels off (isolated)
Port A to port B ON
Port A to port C OFF (isolated)
A [0,1,4,5,8,9] ↔ B [0,1,4,5,8,9]
L
L
H
A [2,3,6,7,10,11] ↔ C [2,3,6,7,10,11]
All other channels OFF (isolated)
A [2,3,6,7,10,11] ↔ B [2,3,6,7,10,11]
L
H
L
A [0,1,4,5,8,9] ↔ C [0,1,4,5,8,9]
All other channels OFF (isolated)
L
12
H
H
Port A to port B OFF (isolated)
Port A to port C ON
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
TS3DDR4000
www.ti.com
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TS3DDR4000 is a high-speed switch targeted for DDR memory applications that require 1:2 or 2:1
switching. The following sections describe two application scenarios that are widely used. In addition to memory
applications, the TS3DDR4000 can also be used for generic high-speed switching that requires high bandwidth
and minimal signal degradation.
9.2 Typical Application
9.2.1 Non-Volatile Dual In-line Memory Module (NVDIMM) application
NVDIMM Module
Power-good signal
DDR bus
Termination
Resistor
DDR bus
during power
failure
TS3DDR4000
Memory
Controller
JEDEC standard DIMM Socket
Battery/
Supercapacitor
Register
& PLL
DRAM
Control
NVDIMM Controller
NAND Flash
Figure 19. TS3DDR4000 Used In NVDIMM Application
9.2.1.1 Design Requirements
The TS3DDR4000 can be used in the NVDIMM application to provide server systems reliable data backups
when the system encounters power-failure conditions. Figure 19 depicts a typical NVDIMM design utilizing the
TS3DDR4000.
In normal system operation, the TS3DDR4000 routes the DDR signals between the system and the DRAM for
normal data access. When the system encounters power failure, the charge stored in the battery or the super
capacitor is used to power the NVDIMM controller, which configures the TS3DDR4000 to save the data from
DRAM into the NAND Flash. The NAND Flash is non-volatile in nature, so the data stored internally stays intact
even when the power goes away eventually. When the system power comes back on, the NVDIMM controller
can re-route the data from the NAND Flash through the TS3DDR4000 back into the DRAM and can
subsequently re-start the normal system operation.
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
13
TS3DDR4000
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
www.ti.com
Typical Application (continued)
9.2.1.2 Detailed Design Procedure
The battery or the super capacitor needs to be designed to have enough capacity to maintain the power long
enough for the backup procedure to be completed. At a backup speed of 128 MB/sec, it takes about 10 seconds
per 1 GB to either backup or restore the data. Typically a super capacitor is preferred for its longer life of
operation. The super capacitor is usually a separate module and is connected to the NVDIMM via a cable.
NVDIMMs require support from the system motherboard. When plugged in, the BIOS must recognize the
NVDIMMs. Manufacturers who control the BIOS and MRC (memory reference code) can make the necessary
code changes to implement NVDIMMs into their servers.
9.2.2 Load Isolation Application
SSD Controller
Control
SSTL
signaling
PCIe, Fiber
Channel, or iSCSI
Flash
Controller
SSTL
signaling
TS3DDR4000
Processor
Flash Memory
Bank #1
SSTL
signaling
Buffer
Flash Memory
Bank #2
Figure 20. TS3DDR4000 Used In Load Isolation Application
9.2.2.1 Design Requirements
In recent years, the size of Solid-State-Drives (SSDs) has increased rapidly, making it necessary to increase the
number of flash memory devices in each drive. The flash memory devices sometimes share the same control
and data channel to communicate with the controller. This causes increased loading to each communication
channel as the number of flash memory devices increases. To meet the performance requirement of an SSD, the
ability to isolate the loading becomes necessary.
9.2.2.2 Detailed Design Procedure
As depicted in Figure 20, the TS3DDR4000 can be used for load isolation purpose. Flash memory bank #1 and
#2 can share the same communication channel to the flash controller without increasing the loading to each
other. While the TS3DDR4000 is enabled for one channel, the other channel is fully isolated. The off-isolation
specification is about –21 dB at 1067 MHz, as described in the Specifications section.
10 Power Supply Recommendations
VDD should be in the range of 2.375 V to 3.6 V. A 0.1 µF or higher decoupling capacitors placed as closed to the
BGA pad as possible is recommended. There are no power sequence requirements for the TS3DDR4000.
14
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
TS3DDR4000
www.ti.com
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
11 Layout
11.1 Layout Guidelines
Standard layout technique for 0.65 mm pitch BGA package shall be employed. The following commonly-used
printed-circuit-board (PCB) layout guidelines are recommended:
• Use Non-Solder-Mask-Defined (NSMD), rather than Solder-Mask-Defined (SMD) pads for the BGA solder
balls to adhere if possible. For most applications, the NSMD pads provide more flexibility, fewer stress.
Solder mask
Solder mask
Copper pad
PCB
PCB
Solder Mask Defined
(SMD) Pads
Non-Solder Mask Defined
(NSMD) Pads
Figure 21. Solder-Mask-Defined (SMD) and Non-Solder-Mask-Defined (NSMD) Pads
•
•
One trace can generally be routed between two solder pads of a 0.65 mm pitch BGA. This allows the outer
two rows of solder pads to be routed on the same top/bottom layer. The TS3DDR4000 has 4 rows, and thus
no VIAs is generally required to route all the inner balls out.
Generally high-speed signal layout guidelines:
– To minimize the effects of crosstalk on adjacent traces, keep the traces at least two times the trace width
apart.
– Separate high-speed signals from low-speed signals and digital from analog signals.
– Avoid right-angle bends in a trace and try to route them at least with two 45° corners.
– The high-speed differential signal traces should be routed parallel to each other as much as possible. The
traces are recommended to be symmetrical.
– A solid ground plane should be placed next to the high-speed signal layer. This also provides an excellent
low-inductance path for the return current flow.
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
15
TS3DDR4000
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
www.ti.com
11.2 Layout Example
To GND Plane
To VDD Plane
Decoupling
capacitor
Port C
A0
SEL0
B0
C0
A1
GND
B1
C1
A2
VDD
B2
C2
A3
GND
B3
C3
A4
GND
B4
C4
A5
GND
B5
C5
A6
VDD
B6
C6
A7
EN
B7
C7
A8
GND
B8
C8
Top Layer
A9
VDD
B9
C9
Bottom Layer
A10
GND
B10
C10
A11
SEL1
B11
C11
Port A
Port B
Decoupling
capacitor
To VDD Plane
To GND Plane
Controller
Figure 22. TS3DDR4000 Layout Example
16
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
TS3DDR4000
www.ti.com
SCDS356C – NOVEMBER 2014 – REVISED MARCH 2019
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TS3DDR4000
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TS3DDR4000ZBAR
ACTIVE
NFBGA
ZBA
48
3000
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
DDR4000
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
