TS3L501E
SCDS307D – SEPTEMBER 2010 – REVISED OCTOBER 2022
TS3L501E 11-Channel SPDT/22-Bit to 11-Bit Multiplexer and Demultiplexer
Ethernet LAN Switch With Power-Down Mode
1 Features
3 Description
•
•
•
The TS3L501E is a 11-channel SPDT analog switch
or 22-bit to 11-bit multiplexer or demultiplexer LAN
switch with a single select (SEL) input and PowerDown Mode input. The device provides additional
I/Os for switching status indicating LED signals and
includes high ESD protection. SEL input controls the
data path of the multiplexer or demultiplexer. Powerdown input can put the device into the standby
mode for minimizing current consumption per mode
selection.
•
•
•
•
•
•
•
•
•
Integrated power-down mode
Wide bandwidth (BW = 600 MHz typical)
Low crosstalk (XTALK = –37 dB typical
at 250 MHz)
Low bit-to-bit skew (tsk(o) = 100 ps maximum)
Low and Flat ON-State Resistance
(ron = 4 Ω typical, ron(flat) = 0.5 Ω typical)
Low input and output capacitance
(CON = 9 pF typical)
Rail-to-rail switching on data I/O ports
(0 V to 3.6 V)
VCC operating range from: 3 V to 3.6 V
Support power-down mode
Latch-up performance exceeds 100 mA per JESD
78, class II
ESD performance (A, B, C, and LED pins)
– ±4-kV IEC61000-4-2, Contact Discharge
– 6-kV Human Body Model per JESD22-A114E
(switch I/O pins to GND)
ESD performance (all pins)
– 2-kV Human Body Model per JESD22-A114E
2 Applications
•
•
•
•
10, 100, and 1000 Base-T signal switching
Differential (LVDS and LVPECL) signal switching
Audio and video switching
Hub and router signal switching
The device provides a low and flat ON-state
resistance (ron) and an excellent ON-state resistance
match. Low input or output capacitance, high
bandwidth, low skew, and low crosstalk among
channels make this device suitable for various LAN
applications, such as 10/100/1000 Base-T. This
device can be used to replace mechanical relays
in LAN applications. It also can be used to route
signals from a 10/100 Base-T Ethernet transceiver to
the RJ-45 LAN connectors in laptops or in docking
stations.
It is characterized for operation over the free-air
temperature range of –40°C to 85°C.
Package Information(1)
PART NUMBER
TS3L501E
(1)
PACKAGE
RUA (WQFN, 42)
BODY SIZE (NOM)
9.00 mm × 3.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
A0
B0
A1
B1
A2
B2
A3
B3
A4
A5
B4
B5
A6
B6
A7
B7
C0
C1
C2
LED_A0
C3
C4
C5
C6
C7
LED_B0
LED_A1
LED_B1
LED_A2
LED_B2
LED_C0
LED_C1
LED_C2
SEL
PD
Control Logic
POWER DOWN
Copyright © 2016, Texas Instruments Incorporated
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3L501E
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SCDS307D – SEPTEMBER 2010 – REVISED OCTOBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics for 1000 Base-T
Ethernet Switching........................................................ 6
6.6 Electrical Characteristics for 10/100 Base-T
Ethernet Switching........................................................ 7
6.7 Switching Characteristics............................................7
6.8 Dynamic Characteristics............................................. 7
6.9 Typical Characteristics................................................ 8
7 Parameter Measurement Information............................ 9
7.1 Enable and Disable Times.......................................... 9
7.2 Skew......................................................................... 10
7.3 HP8753ES Setup...................................................... 11
7.4 HP8753ES Setup......................................................12
7.5 HP8753ES Setup......................................................13
8 Detailed Description......................................................14
8.1 Overview................................................................... 14
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................14
9 Application and Implementation.................................. 15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
10 Power Supply Recommendations..............................16
11 Layout........................................................................... 17
11.1 Layout Guidelines................................................... 17
11.2 Layout Example...................................................... 18
12 Device and Documentation Support..........................19
12.1 Documentation Support.......................................... 19
12.2 Receiving Notification of Documentation Updates..19
12.3 Support Resources................................................. 19
12.4 Trademarks............................................................. 19
12.5 Electrostatic Discharge Caution..............................19
12.6 Glossary..................................................................19
13 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2017) to Revision D (October 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed 8-channel to 11-channel throughout the data sheet............................................................................1
• Changed 16-Bit to 8-Bit to 22-Bit to 11-Bit throughout the data sheet................................................................1
Changes from Revision B (May 2016) to Revision C (December 2017)
Page
• Added pin numbers 4, 8, 14, 21, 30, 39 to VDD in the Pin Functions table......................................................... 3
Changes from Revision A (September 2010) to Revision B (May 2016)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Removed Ordering Information table .................................................................................................................1
2
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LED_ B2
LED_ C2
VDD
41
40
39
LED_A2
42
5 Pin Configuration and Functions
VDD
1
38
B0
A0
2
37
B1
A1
3
36
C0
VDD
4
35
C1
PD
5
34
B2
A2
6
33
B3
A3
7
32
C2
VDD
8
31
C3
A4
9
30
VDD
A5
10
29
B4
Exposed
Center Pad
(GND)
B6
LED_A0
15
24
B7
LED_ A1
16
23
C6
LED_ B0
17
22
C7
21
C5
25
VDD
26
14
19
SEL
VDD
20
C4
13
LED_C1
B5
27
LED_C0
28
12
18
11
A7
LED_B1
A6
The exposed center pad must be connected to GND.
Figure 5-1. RUA Package, 42-Pin WQFN (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
A0
2
I/O
Port A Common I/O signal path
A1
3
I/O
Port A Common I/O signal path
A2
6
I/O
Port A Common I/O signal path
A3
7
I/O
Port A Common I/O signal path
A4
9
I/O
Port A Common I/O signal path
A5
10
I/O
Port A Common I/O signal path
A6
11
I/O
Port A Common I/O signal path
A7
12
I/O
Port A Common I/O signal path
B0
38
I/O
Port B I/O signal path
B1
37
I/O
Port B I/O signal path
B2
34
I/O
Port B I/O signal path
B3
33
I/O
Port B I/O signal path
B4
29
I/O
Port B I/O signal path
B5
28
I/O
Port B I/O signal path
B6
25
I/O
Port B I/O signal path
B7
24
I/O
Port B I/O signal path
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Table 5-1. Pin Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
C0
36
I/O
Port C I/O signal path
C1
35
I/O
Port C I/O signal path
C2
32
I/O
Port C I/O signal path
C3
31
I/O
Port C I/O signal path
C4
27
I/O
Port C I/O signal path
C5
26
I/O
Port C I/O signal path
C6
23
I/O
Port C I/O signal path
C7
22
I/O
Port C I/O signal path
Exposed Center Pad
—
Ground
LED_A0
15
I/O
Port A LED I/O Common signal path, (may also be used as a general
purpose signal path)
LED_A1
16
I/O
Port A LED Common I/O signal path, (may also be used as a general
purpose signal path)
LED_A2
42
I/O
LED_B0
17
I/O
Port B LED I/O signal path, (may also be used as a general purpose
signal path)
LED_B1
18
I/O
Port B LED I/O signal path, (may also be used as a general purpose
signal path)
LED_B2
41
I/O
Port B LED I/O signal path, (may also be used as a general purpose
signal path)
LED_C0
19
I/O
Port C LED I/O signal path, (may also be used as a general purpose
signal path)
LED_C1
20
I/O
Port C LED I/O signal path, (may also be used as a general purpose
signal path)
LED_C2
40
I/O
Port C LED I/O signal path, (may also be used as a general purpose
signal path)
PD
5
I
Power down input, active high
Select input
GND
SEL
13
I
VDD
1, 4, 8, 14, 21, 30, 39
—
(1)
4
NO.
Port A LED Common I/O signal path, (may also be used as a general
purpose signal path)
Power
I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
–0.5
4.6
V
VIN
Control input
voltage(2) (3)
–0.5
7
V
VI/O
Switch I/O voltage(2) (3) (4)
–0.5
7
V
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
±128
mA
±100
mA
150
°C
VDD
Supply voltage
II/O
ON-state switch
current(5)
Continuous current through VDD or GND
Tstg
(1)
(2)
(3)
(4)
(5)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
All pins except 1, 4, 5, 8,
13, 14, 21, 30, and 39
±6000
Pins 1, 4, 5, 8, 13, 14, 21,
30, and 39
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1)
(2)
UNIT
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VDD
Supply voltage
3
3.6
V
VIH
High-level control input voltage (SEL)
2
5.5
V
VIL
Low-level control input voltage (SEL)
0
0.8
V
VIN
Input voltage (SEL)
0
5.5
V
VI/O
Input or output voltage
0
VDD
V
TA
Operating free-air temperature
–40
85
°C
(1)
UNIT
All unused control inputs of the device must be held at VDD or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
TS3L501E
THERMAL METRIC(1)
RUA (WQFN)
UNIT
42 PINS
RθJA
Junction-to-ambient thermal resistance(2)
30.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
12.8
°C/W
RθJB
Junction-to-board thermal resistance
5.2
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.5
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.5 Electrical Characteristics for 1000 Base-T Ethernet Switching
for 1000 Base-T Ethernet switching over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V
(unless otherwise noted)
TEST CONDITIONS(1)
PARAMETER
TYP(2)
MAX
–0.7
–1.2
V
UNIT
VIK
SEL, PD
VDD = 3.6 V, IIN = –18 mA
IIH
SEL, PD
VDD = 3.6 V, VIN = VDD
±2
μA
IIL
SEL, PD
VDD = 3.6 V, VIN = GND
±1
μA
IOFF
SEL, PD
VDD = 0 V, VIN = 0 to 3.6 V
±1
μA
600
μA
3
pF
ICC
VDD = 3.6 V, II/O = 0, switch ON or OFF
ICC_PD
VDD = 3.6 V, VIN = 3.6 V, PD = high
CIN
SEL, PD
f = 1 MHz, VIN = 0
COFF
B or C port
250
1
2.6
VI = 0,f = 1 MHz, outputs open, switch OFF
3
4
pF
CON
VI = 0,f = 1 MHz, outputs open, switch ON
9
9.8
pF
ron
VDD = 3 V, 1.5 V ≤ VI ≤ VDD, IO = –40 mA
4
8
Ω
ron(flat) (3)
VDD = 3 V, VI = 1.5 V and VDD, IO = –40 mA
0.7
Δron (4)
VDD = 3 V, 1.5 V ≤ VI ≤ VDD, IO = –40 mA
0.8
(1)
(2)
(3)
(4)
6
MIN
Ω
1.5
Ω
VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs.
All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C.
ron(flat) is the difference of ron in a given channel at specified voltages.
Δron is the difference of ron from center (A4, A5) ports to any other port.
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6.6 Electrical Characteristics for 10/100 Base-T Ethernet Switching
for 10/100 Base-T Ethernet switching over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V
(unless otherwise noted)
TEST CONDITIONS(1)
PARAMETER
MIN
TYP(2)
MAX
–0.7
–1.2
V
UNIT
VIK
SEL, PD
VDD = 3.6 V, IIN = –18 mA
IIH
SEL, PD
VDD = 3.6 V, VIN = VDD
±2
μA
IIL
SEL, PD
VDD = 3.6 V, VIN = GND
±1
μA
IOFF
SEL, PD
VDD = 0 V, VIN = 0 to 3.6 V
±1
μA
600
μA
ICC
VDD = 3.6 V, II/O = 0, switch ON or OFF
ICC_PD
VDD = 3.6 V, VIN = 3.6 V, PD = high
250
1
CIN
SEL, PD
f = 1 MHz, VIN = 0
2.6
3.0
pF
COFF
B or C port
VI = 0,f = 10 MHz, outputs open, switch OFF
3
4
pF
CON
VI = 0,f = 10 MHz, outputs open, switch ON
9
9.8
pF
ron
VDD = 3 V, 1.25 V ≤ VI ≤ VDD, IO = –10 mA to –30 mA
4
6
Ω
(3)
ron(flat)
Δron (4)
(1)
(2)
(3)
(4)
VDD = 3 V, VI = 1.25 V and VDD, IO = –10 mA to –30 mA
0.5
VDD = 3 V, 1.25 V ≤ VI ≤ VDD, IO = –10 mA to –30 mA
0.8
Ω
1.5
Ω
VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs.
All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C.
ron(flat) is the difference of ron in a given channel at specified voltages.
Δron is the difference of ron from center (A4, A5) ports to any other port.
6.7 Switching Characteristics
over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V, RL = 200 Ω, CL = 10 pF
(unless otherwise noted) (see Figure 7-1 and Figure 7-2)
PARAMETER
tpd (2)
FROM
(INPUT)
TO
(OUTPUT)
A or B/C
B/C or A
SEL
A or B/C
0.5
0.9
tPZH, tPZL
tPHZ, tPLZ
MIN
TYP(1)
MAX
UNIT
0.3
ns
15
ns
SEL
A or B/C
9
ns
tsk(o) (3)
A or B/C
B/C or A
50
100
ps
(4)
A or B/C
B/C or A
50
100
ps
PD
A or B/C
250
ns
tsk(p)
tON/tOFF (5)
(1)
(2)
All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C.
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance when driven by an ideal voltage source (zero output impedance).
Output skew between center port (A4 to A5) to any other port
Skew between opposite transitions of the same output in a given device |tPHL – tPLH|
Device enable/disable time from PD
(3)
(4)
(5)
6.8 Dynamic Characteristics
over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP(1)
UNIT
XTALK
RL = 50 Ω, f = 250 MHz, see Figure 7-4
–37
dB
OIRR
RL = 50 Ω, f = 250 MHz, see Figure 7-5
–37
dB
BW
See Figure 7-3
600
MHz
(1)
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
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6.9 Typical Characteristics
0
-14
-2
-24
-4
-34
Attenuation - dB
Gain - dB
-6
-8
-10
-44
-54
-64
-12
-74
-14
-84
-16
1.00E+06
10.00E+06 100.00E+06 1.00E+09
f - Frequency - Hz
10.00E+09
-94
1.00E+6
Figure 6-1. Gain vs Frequency
10.00E+6
100.00E+6 1.00E+9
f - Frequency - Hz
10.00E+9
Figure 6-2. OFF Isolation vs Frequency
3.5
-19.97
-29.97
3
RON - On-Resistance - W
Attenuation - dB
-39.97
-49.97
-59.97
-69.97
-79.97
-89.97
-99.97
-109.97
1.00E+6
2.5
2
1.5
1
0.5
10.00E+6
100.00E+6 1.00E+9
f - Frequency - Hz
10.00E+9
0
0
0.5
Figure 6-3. Crosstalk vs Frequency
1
1.5
2
2.5
3
VI - Input Voltage - V
3.5
4
Figure 6-4. ron (Ω) vs Vcom (V)
8
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7 Parameter Measurement Information
7.1 Enable and Disable Times
VDD
Input Generator
VIN
50 W
50 W
VG1
TEST CIRCUIT
DUT
2 × VDD
Input Generator
S1
RL
VO
VI
50 W
CL
(see Note A)
50 W
VG2
RL
TEST
VDD
S1
RL
Vin
CL
VD
tPLZ/tPZL
3.3 V
2 × VDD
200 W
GND
10 pF
0.3 V
tPHZ/tPZH
3.3 V
GND
200 W
VDD
10 pF
0.3 V
VI
VO
2.5 V
Output Control
(VIN)
1.25 V
1.25 V
0V
Output
Waveform 1
S1 at 2 VDD
(see Note B)
tPZL
tPLZ
VOH
VDD/2
VOL + 0.3 V
tPZH
VO
Open
GND
Output
Waveform 2
S1 at GND
(see Note B)
VOL
tPHZ
VDD/2
VOH - 0.3 V
VOH
VOL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
Figure 7-1. Test Circuit and Voltage Waveforms
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7.2 Skew
VDD
Input Generator
VIN
50 W
50 W
VG1
TEST CIRCUIT
DUT
2 × VDD
Input Generator
VO
VI
Open
RL
TEST
VDD
S1
RL
Vin
CL
tsk(o)
3.3 V ± 0.3 V
Open
200 W
VDD or GND
10 pF
tsk(p)
3.3 V ± 0.3 V
Open
200 W
VDD or GND
10 pF
3.5 V
2.5 V
1.5 V
Data In at
Ax or Ay
tPHLx
VOH
(VOH + VOL)/2
VOL
Data Out at
XB1 or XB2
tsk(o)
VO
CL
(see Note A)
50 W
tPLHx
VO
S1
GND
50 W
VG2
VI
RL
3.5 V
tsk(o)
VOH
(VOH + VOL)/2
VOL
Data Out at
YB1 or YB2
tPLHy
2.5 V
1.5 V
Input
tPHLy
tsk(o) = t PLHy - t PLHx or t PHLy - t PHLx
VOLTAGE WAVEFORMS
OUTPUT SKEW (tsk(o))
tPLH
tPHL
VOH
(VOH + VOL)/2
VOL
Output
tsk(p) = t PHL - t PLH
VOLTAGE WAVEFORMS
PULSE SKEW [tsk(p)]
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 7-2. Test Circuit and Voltage Waveforms
10
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EXT TRIGGER
BIAS
VBIAS
Network Analyzer
(HP8753ES)
P1
P2
VDD
0B1
A0
SEL
DUT
CL = 10 pF
(see Note A)
VSEL
A.
CL includes probe and jig capacitance.
Figure 7-3. Test Circuit for Frequency Response (BW)
Frequency response is measured at the output of the ON channel. For example, when VSEL = 0 and A0 is the
input, the output is measured at 0B1. All unused analog I/O ports are left open.
7.3 HP8753ES Setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
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EXT TRIGGER
BIAS
VBIAS
Network Analyzer
(HP8753ES)
P1
P2
VDD
A0
0B1
RL = 50 W
A1
1B1
0B2
DUT
A2
1B2
2B1
RL = 50 W
A3
3B1
2B2
3B2
SEL
VSEL
A.
B.
CL includes probe and jig capacitance.
A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 7-4. Test Circuit for Crosstalk (XTALK)
Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VSEL = 0 and A1 is the
input, the output is measured at A3. All unused analog input (A) ports are connected to GND, and output (B)
ports are left open.
7.4 HP8753ES Setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
12
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EXT TRIGGER
BIAS
VBIAS
Network Analyzer
(HP8753ES)
P1
P2
VDD
A0
0B1
RL = 50 W
A1
1B1
DUT
0B2
1B2
SEL
VSEL
A.
B.
CL includes probe and jig capacitance.
A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 7-5. Test Circuit for OFF Isolation (OIRR)
OFF isolation is measured at the output of the OFF channel. For example, when VSEL = GND and A1 is the input,
the output is measured at 1B2. All unused analog input (A) ports are connected to ground, and output (B) ports
are left open.
7.5 HP8753ES Setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
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8 Detailed Description
8.1 Overview
The TS3L501E is a 11-channel SPDT analog switch or 22-bit to 11-bit multiplexer/demultiplexer LAN switch with
a single select (SEL) input and Power Down Mode input. The device provides additional I/Os for switching status
indicating LED signals and includes high ESD protection. SEL input controls the data path of the multiplexer/
demultiplexer. Power Down input can put the device into the standby mode for minimizing current consumption
per mode selection.
The device provides a low and flat ON-state resistance (ron) and an excellent ON-state resistance match.
Low input/output capacitance, high bandwidth, low skew, and low crosstalk among channels make this device
suitable for various LAN applications, such as 10/100/1000 Base-T. This device can be used to replace
mechanical relays in LAN applications. It also can be used to route signals from a 10/100 Base-T Ethernet
transceiver to the RJ-45 LAN connectors in laptops or in docking stations.
8.2 Functional Block Diagram
A0
B0
A1
B1
A2
B2
A3
B3
A4
A5
B4
B5
A6
B6
A7
B7
C0
C1
C2
LED_A0
C3
C4
C5
C6
C7
LED_B0
LED_A1
LED_B1
LED_A2
LED_B2
LED_C0
LED_C1
LED_C2
SEL
Control Logic
PD
POWER DOWN
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
The TS3L501E device switches and pin out are optimized for ethernet application but the device can used for
many applications where a multi-channel, 1:2 SPDT, high bandwidth switch is needed.
8.4 Device Functional Modes
The TS3L501E supports a power down mode which reduces the current consumption of the device and places
all the signal paths in a high impedance state. To place the TS3L501E in power down mode, set the PD pin with
a logic high voltage as seen in Table 8-1.
Table 8-1. Function Table
PD
14
SEL
FUNCTION
L
L
An to Bn, LED_An to LED_Bn
L
H
An to Cn, LED_An to LED_Cn
H
X
Hi-Z
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
There are many Local Area Network (LAN) applications in which the ethernet hubs or controllers have a limited
number of I/Os or need to route signals from a single ethernet PHY to multiple ethernet jacks. The TS3L501E
solution can effectively expand the limited I/Os by switching between multiple ethernet jacks to interface them to
a single ethernet PHY.
The LED_An, LED_Bn,and LED_Cn pins are rated the same as the other signal path pins so you may use these
pins as extra data paths if needed.
9.2 Typical Application
VDD
TS3L501E
Processor
2
LED_BN
2
LED 1
LED_AN
GPIO
2
LED 2
LED_CN
7
Gigabit
Ethernet
PHY
7
BN
AN
RJ45 Port 1
7
CN
GPIO
SEL
GPIO
PD
RJ45 Port 2
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 9-1. Typical Application Schematic
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9.2.1 Design Requirements
Ensure that all of the signals passing through the switch are within the recommended operating ranges. To
ensure proper performance, see Recommended Operating Conditions.
9.2.2 Detailed Design Procedure
The TS3L501E can be properly operated without any external components.
TI recommends that the digital control pins SEL and PD be pulled up to VCC or down to GND to avoid undesired
switch positions that could result from the floating pin.
Connect the exposed thermal pad to ground.
9.2.3 Application Curves
0
-2
-4
Gain - dB
-6
-8
-10
-12
-14
-16
1.00E+06
10.00E+06 100.00E+06 1.00E+09
f - Frequency - Hz
10.00E+09
Figure 9-2. Gain vs Frequency
10 Power Supply Recommendations
Power to the device is supplied through the VDD pins. TI recommends placing a bypass capacitor as close to the
supply pin (VCC) as possible to help smooth out lower frequency noise to provide better load regulation across
the frequency spectrum.
All VDD pins are internally connected. One PCB layout option is to connect one of the VDD to the power supply
and leave the other VDD pins open.
Supply the TS3L501E VDD pins with the recommended voltage before appling a signal voltage to the I/O signal
paths to avoid violating the recommended opperating condition I/O voltage 0-VDD.
16
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
TI recommends keeping the high-speed signals as short as possible.
Each via introduces discontinuities in the transmission line of the signal and increases the chance of picking
up interference from the other layers of the board. Be careful when designing test points on twisted pair lines;
through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting
holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed signals because they cause signal reflections. If a stub is unavoidable, then
the stub must be less than 200 mm.
Route all high-speed signal traces over continuous GND planes, with no interruptions. Avoid crossing over
anti-etch, commonly found with plane splits.
Due to high-frequency signals, a printed-circuit board with at least four layers is recommended; two signal
layers separated by a ground and power layer as shown in Figure 11-1.
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer
should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the
ground or power plane. When running across split planes is unavoidable, sufficient decoupling must be used.
Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.
Signal 1
GND Plane
Power Plane
Signal 2
Figure 11-1. Four-Layer Board Stackup
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11.2 Layout Example
VDD
To
To
To
System System System
0603
42
41
40
39
1
38
To System
2
37
To System
3
36
To System
4
35
To System
5
34
To System
6
33
To System
7
32
8
31
Exposed Center
Pad
(GND)
9
To System
10
To System
11
28
To System
12
27
To System
13
26
14
25
To System
15
24
To System
16
23
To System
17
22
19
20
To System
To System
To System
To System
To System
To System
To System
30
To System
18
To System
29
To System
To System
To System
To System
To System
To System
To System
To System
21
To
To
To
System System System
Figure 11-2. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TS3L501ERUAR
ACTIVE
WQFN
RUA
42
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TK501E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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