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TS3USB30
SCDS237F – AUGUST 2007 – REVISED AUGUST 2015
TS3USB30 High-Speed USB 2.0 (480-MBPS)
1:2 Multiplexer/Demultiplexer Switch With Single Enable
1 Features
3 Description
•
•
•
The TS3USB30 is a high-bandwidth switch specially
designed for the switching of high-speed USB 2.0
signals in handset and consumer applications, such
as cell phones, digital cameras, and notebooks with
hubs or controllers with limited USB I/Os. The wide
bandwidth (955 MHz) of this switch allows signals to
pass with minimum edge and phase distortion. The
device multiplexes differential outputs from a USB
host device to one of two corresponding outputs. The
switch is bidirectional and offers little or no
attenuation of the high-speed signals at the outputs. It
is designed for low bit-to-bit skew and high channelto-channel noise isolation, and is compatible with
various standards, such as high-speed USB 2.0 (480
Mbps).
1
•
•
•
•
•
•
•
VCC Operation at 3 V and 4.3 V
1.8-V Compatible Control-Pin Inputs
IOFF Supports Partial Power-Down-Mode
Operation
Ron = 10 Ω Maximum
ΔRon 0
–0.5
VCC + 0.3
D+, D– when VCC = 0
–0.5
5.25
VI/O
Signal path I/O voltage (2)
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
II/O
ON-state switch current (5)
±64
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
(4)
(5)
Storage temperature
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
6000
Charged-device model (CDM), per JEDEC specification JESD22-C101
1000
UNIT
V
6.3 Recommended Operating Conditions
See
VCC
(1)
.
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI/O
Data input/output voltage
TA
Operating free-air temperature
(1)
4
MIN
MAX
3
4.3
VCC = 3 V to 3.6 V
1.3
VCC
VCC = 4.3 V
1.7
VCC
VCC = 3 V to 3.6 V
0
0.5
VCC = 4.3 V
0
0.7
0
VCC
V
–40
85
°C
Supply voltage
UNIT
V
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to Implications of Slow or
Floating CMOS Inputs (SCBA004).
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6.4 Thermal Information
TS3USB30
THERMAL METRIC (1)
RSW (UQFN)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
117.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
67.7
°C/W
RθJB
Junction-to-board thermal resistance
23.2
°C/W
ψJT
Junction-to-top characterization parameter
1.9
°C/W
ψJB
Junction-to-board characterization parameter
23.2
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
VIK
TEST CONDITIONS
MIN
TYP (2)
MAX
UNIT
Control input clamp voltage
VCC = 3 V, II = –18 mA
–1.2
V
IIN
Control inputs
VCC = 4.3 V, 0 V,
VIN = 0 to 4.3 V
±1
μA
IOZ
D+ and D– OFF-state leakage
current (3)
VCC = 4.3 V, VO = 0 to 3.6 V, VI = 0,
Switch OFF
±2
μA
IOFF
Powered off leakage current
VCC = 0 V, VO = 0 to 4.3 V,
VI = 0, VIN = VCC or GND
±2
μA
Supply current
VCC = 4.3 V, II/O = 0, Switch ON or OFF
1
μA
Control inputs
VCC = 4.3 V, VIN = 2.6 V
10
μA
Cin
Control inputs digital input
capacitance
VCC = 0 V, VIN = VCC or GND
1
pF
Cio(OFF)
OFF-state input capacitance
VCC = 3.3 V, VI/O = 3.3 V or 0, Switch OFF
2
pF
Cio(ON)
ON-state input capacitance
VCC = 3.3 V, VI/O = 3.3 V or 0, Switch ON
7
RON
ON-state resistance (5)
VCC = 3 V, VI = 0.4, IO = –8 mA
6
ΔRON
ON-state resistance match between
VCC = 3 V, VI = 0.4, IO = –8 mA
channels
0.35
Ω
RON(flat)
ON-state resistance flatness
2
Ω
ICC
ΔICC
(1)
(2)
(3)
(4)
(5)
(4)
VCC = 3 V, VI = 0 V or 1 V, IO = –8 mA
pF
Ω
10
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
6.6 Dynamic Electrical Characteristics
over operating range, TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V
PARAMETER
TEST CONDITIONS
TYP (1)
UNIT
XTALK
Crosstalk
RL = 50 Ω, f = 240 MHz, See Figure 6
–56
OISO
OFF isolation
RL = 50 Ω, f = 240 MHz, See Figure 5
–39
dB
BW
Bandwidth (–3 dB)
RL = 50 Ω, CL = 5 pF, See Figure 7
955
MHz
(1)
dB
For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
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6.7 Switching Characteristics
over operating range, TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V
PARAMETER
TEST CONDITIONS
RL = 50 Ω, CL = 5 pF,
See Figure 8
TYP (1)
MAX
UNIT
tpd
Propagation delay (2)
tON
Line enable time, SEL to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
30
ns
tOFF
Line disable time, SEL to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
25
ns
tON
Line enable time, OE to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
30
ns
tOFF
Line disable time, OE to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
25
ns
tSK(O)
Output skew between center port to any other port (2)
RL = 50 Ω, CL = 5 pF,
See Figure 9
50
ps
tSK(P)
Skew between opposite transitions of the same output
(tPHL – tPLH) (2)
RL = 50 Ω, CL = 5 pF,
See Figure 9
20
ps
tJ
Total jitter (2)
RL = 50 Ω, CL = 5 pF,
tR = tF = 500 ps at 480 Mbps
(PRBS = 215 – 1)
20
ps
(1)
(2)
(3)
6
(3)
MIN
0.25
ns
For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
Specified by design
The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance.
The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. Since this time constant is much smaller than the rise/fall
times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch, when used in
a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven side.
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6.8 Typical Characteristics
0
0
–1
–10
–20
Attenuation (dB)
–2
Gain (dB)
–3
–4
–5
–30
–40
–50
–60
–6
–70
–7
–80
–8
–90
100.0E+3
100.0E+3
1.0E+6
10.0E+6
100.0E+6
1.0E+9
10.0E+9
1.0E+6
10.0E+6
100.0E+6
1.0E+9
10.0E+9
Frequency (Hz)
Frequency (Hz)
Figure 2. OFF Isolation
Figure 1. Gain vs Frequency
0
–10
Attenuation (dB)
–20
–30
–40
–50
–60
–70
–80
–90
–100
100.0E+3
1.0E+6
10.0E+6
100.0E+6
1.0E+9
10.0E+9
Frequency (Hz)
Figure 3. Crosstalk
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7 Parameter Measurement Information
VCC
1D or 2D VOUT1
VIN
TEST
RL
CL
VIN
tON
50 Ω
5 pF
VCC
tOFF
50 Ω
5 pF
VCC
D
1D or 2D VOUT2
(B)
CL
RL
S
OE
VSEL(A)
1.8 V
Logic
RL
Input
(VSEL or V OE)
CL(B)
GND
50%
50%
0
tON
VOE(A)
Switch
Output
(VOUT1 or V OUT2)
tOFF
90%
90%
VOH
VOL
A.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns,
tf < 5 ns.
B.
CL includes probe and jig capacitance.
Figure 4. Turn-On (tON) and Turn-Off Time (tOFF)
VCC
Network Analyzer
Channel OFF: 1D to D
50 Ω
VOUT1 1D
VSEL = VCC
VIN
D
Source
Signal
50 Ω
2D
Network Analyzer Setup
Source Power = 0 dBm
(632-mV P-P at 50-Ω load)
VSEL S
50 Ω
+
GND
DC Bias = 350 mV
Figure 5. OFF Isolation (OISO)
VCC
Network Analyzer
Channel ON: 1D to D
50 Ω
VOUT1 1D
Channel OFF: 2D to D
VIN
Source
Signal
VSEL = VCC
VOUT2 2D
50 Ω
VSEL S
50 Ω
+
GND
Network Analyzer Setup
Source Power = 0 dBm
(632-mV P-P at 50-Ω load)
DC Bias = 350 mV
Figure 6. Crosstalk (XTALK)
8
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Parameter Measurement Information (continued)
VCC
Network Analyzer
50 Ω
VOUT1
1D
Channel ON: 1D to D
D
Source
Signal
VIN
VCTRL = GND
2D
Network Analyzer Setup
50 Ω
VSEL
Source Power = 0 dBm
(632-mV P-P at 50-Ω load)
S
GND
GND
DC Bias = 350 mV
Figure 7. Bandwidth (BW)
400 mV
Figure 8. Propagation Delay
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Parameter Measurement Information (continued)
VOH
VOL
Pulse Skew tSK(P)
VOH
VOL
VOH
VOL
Output Skew tSK(P)
Figure 9. Skew Test
10
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Parameter Measurement Information (continued)
VCC
VOUT1 1D
D
+
VIN
Channel ON
VOUT2 2D
r on
VSEL
IIN
S
VIN
VOUT2 or VOUT1
Ω
IIN
VSEL = VIH or VIL
+
GND
Figure 10. ON-State Resistance (RON)
VCC
VOUT1 1D
D
+
VOUT2 2D
VSEL
VIN
+
S
OFF-State Leakage Current
Channel OFF
VSEL = VIH or VIL
+
GND
Figure 11. OFF-State Leakage Current
VCC
VOUT1 1D
Capacitance
Meter
VBIAS
VBIAS = VCC or GND
VOUT2 2D
VSEL = VCC or GND
VIN D
Capacitance is measured at 1D,
2D, D, and S inputs during ON
and OFF conditions.
VSEL S
GND
Figure 12. Capacitance
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8 Detailed Description
8.1 Overview
The TS3USB30 is a high-bandwidth switch specially designed for the switching and isolating of high-speed USB
2.0 signals in systems with limited USB I/Os. The wide bandwidth (955 MHz) of this switch allows signals to pass
with minimum edge and phase distortion. The device multiplexes differential outputs from a USB host device to
one of two corresponding outputs or from two different hosts to one corresponding output. The switch is
bidirectional and offers little or no attenuation of the high-speed signals at the outputs. It is designed for low bitto-bit skew and high channel-to-channel noise isolation, and is compatible with various standards, such as highspeed USB 2.0 (480 Mbps).
8.2 Functional Block Diagram
D1+
D+
D2+
D1–
D–
D2–
S
OE
Control
8.3 Feature Description
The TS3USB30 has a bus-switch enable pin, OE, that can place the signal paths in high impedance. This allows
the user to isolate the bus when it is not in use and consume less current.
8.4 Device Functional Modes
The device functional modes are shown in Table 1.
Table 1. Truth Table
12
S
OE
FUNCTION
X
H
Disconnect
L
L
D = D1
H
L
D = D2
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
There are many USB applications in which the USB hubs or controllers have a limited number of USB I/Os. The
TS3USB30 solution can effectively expand the limited USB I/Os by switching between multiple USB buses in
order to interface them to a single USB hub or controller. TS3USB221 can also be used to connect a single
controller to two USB connectors or controllers.
9.2 Typical Application
VCC
TS3USB30
1D+
USB2.0
Controller
D+
1D–
Set Top Box
(STB) CPU
or DSP
Processor
USB
Connector
D–
2D+
DVR or
Mass Storage
Controller
2D–
Control
S
OE
Figure 13. Application Diagram
9.2.1 Design Requirements
Design requirements of the USB 1.0, 1.1, and 2.0 standards should be followed. TI recommends that the digital
control pins S and OE be pulled up to VCC or down to GND to avoid undesired switch positions that could result
from the floating pin.
9.2.2 Detailed Design Procedure
The TS3USB30 can be properly operated without any external components. However, it is recommended that
unused pins should be connected to ground through a 50-Ω resistor to prevent signal reflections back into the
device.
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Typical Application (continued)
0.5
0.5
0.4
0.4
0.3
0.3
Differential Signal (V)
Differential Signal (V)
9.2.3 Application Curves
0.2
0.1
0.0
–0.1
–0.2
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.3
–0.4
–0.4
–0.5
–0.5
0.0
0.2
0.4
0.5
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0
0.2
0.4
0.5
–9
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–9
Time (X 10 ) (s)
Time (X 10 ) (s)
Figure 14. Eye Pattern: 480-Mbps USB Signal With No
Switch (Through Path)
Figure 15. Eye Pattern: 480-Mbps USB Signal With Switch
NC Path
0.5
0.4
Differential Signal (V)
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0.0
0.2
0.4
0.5
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–9
Time (X 10 ) (s)
Figure 16. Eye Pattern: 480-Mbps USB Signal With Switch NO Path
14
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10 Power Supply Recommendations
Power to the device is supplied through the VCC pin and should follow the USB 1.0, 1.1, and 2.0 standards. TI
recommends placing a bypass capacitor as close as possible to the supply pin VCC to help smooth out lower
frequency noise to provide better load regulation across the frequency spectrum.
11 Layout
11.1 Layout Guidelines
Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the D+
and D– traces.
The high speed D+ and D– traces should always be matched lengths and must be no more than 4 inches;
otherwise, the eye diagram performance may be degraded. A high-speed USB connection is made through a
shielded, twisted pair cable with a differential characteristic impedance. In layout, the impedance of D+ and D–
traces should match the cable characteristic differential impedance for optimal performance.
Route the high-speed USB signals using a minimum of vias and corners which will reduce signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points on twisted pair
lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then
the stub should be less than 200 mm.
Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended: two signal layers separated by a ground and power layer. The majority of signal traces should run
on a single layer, preferably Signal 1. Immediately next to this layer should be the GND plane, which is solid with
no cuts. Avoid running signal traces across a split in the ground or power plane. When running across split
planes is unavoidable, sufficient decoupling must be used. Minimize the number of signal vias reduces EMI by
reducing inductance at high frequencies. For more information on layout guidelines, see High Speed Layout
Guidelines (SCAA082) and USB 2.0 Board Design and Layout Guidelines (SPRAAR7).
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11.2 Layout Example
To Device 2
VCC
To Device 1
= VIA to GND Plane
0603 Cap
OE
To System
D2-
D1-
To System
D-
VCC
GND
S
D+
To System
D2+
D1+
To System
To Device 2
To Device 1
Figure 17. Layout Recommendation
16
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• High Speed Layout Guidelines, SCAA082
• USB 2.0 Board Design and Layout Guidelines, SPRAAR7
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TS3USB30RSWR
ACTIVE
UQFN
RSW
10
3000
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
-40 to 85
(L67, L6O)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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