TS5A6542YZTR

TS5A6542 0.75-Ω SPDT ANALOG SWITCH WITH INPUT LOGIC TRANSLATION www.ti.com SCDS230 – APRIL 2006 FEATURES • • • • • • • • • • Specified Break-Before-Make Switching Low ON-State Resistance (0.75 Ω Max) Control Inputs Referenced to VIO Low Charge Injection Excellent ON-State Resistance Matching Low Total Harmonic Distortion (THD) 2.25-V to 5.5-V Power Supply (V+) 1.65-V to 1.95-V Logic Supply (VIO) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 4000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) – 400-V Machine Model (A115-A) • COM Port to GND – 8000-V Human-Body Model (A114-B, Class II) – ±15-kV Contact Discharge (IEC 61000-4-2) APPLICATIONS • • • Cell Phones PDAs Portable Instrumentation YZT PACKAGE (BOTTOM VIEW) VIO NC GND NO D1 4 5 D2 C1 3 C2 B1 2 7 B2 A1 1 8 A2 6 V+ IN COM GND DESCRIPTION/ORDERING INFORMATION The TS5A6542 is a single-pole double-throw (SPDT) analog switch that is designed to operate from 2.25 V to 5.5 V. The device offers a low ON-state resistance with an excellent channel-to-channel ON-state resistance matching, and the break-before-make feature to prevent signal distorion during the transferring of a signal from one path to another. The device has excellent total harmonic distortion (THD) performance and consumes very low power. These features make this device suitable for portable audio applications. The TS5A6542 has a separate logic supply pin (VIO) operates from 1.65 V to 1.95 V. VIO powers the control circuitry, which allows the TS5A6542 to be controlled by 1.8-V signals. ORDERING INFORMATION TA –40°C to 85°C (1) (2) PACKAGE (1) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZT (Pb-free) 0.625-mm max height ORDERABLE PART NUMBER Tape and reel TS5A6542YZTR TOP-SIDE MARKING (2) _ _ _ JH7 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. YZT: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TS5A6542 0.75-Ω SPDT ANALOG SWITCH WITH INPUT LOGIC TRANSLATION www.ti.com SCDS230 – APRIL 2006 SUMMARY OF CHARACTERISTICS (1) 2:1 Multiplexer/Demultiplexer (1 × SPDT) Configuration Number of channels 1 ON-state resistance (ron) 0.75 Ω max ON-state resistance match (∆ron) 0.1 Ω max ON-state resistance flatness [(ron(flat)] 0.1 Ω max Turn-on/turn-off time (tON/tOFF) 25 ns/20 ns Charge injection (QC) 15 pC Bandwidth (BW) 43 MHz OFF isolation (OISO) –63 dB at 1 MHz Crosstalk (XTALK) –63 dB at 1 MHz Total harmonic distortion (THD) 0.004% Leakage current [INO(OFF)/INC(OFF)] 20 nA Package option (1) 8-pin WCSP V+ = 5 V, TA = 25°C FUNCTION TABLE NC TO COM, COM TO NC NO TO COM, COM TO NO L ON OFF H OFF ON IN Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) MAX UNIT V+ VIO Supply voltage range (3) –0.5 6.5 V VNC VNO VCOM Analog voltage range (3) (4) (5) –0.5 V+ + 0.5 V II/OK Analog port diode current (6) INC INO ICOM On-state switch current VI Digital input voltage range (3) (4) IIK Digital input clamp current I+ IGND Continuous current through V+ or GND θJA Package thermal impedance (8) Tstg Storage temperature range (1) (2) (3) (4) (5) (6) (7) (8) 2 MIN VNO, VCOM < 0 or VNO, VCOM > V+ VNO, VCOM = 0 to V+ On-state peak switch current (7) VI < 0 –50 50 –200 200 –400 400 –0.5 6.5 –50 –100 –65 mA mA V mA 100 mA 102 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum All voltages are with respect to ground, unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 5.5 V maximum. Requires clamp diodes on analog port to V+ Pulse at 1-ms duration