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TS5MP646
SCDS371E – JANUARY 2018 – REVISED APRIL 2019
TS5MP646 4 Data Lane 2:1 MIPI Switch (10-Channel, 2:1 Analog Switch)
1 Features
3 Description
•
•
•
The TS5MP646 is a four data lane MIPI switch. This
device is an optimized 10-channel (5 differential)
single-pole, double-throw switch for use in high speed
applications. The TS5MP646 is designed to facilitate
multiple MIPI compliant devices to connect to a single
CSI/DSI, C-PHY/D-PHY module.
1
•
•
•
•
•
•
Supply Range of 1.65 V to 5.5 V
10-Channel 2:1 Switch
Powered-Off Protection:
I/Os Hi-Z when VDD = 0 V
Low RON of 4.2-Ω Typical
Bandwidth of 3 GHz
Ultra Low Crosstalk of -40 dB
Low Power Disable Mode
1.8-V Compatible Logic Inputs
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (HBM)
The device has a bandwidth of 3 GHz, low channelto-channel skew with little signal degradation, and
wide margins to compensate for layout losses. The
device's low current consumption meets the needs of
low power applications, including mobile phones and
other personal electronics.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
•
•
•
TS5MP646
Mobile Phones
Tablet
PC/Notebook
Virtual and Augmented Reality
Drones
Camera-based carcode scanner
Medical
IP Netcam
Simplified C-PHY Schematic
1.65 V ± 5.5 V
1.65 V ± 5.5 V
100 nF
2.2 µF
2.2 µF
CLK
Trio[1:3]
VDD
Data[1:4]
CLK
MIPI Module 1
TS5MP646
MIPI Switch
Trio[1:3]
50 Ÿ
Trio [1:3]
Processor
Data[1:4]
MIPI Module 2
SEL
/OE
VDD
MIPI Module 1
Data[1:4]
CLK
MIPI Module 2
BODY SIZE (NOM)
2.42 mm x 2.42 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified D-PHY Schematic
100 nF
PACKAGE
DSBGA (YFP)
50 Ÿ
TS5MP646
MIPI Switch
Processor
50 Ÿ
SEL
/OE
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS5MP646
SCDS371E – JANUARY 2018 – REVISED APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
5
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2019) to Revision E
Page
•
Added min differential bandwidth specification 2.7 GHz ........................................................................................................ 8
•
Changed typ differential bandwith specification to 4.1 GHz ................................................................................................... 8
Changes from Revision C (August 2018) to Revision D
Page
•
Added the Simplified D-PHY and C-PHY Schematic ............................................................................................................. 1
•
Added the Typical D-PHY and C-PHY Application circuits .................................................................................................. 20
•
Added Eye diagrams to the Application Curves section....................................................................................................... 22
•
Added the MIPI D-PHY Application section ......................................................................................................................... 23
•
Added the MIPI C-PHY Application section ......................................................................................................................... 25
Changes from Revision B (July 2018) to Revision C
•
Page
Changed the Applications list ................................................................................................................................................. 1
Changes from Revision A (March 2018) to Revision B
Page
Changes from Original (January 2018) to Revision A
Page
•
2
Changed the BODY SIZE (NOM) in the Device Information table From: 2.459 x 2.459 To: 2.42 x 2.42 .............................. 1
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SCDS371E – JANUARY 2018 – REVISED APRIL 2019
5 Pin Configuration and Functions
DSBGA Package
36 Pin (YFP)
Top View
1
2
3
4
5
6
A
VDD
GND
DA4N
DA4P
OE
SEL
B
DB4N
DB4P
DA3N
DA3P
D4N
D4P
C
DB3N
DB3P
NC
NC
D3N
D3P
D
DB2N
DB2P
DA2N
DA2P
D2N
D2P
E
DB1N
DB1P
DA1N
DA1P
D1N
D1P
F
CLKBN
CLKBP
CLKAN
CLKAP
CLKN
CLKP
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
VDD
A1
PWR
Power supply input
GND
A2
GND
Device Ground
DA4N
A3
I/O
Differential I/O
DA4P
A4
I/O
Differential I/O
OE
A5
I
Output enable (Active Low)
SEL
A6
I
Channel Select
DB4N
B1
I/O
Differential I/O
DB4P
B2
I/O
Differential I/O
DA3N
B3
I/O
Differential I/O
DA3P
B4
I/O
Differential I/O
D4N
B5
I/O
Differential I/O
D4P
B6
I/O
Differential I/O
DB3N
C1
I/O
Differential I/O
DB3P
C2
I/O
Differential I/O
NC
C3
-
No connect
NC
C4
-
No connect
D3N
C5
I/O
Differential I/O
D3P
C6
I/O
Differential I/O
DB2N
D1
I/O
Differential I/O
DB2P
D2
I/O
Differential I/O
DA2N
D3
I/O
Differential I/O
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
DA2P
D4
I/O
Differential I/O
D2N
D5
I/O
Differential I/O
D2P
D6
I/O
Differential I/O
DB1N
E1
I/O
Differential I/O
DB1P
E2
I/O
Differential I/O
DA1N
E3
I/O
Differential I/O
DA1P
E4
I/O
Differential I/O
D1N
E5
I/O
Differential I/O
D1P
E6
I/O
Differential I/O
CLKBN
F1
I/O
Differential I/O
CLKBP
F2
I/O
Differential I/O
CLKAN
F3
I/O
Differential I/O
CLKAP
F4
I/O
Differential I/O
CLKN
F5
I/O
Differential I/O
CLKP
F6
I/O
Differential I/O
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VDD
Supply Voltage
-0.5
6
V
VI/O
Analog voltage range (DxN, CLKN, DxP, CLKP, DAxN, CLKAN,
DAxP, CLKAP, DBxN, CLKBN, DBxP, CLKBP)
-0.5
4
V
VSEL, VOE
Digital Input Voltage (SEL, /OE)
-0.5
6
V
TJ
Junction temperature
-65
150
°C
Tstg
Storage temperature
-65
150
°C
(1)
UNIT
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 500-V HBM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ± WWW V and/or ± XXX V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 250-V CDM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ± YYY V and/or ± ZZZ V may actually have higher performance.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Supply Voltage
1.65
5.5
V
VI/O
Analog voltage range (DxN, CLKN, DxP, CLKP, DAxN, CLKAN, DAxP,
CLKAP, DBxN, CLKBN, DBxP, CLKBP)
0
3.6
V
V(SEL)
V(OE)
Digital Input Voltage
0
5.5
V
II/O
Continuous I/O current
-35
35
mA
TA
Operating ambient temperature
-40
85
°C
TJ
Junction temperature
-65
150
°C
6.4 Thermal Information
TS5MP646
THERMAL METRIC (1)
YFP
UNIT
36
RθJA
Junction-to-ambient thermal resistance
57.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.3
°C/W
RθJB
Junction-to-board thermal resistance
12.6
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
12.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
IDD
IDD_PD
IDD_PD_1.
VDD Active Supply Current
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V
0
30
60
µA
Power-down Supply current
VDD = 1.65 V to 5.5 V
OE = VDD
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V
0
0.1
1
µA
Power-down Supply current
VDD = 1.65 V to 5.5 V
OE = 1.8 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V
0
0.1
10
µA
On-state resistance
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0.2 V
DAn, DBn, CLKAn, CLKBn = 0.2 V, -8
mA
6
9
Ω
On-state resistance
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 1.2 V
DAn, DBn, CLKAn, CLKBn = 1.2 V, -8
mA
6
10
Ω
8
DC CHARACTERISTICS
RON_HS
RON_LP
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RON_flat_
DRON_LP
IOFF
IOFF_3_6
ION
ION_3_6
TYP
MAX
UNIT
On-state resistance flatness
0.1
Ω
On-state resistance flatness
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0 V to 1.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3
V, -8 mA
0.9
Ω
On-state resistance match between+and
- paths
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0.2 V
DAn, DBn, CLKAn, CLKBn = 0.2 V, -8
mA
0.1
Ω
On-state resistance match between+and
- paths
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 1.3 V
DAn, DBn, CLKAn, CLKBn = 1.3 V, -8
mA
0.1
Ω
Switch off leakage current
VDD = 1.65 V to 5.5 V
OE = 0 V to 5.5 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V to 1.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3
V
-0.5
0.5
µA
Switch off leakage current
VDD = 0V1.5V,1.65V,3.3V,5.5V
/OE = 0V,1.5V,1.65V,3.3V,5.5V
SEL= 0V,1.5V,1.65V,3.3V,5.5V
DX,CLKX = 3.6V
DAX,DBx,CLKAX,CLKBX = 3.6V
-10
10
µA
Switch on leakage current
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V to 1.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3
V
-0.5
0.5
µA
Switch on leakage current
VDD = 1.5V,1.65V,3.3V,5.5V
/OE = 0V
SEL= 0V,1.5V,1.65V,3.3V,5.5V
DX,CLKX = 3.6V
DAX,DBx,CLKAX,CLKBX = 3.6V
-50
50
µA
1.5
µs
50
µs
100
kHz
P
DRON_HS
MIN
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0 V to 0.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 0.3
V, -8 mA
HS
RON_flat_L
TEST CONDITIONS
DYNAMIC CHARACTERISTICS
tSWITCH
Switching time between channels
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
tSWITCH_
Switching time between channels by
charge pump
VDD = 1.5V,1.65V,3.3V,5.5V
/OE = 0V
DX, CLKX = 0.6 V
DAX, DBX, CLKAX, CLKBX:
RL=50Ω,CL=5pF
CP
fSEL_MAX
6
VDD = 1.65 V to 5.5 V
Maximum toggling frequency for the SEL Dn, CLKn = 0.6 V
line
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Device turnon-time OE to switch on
VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
50
300
µs
tON_VDD
Device turnon-time VDD to switch on
VDD = 0 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
50
300
µs
tOFF_OE
Device turnoff time OE to switch off
VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
0.5
1
µs
tOFF_VDD
Device turnoff time VDD to switch off
VDD = 5 V to 0 V
VDD ramp rate = 250 µs
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
0.5
1
ms
tMIN_/OE
Minimum pulse width for OE
VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
Break before make time
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = RL = 50 Ω, CL = 1 pF
DAn, DBn, CLKAn, CLKBn: 0.6 V
Intrapair skew
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.3 V
DnX, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
1
ps
Interpair Skew
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.3 V
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
4
ps
Propagation delay with 100 ps rise time
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
tRISE = 100 ps
40
ps
Differential off isolation
VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn:
RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV+200 mVPP (differential)
f = 1250 MHz
-20
dB
Differential channel to channel crosstalk
VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn:
RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV+200 mVPP (differential)
f = 1250 MHz
-40
dB
tON_OE
tBBM
tSKEW
tSKEW
tPD
OISO
XTALK
500
ns
50
ns
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
BW
ILOSS
COFF
CON
MIN
TYP
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn:
RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV+200 mVPP (differential)
f = 1250 MHz
2.7
4.1
Insertion Loss
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn:
RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV+200 mVPP (differential)
f = 100 kHz
-0.65
Off capacitance
VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn =
0 V, 0.2 V
f = 1250 MHz
1.5
pF
On capacitance
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn =
0 V, 0.2 V
f = 1250 MHz
1.5
pF
Differential Bandwidth
TEST CONDITIONS
MAX
UNIT
GHz
dB
DIGITAL CHARACTERISTICS
VIH
Input logic high (SEL, OE)
VI/O = 0.6 V RL = 50 Ω, CL = 5 pF
1.425
5.5
VIL
Input logic low (SEL, /OE)
IIH
Input high leakage current (SEL, /OE)
IIL
VI/O = 0.6 V RL = 50 Ω, CL = 5 pF
0
0.5
V
VI/O = 0.6 V RL = 50 Ω, CL = 5 pF
-5
5
µA
Input low leakage current (SEL, /OE)
VI/O = 0.6 V RL = 50 Ω, CL = 5 pF
-5
5
µA
RPD
Internal pull-down resistance on digital
input pins
VI/O = 0.6 V RL = 50 Ω, CL = 5 pF
6
MΩ
CI
Digital Input capacitance (SEL, /OE)
f = 1 MHz
5
pF
8
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6.6 Typical Characteristics
7
7
RON (-40°C)
RON (25°C)
RON (85°C)
RON (-40°C)
RON (25°C)
RON (85°C)
6.5
6
6
5.5
5.5
RON (:)
RON (:)
6.5
5
5
4.5
4.5
4
4
3.5
3.5
3
3
0
0.2
0.4
0.6
0.8
Input Voltage (V)
1
1.2
0
1.4
Figure 1. RON vs Input Voltage. VDD = 1.65 V
0.4
0.6
0.8
Input Voltage (V)
1
1.2
1.4
D002
Figure 2. RON vs Input Voltage. VDD = 3.3 V
7
0
RON (-40°C)
RON (25°C)
RON (85°C)
6.5
-1
-2
6
-3
-0.33 dB
-4
Gain (dB)
5.5
RON (:)
0.2
D001
5
4.5
-5
-3.32 dB
-6
-7
-8
4
-9
-10
3.5
-11
0
0.2
0.4
0.6
0.8
Input Voltage (V)
1
1.2
Bandwidth
-12
300000
3
1.4
1E+7
1E+8
Frequency (Hz)
D003
1E+9
1E+10
D004
Figure 4. Differential Bandwidth
Figure 3. RON vs Input Voltage. VDD = 5.5 V
0
0
-20
-20
-40
Gain (dB)
Gain (dB)
-40
-60
-60
-80
-100
-80
-120
Crosstalk
Off Isolation
-100
100000
1000000
1E+7
1E+8
Frequency (Hz)
1E+9
1E+10
-140
200000 1000000
D005
Figure 5. Off Isolation
1E+7
1E+8
Frequency (Hz)
1E+9
1E+10
D006
Figure 6. Differential Crosstalk
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7 Parameter Measurement Information
Channel ON
RON = V/ION
V
VI/O
ION
Switch
Copyright © 2018, Texas Instruments Incorporated
Figure 7. On Resistance
VI/O
VI/O
A
A
Switch
Figure 8. Off Leakage
VI/O
A
Switch
Figure 9. On Leakage
VI/OA
VI/O
VI/OB
SEL
CL
CL
RL
RL
VSEL
1.8 V
VSEL
VIL
1.8 V
VSEL
VIH
VIH
VIL
0V
tSWITCH
tSWITCH
VI/OA
80
%
0V
tSWITCH
tSWITCH
VI/O
20 %
VI/O
80 %
VI/OB
0V
20 %
0V
Copyright © 2018, Texas Instruments Incorporated
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 3 ns,
tf = 3 ns.
(2)
CL includes probe and jig capacitance.
Figure 10. tSWITCH Timing
10
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Parameter Measurement Information (continued)
1.65 V
VDD
VI/O
VI/O
CL
/OE
1.8 V
RL
V/OE
VIH
VIL
0V
tOFF
tON
VI/O
V/OE
90 %
VI/O
10 %
0V
Copyright © 2018, Texas Instruments Incorporated
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 3 ns,
tf = 3 ns.
(2)
CL includes probe and jig capacitance.
Figure 11. tON and tOFF Timing for OE
Network Analyzer
50
Switch
DXP
50
Source
Signal
50
DXN
50
Source
Signal
50
50
Copyright © 2018, Texas Instruments Incorporated
Figure 12. Off Isolation
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Parameter Measurement Information (continued)
Network Analyzer
50
Switch
DXP
50
Source
Signal
50
50
DXN
50
Source
Signal
50
DXP
50
50
50
DXN
50
50
50
Copyright © 2018, Texas Instruments Incorporated
Figure 13. Crosstalk
Network Analyzer
50
Switch
DXN
50
Source
Signal
50
DXP
50
Source
Signal
50
50
Copyright © 2017, Texas Instruments Incorporated
Figure 14. Bandwidth and Insertion Loss
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Parameter Measurement Information (continued)
Generator
Switch
50
D1P
DX1P
Source
Signal
50
50
50
D1N
Source
Signal
DX1N
50
50
50
D2P
DX2P
Source
Signal
50
50
50
D2N
Source
Signal
DX2N
50
50
50
D3P
DX3P
Source
Signal
50
50
50
D3N
Source
Signal
DX3N
50
50
50
D4P
DX4P
Source
Signal
50
50
50
D4N
Source
Signal
DX4N
50
50
50
CLKP
CLKXP
Source
Signal
50
50
50
CLKN
Source
Signal
CLKXN
50
50
Copyright © 2017, Texas Instruments Incorporated
Figure 15. tPD, tSKEW(INTRA) and tSKEW(INTER) Setup
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Parameter Measurement Information (continued)
DXX/CLKX
50%
50%
tPD
tPD
DXXX/CLKXX
50%
50%
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 100
ps, tf = 100 ps.
(2)
CL includes probe and jig capacitance.
Figure 16. tPD
DXX/CLKX
50%
50%
tSKEW
DXXX/CLKXX
tSKEW
50%
50%
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 100
ps, tf = 100 ps.
(2)
CL includes probe and jig capacitance.
Figure 17. tSKEW(INTRA)
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Parameter Measurement Information (continued)
tSKEW
DX/CLKX
tSKEW
tSKEW
DX1
50%
50%
DX2
50%
50%
DX3
50%
DX4
50%
CLK
50%
50%
50%
50%
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 100
ps, tf = 100 ps.
(2)
CL includes probe and jig capacitance.
(3)
tSKEW is the max skew between all channels. Diagram exaggerates tSKEW to show measurement technique
Figure 18. tSKEW(INTER)
0.6 V
VI/O
VSEL
CL
RL
SEL
VI/O
VSEL
80 %
tBBM
0.6 V
tBBM
Copyright © 2017, Texas Instruments Incorporated
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 3 ns,
tf = 3 ns.
(2)
CL includes probe and jig capacitance.
Figure 19. tBBM
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8 Detailed Description
8.1 Overview
The TS5MP646 is a high-speed 4 data lane 2:1 MIPI Switch. The device includes 10 channels (5 differential)
with 4 differential data lanes and 1 differential clock lane for D-PHY, CSI or DSI. The switch allows a single MIPI
port to interface between two MIPI modules, expanding the number of potential MIPI devices that can be used
within a system that is MIPI port limited.
8.2 Functional Block Diagram
VDD
SEL
6 MO
Control
Logic
/OE
6 MO
CLKAP
CLKP
CLKBP
CLKAN
CLKN
CLKBN
DA1P
D1P
DB1P
DA1N
D1N
DB1N
DA2P
D2P
DB2P
DA2N
D2N
DB2N
DA3P
D3P
DB3P
DA3N
D3N
DB3N
DA4P
D4P
DB4P
DA4N
D4N
DB4N
GND
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8.3 Feature Description
8.3.1
Powered-Off Protection
When the TS5MP646 is powered off (VDD = 0 V) the I/Os and digital logic pins of the device remains in a high
impedance state. The crosstalk, off-isolation, and leakage will remain within the electrical specifications. This
prevents errant voltages from reaching the rest of the system and maintains isolation when the system is
powering up.
Figure 20 shows an example system containing a switch without powered-off protection with the following system
level scenario.
1. Subsystem A powers up and starts sending information to Subsystem B that remains unpowered.
2. The I/O voltage back powers the supply rail in Subsystem B.
3. The digital logic is back powered and turns on the switch. The signal is transmitted to Subsystem B before it
is powered and damages it.
Unpowered
Powered
LDO
2
VDD
Subsystem A
1
ESD
SEL
Switch
Subsystem B
3
Figure 20. System Without Powered-Off Protection
With powered-off protection, the switch prevents back powering the supply and the switch remains highimpedance. Subsystem B remains protected.
Unpowered
Powered
LDO
VDD
Protection
Subsystem A
ESD
SEL
Subsystem B
Hi-Z
Switch
Figure 21. System With Powered-Off Protection
This features has the following system level benefits.
•
•
•
Protects the system from damage.
Prevents data from being transmitted unintentionally
Eliminates the need for power sequencing solutions reducing BOM count and cost, simplifying system design
and improving reliability.
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Feature Description (continued)
8.3.2
1.8-V Logic Compatible Inputs
The TS5MP646 has 1.8-V logic compatible digital inputs for switch control. Regardless of the VDD voltage the
digital input thresholds remained fixed, allowing a 1.8-V processor GPIO to control the TS5MP646 without the
need for an external translator. This saves both space and BOM cost.
An example setup for a system without a 1.8-V logic compatible input is shown in Figure 22. Here the supply
mismatch between the process and its GPIO output and the supply to the switch require a translator.
3.3 V
1.8 V
Processor
GPIO
VDD
SEL
1.8 V
Switch
Figure 22. System Without 1.8 V Logic Compatible Inputs
With the 1.8 V logic compatibility in the TS5MP646, the translator is built in to the device so that the external
components are no longer needed, simplifying the system design and overall cost.
3.3 V
1.8 V
VDD
Processor
GPIO
1.8 V
SEL
Switch
Figure 23. System With 1.8 V Logic Compatible Inputs
8.3.3
Low Power Disable Mode
The TS5MP646 has a low power mode that places all the signal paths in a high impedance state and lowers the
current consumption while the device is not in use. To put the device in low power mode and disable the switch,
the output enable pin OE must be supplied with a logic high signal.
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8.4 Device Functional Modes
8.4.1 Pin Functions
The SEL and OE pins have a weak 6-MΩ pull-down to prevent floating input logic.
Table 1. Function Table
8.4.2
OE
SEL
H
X
L
L
L
H
Function
I/O pins High-Impedance
CLK(P/N) = CLKA(P/N)
Dn(P/N) = DAn(P/N)
CLK(P/N) = CLKB(P/N)
Dn(P/N) = DBn(P/N)
Low Power Disable Mode
While the output enable pin OE is supplied with a logic high, the device remains in low power disabled state. This
reduces the current consumption substantially and the switches are high impedance. The SEL pin is ignored
while the OE remains high. Upon exiting low power mode, the switch status reflects the SEL pin as seen in
Table 1.
8.4.3
Switch Enabled Mode
While the output enable pin OE is supplied with a logic low, the device remains in switch enabled mode.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
Figure 24 represents a typical application of the TS5MP646 MIPI switch. The TS5MP646 is used to switch
signals between multiple MIPI modules and a single MIPI port on a processor. This expands the capabilities of a
single port to handle multiple MIPI modules.
1.65 V ± 5.5 V
100 nF
2.2 µF
VDD
CLK
Data[1:4]
CLK
MIPI Module 1
Data[1:4]
TS5MP646
MIPI Switch
CLK
Processor
Data[1:4]
MIPI Module 2
SEL
/OE
Figure 24. Typical D-PHY Application
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Typical Application (continued)
1.65 V ± 5.5 V
100 nF
2.2 µF
Trio[1:3]
VDD
MIPI Module 1
Trio[1:3]
50 Ÿ
Trio [1:3]
MIPI Module 2
50 Ÿ
TS5MP646
MIPI Switch
Processor
50 Ÿ
SEL
/OE
Figure 25. Typical C-PHY Application
9.2.1 Design Requirements
Design requirements of the MIPI standard must be followed. Supply pin decoupling capacitors of 2.2 µF and 100
nF are recommended for best performance. The TS5MP646 has internal 6-MΩ pulldown resistors on SEL and
OE. The pulldown on these pins ensure that the digital remains in a non-floating state during system power-up to
prevent shoot through current spikes and an unknown switch status. By default the switch will power up enabled
and with the A path selected until driven externally by the processor.
9.2.2 Detailed Design Procedure
The TS5MP646 can be properly operated without any external components. However, TI recommends that
unused I/O signal pins be connected to ground through a 50 Ω resistor to prevent signal reflections and maintain
device performance. The NC pins of the device do not require any external connections or terminations and have
no connection to the rest of the device internally.
The clock and data lanes can be interchanged as necessary to facilitate the best layout possible for the
application. For example, the clock can be placed on the D1 channel and a data lane can be used on the CLK
channel if this improves the layout. In addition, the signal lines of the TS5MP646 are routed single ended on the
chip die. This makes the device suitable for both differential and single-ended high-speed systems.
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Typical Application (continued)
9.2.3 Application Curves
0
-1
-2
-3
-0.33 dB
Gain (dB)
-4
-5
-3.32 dB
-6
-7
-8
-9
-10
-11
Bandwidth
-12
300000
1E+7
1E+8
Frequency (Hz)
1E+9
1E+10
D004
Figure 26. Differential Bandwidth
Figure 27. 2.5 Gbps with Signal Switch
22
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Figure 28. 2.5 Gbps Through Path
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Typical Application (continued)
9.2.3.1 MIPI D-PHY Application
The clock and data lanes can be interchanged as necessary to facilitate the best layout possible for the
application. In addition, the signal lines of the TS5MP646 are routed single ended on the chip die. This makes
the device suitable for both differential and single-ended high-speed systems. This also allows the positive and
negative lines to be interchanged as necessary to facilitate the best layout possible for the application.
D-PHY application includes a differential clock and 4 differential datalanes. All the channels of the device perform
similar and the clock or data signals may be interchanged as necessary to facilitate the best layout possible for
the application.
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Typical Application (continued)
VDD
D-PHY
Module A
SEL
6M
Control
Log ic
D-PHY
Module B
/OE
6M
MIP I_CSI_CLKP
+/- Clock
MIP I_CSI_CLKN
MIP I_CSI_DATA1P
MIP I_CSI_DATA2P
MIP I_CSI_DATA3P
MIP I_CSI_DATA4P
CLKAN
MIP I_CSI_CLKN_Module A
CLKBN
MIP I_CSI_CLKN_Module B
DA1P
MIP I_CSI_DATA1P_Module A
DB1P
MIP I_CSI_DATA1P_Module B
DA1N
MIP I_CSI_DATA1N_Module A
DB1N
MIP I_CSI_DATA1N_Module B
DA2P
MIP I_CSI_DATA2P_Module A
DB2P
MIP I_CSI_DATA2P_Module B
DA2N
MIP I_CSI_DATA2N_Module A
DB2N
MIP I_CSI_DATA2N_Module B
DA3P
MIP I_CSI_DATA3P_Module A
DB3P
MIP I_CSI_DATA3P_Module B
DA3N
MIP I_CSI_DATA3N_Module A
DB3N
MIP I_CSI_DATA3N_Module B
DA4P
MIP I_CSI_DATA4P_Module A
DB4P
MIP I_CSI_DATA4P_Module B
DA4N
MIP I_CSI_DATA4N_Module A
DB4N
MIP I_CSI_DATA4N_Module B
D2P
D2N
D3P
D3N
D4P
+/- DATA4
MIP I_CSI_DATA4N
MIP I_CSI_CLKP_Module B
D1N
+/- DATA3
MIP I_CSI_DATA3N
CLKBP
D1P
+/- DATA2
MIP I_CSI_DATA2N
MIP I_CSI_CLKP_Module A
CLKN
+/- DATA1
MIP I_CSI_DATA1N
CLKAP
CLKP
D4N
GND
Figure 29. MIPI D-PHY Example Pinout
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Typical Application (continued)
9.2.3.2 MIPI C-PHY Application
The clock and data lanes can be interchanged as necessary to facilitate the best layout possible for the
application. In addition, the signal lines of the TS5MP646 are routed single ended on the chip die. This
makes the device suitable for both differential and single-ended high-speed systems. This also allows the
positive and negative lines to be interchanged as necessary to facilitate the best layout possible for the
application.
C-PHY application includes 3 trios of signals which may be routed on any channel which means there will be
one unused channel on the TS5MP646. TI recommends that the unused I/O signal pin be connected to
ground through a 50 Ω resistor to prevent signal reflections and maintain device performance.
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Typical Application (continued)
VDD
C-PHY
Module A
SEL
6M
Control
Log ic
C-PHY
Module B
/OE
6M
MIP I_CSI_A0
MIP I_CSI_B0
MIP I_CSI_A1
Trio 1
MIP I_CSI_B1
MIP I_CSI_C1
MIP I_CSI_A2
Trio 2
MIP I_CSI_B2
MIP I_CSI_C2
MIP I_CSI_A0_Module A
CLKBP
MIP I_CSI_A0_Module B
CLKAN
MIP I_CSI_B0_Module A
CLKBN
MIP I_CSI_B0_Module B
DA1P
MIP I_CSI_C0_Module A
DB1P
MIP I_CSI_C0_Module B
DA1N
MIP I_CSI_A1_Module A
DB1N
MIP I_CSI_A1_Module B
DA2P
MIP I_CSI_B1_Module A
DB2P
MIP I_CSI_B1_Module B
DA2N
MIP I_CSI_C1_Module A
DB2N
MIP I_CSI_C1_Module B
DA3P
MIP I_CSI_A2_Module A
DB3P
MIP I_CSI_A2_Module B
DA3N
MIP I_CSI_B2_Module A
DB3N
MIP I_CSI_B2_Module B
DA4P
MIP I_CSI_C2_Module A
DB4P
MIP I_CSI_C2_Module B
CLKN
Trio 0
MIP I_CSI_C0
CLKAP
CLKP
D1P
D1N
D2P
D2N
D3P
D3N
D4P
50 Ÿ
50
DA4N
D4N
DB4N
GND
50 Ÿ
GND
Figure 30. MIPI C-PHY Example Pinout
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10 Power Supply Recommendations
When the TS5MP646 is powered off (VDD = 0 V), the I/Os of the device remains in a high-Z state. The crosstalk,
off-isolation, and leakage remain within the electrical Specifications. Power to the device is supplied through the
VDD pin. Decoupling capacitors of 100 nF and 2.2 µF are recommended on the supply.
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11 Layout
11.1 Layout Guidelines
Place the supply de-coupling capacitors as close to the VDD and GND pin as possible. The spacing between the
power traces, supply and ground, and the signal I/O lines, clock and data, should be a minimum of three times
the race width of the signal I/O lines to maintain signal integrity.
The characteristic impedance of the trace(s) must match that of the receiver and transmitter to maintain signal
integrity. Route the high-speed traces using a minimum amount of vias and corners. This will reduce the amount
of impedance changes.
When it becomes necessary to make the traces turn 90°, use two 45° turns or an arc instead of making a single
90° turn.
Do not route high-speed traces near crystals, oscillators, external clock signals, switching regulators, mounting
holes or magnetic devices.
Avoid stubs on the signal lines.
All I/O signal traces should be routed over a continuous ground plane with no interruptions. The minimum width
from the edge of the trace to any break in the ground plane must be 3 times the trace width. When routing on
PCB inner signal layers, the high speed traces should be between two ground planes and maintain characteristic
impedance.
High speed signal traces must be length matched as much as possible to minimize skew between data and clock
lines.
11.2 Layout Example
Top Layer Routing
VIA to
power plane
Bottom Layer Routing
VIA to
ground plane
Via
C
To Control
Logic
C
To MIPI
Modules
VDD
GND
DA4
N
DA4
P
/OE
SEL
DB4
N
DB4
P
DA3
N
DA3
P
D4N
D4P
DB3
N
DB3
P
NC
NC
D3N
D3P
DB2
N
DB2
P
DA2
N
DA2
P
D2N
D2P
DB1
N
DB1
P
DA1
N
DA1
P
D1N
D1P
CLK
BN
CLK
BP
CLK
AN
CLK
AP
CLK
N
CLK
P
To MIPI Port
Figure 31. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TS5MP646NYFPR
ACTIVE
DSBGA
YFP
36
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TS5MP646
TS5MP646YFPR
ACTIVE
DSBGA
YFP
36
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TS5MP646
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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