Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TVB1440
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
TVB1440 4-Channel Video Re-Driver with Equalization
ECCN: 3E991
1 Features
3 Description
•
TVB1440 is a 4 channel re-driver signal conditioner
for TV applications allowing signal integrity between
TV chipset and TCON boards. I2C control provides
the wide ranges of flexibility to configure the device
for optimal signal conditioning so that video data link
between a source and sink can achieve high fidelity.
TVB1440 allows larger distance between a video
source and sink device through its excellent jitter
cleaning capability.
Compatible with TV Aggregated Video Signaling
Electricals
Compatible to FPD Link 2 Interface
Suited for Digital TV Chipset and TCON Boards
Quad Channel Re-Driver Supporting Data Rates
from 600 Mbps to 5 Gbps
3.3 V and 1.1 V Supply for Low Power Operation
175 mW Active Power Consumption for 4 Lane
Operation
2 mW Shutdown Power
Highly Configurable Input Equalization with 8
Control Settings
– 0 dB to 15 dB
4 Pre-Emphasis Control Settings
– 0, 3, 6 and 9 dB
4 Output Voltage Swing Control Settings
– 350, 500, 700 and 1000 mV
I2C Control to Configure the Device for Optimum
Performance
Extended Temperature Range of -40°C to 85°C
2 kV HBM and 500 V CDM ESD Protection
48-pin QFN 7 mm x 7 mm package.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
The TVB1440 is optimized for power conscience
applications. Apart from its low active power,
TVB1440 contains activity detection circuitry on the
data link input that transitions to a low-power output
disable mode in the absence of a valid input signal.
This activity detect circuit can be disabled if desired.
The device also has a shutdown mode when
exercised results in 2mW.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
It has selectable control for receive equalization
accessible through I2C to compensate for large trace
or cable loss at its input resulting improved eye at the
output signals. Transmitter in each channel has 4
levels of pre-emphasis and 4 levels of output voltage
swing settings which enable optimum video signal
performance from the TVB1440 to downstream
receiver.
TVB1440
Digital Television
Camera
Video Interfaces Requiring Large Throughputs
PACKAGE
VQFN (48)
BODY SIZE (NOM)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematics
Display Sink
TVB1440
TVB1440
TVB1440
TVB1440
D1
Driver
TVB1440
C1
CH2
TVB1440
B1
EQ
SoC
A1
TVB1440
TVB1440
D1
Driver
TVB1440
C1
CH1
Driver
B1
EQ
CH0
A1
Display Source
EQ
TCON
I2C
EQ
CH3
Driver
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ECCN: 3E991
TVB1440
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematics...........................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
5
5
6
7
Absolute Maximum Ratings ......................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ...............................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3
8.4
8.5
8.6
9
Feature Description................................................... 9
Device Functional Modes.......................................... 9
Programming............................................................. 9
Register Maps ......................................................... 13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
10 Power Supply Recommendations ..................... 19
10.1 Power-Up Sequence ............................................. 19
10.2 Power-Down Sequence ........................................ 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Export Control Notice............................................
Glossary ................................................................
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
5 Revision History
Changes from Original (November 2014) to Revision A
•
2
Page
Changed text in the Package Specific section From: "The TVB1440 package has a 5.6 mm x 5.6 mm thermal pad."
To: "The TVB1440 package has a 4.1 mm x 4.1 mm thermal pad.".................................................................................... 21
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TVB1440
ECCN: 3E991
TVB1440
www.ti.com
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
6 Pin Configuration and Functions
VDD
RSVD3
OUT0n
21
VDD
IN1p
41
20
OUT1p
IN1n
42
19
OUT1n
VDD
43
18
GND
IN2p
44
17
OUT2p
IN2n
45
16
OUT2n
NC
46
15
VDD
IN3p
47
14
OUT3p
IN3n
48
1
3
4
5
6
7
8
9
13
12
OUT3n
2
26 25
24
RSVD2
RSVD1
10 11
GND
VDD
30 29 28 27
EN
22
40
TEST2
RSVD4
39
NC
TEST1
TEST3
IN0n
NC
GND
OUT0p
VDD
TEST4
23
SCL_CTL
VDD
38
SDA_CTL
TEST5
IN0p
ADDR
RSTN
36 35 34 33 32 31
37
VDD
TEST6
VDD
VCC
VCC
VQFN 0.5 mm Pitch
RGZ 48 Pin
Top View
Pin Functions
PIN
SIGNAL
NO.
DESCRIPTION
I/O
DATA LANES PINS
IN0p, IN0n
38, 39
IN1p, IN1n
41, 42
IN2p, IN2n
44, 45
IN3p, IN3n
47, 48
OUT0p, OUT0n
23, 22
OUT1p, OUT1n
20, 19
OUT2p, OUT2n
17, 16
OUT3p, OUT3n
14, 13
Lane 0 Differential Input
Input
(100Ω diff)
Lane 1 Differential Input
Lane 2 Differential Input
Lane 3 Differential Input
Lane 0 Differential Output
Output
(100Ω diff)
Lane 1 Differential Output
Lane 2 Differential Output
Lane 3 Differential Output
CONTROL PINS
ADDR
3
3-level Input
EN
26
I
NC
7, 40, 46
I2C Target Address Select.
Device Enable. This input incorporates internal pullup of 200 kΩ.
No Connect. These terminals may be left un-connected, or connect to GND.
RSTN
35
I
Active Low Device Reset. This is 1.1V input. This input includes a 150kΩ resistor to the VDDD core
supply. An external capacitor to GND is recommended on the RSTN input to provide a power-up delay.
This signal is used to place the TVB1440 into Shutdown mode for the lowest power consumption. When
the RSTN input is asserted, all outputs are high-impedance, and inputs are ignored; all I2C registers are
reset to their default values. At power up, the RSTN input must not be de-asserted until the VCC and VDD
supplies have reached at least the minimum recommended supply voltage level.
RSVD1
10
I
Reserved pins. Please connect the pin to GND through 1K resistor.
RSVD2
11
I
Reserved pins. Please connect the pin to VCC through 1K resistor.
RSVD3
27
I
Reserved pins. Please connect the pin to VCC through 1K resistor.
RSVD4
28
I
Reserved pins. Please connect the pin to GND through 1K resistor.
SCL_CTL
SDA_CTL
4
5
I/O
TEST1-6
8, 9, 29, 30,
33, 34
Bidirectional I2C interface to configure TVB1440. This interface is active independent of EN input but
inactive when RSTN is low.
Test Outputs. Do not connect.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TVB1440
3
ECCN: 3E991
TVB1440
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
www.ti.com
Pin Functions (continued)
PIN
SIGNAL
NO.
DESCRIPTION
I/O
SUPPLY AND GROUND PINS
GND
18, 24, 31,
PAD
Ground. Reference GND connections include the device package exposed thermal pad.
VDD
2, 6, 12, 15,
21, 25, 32,
37, 43
Low voltage supply for analog and digital core. Nominally 1.1V
VCC
1, 36
3.3V Supply
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Voltage range
(1)
(1)
MIN
MAX
VCC
–0.3
4
VDD
–0.3
1.3
HS Link I/O (OUTx, INx) Differential Voltage
–0.3
1.3
RSTN
–0.3
1.3
SCL_CTL, SDA_CTL, ADDR, EN
–0.3
4
UNIT
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
MIN
MAX
UNIT
-65
150
·C
Human body model (HBM) (1)
–2000
2000
Charged-device model (CDM) (2)
–500
500
TSTG
Storage temperature range
Electrostatic
discharge
(1)
(2)
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
VCC
Supply Voltage, IO
3
3.6
V
VDD
Supply Voltage, CORE
1
1.26
V
VIH
High-level input voltage for ADDR, EN
1.9
3.6
V
VIL
Low-level input voltage for ADDR, EN
0
0.8
V
VIH,RSTN
High-level input voltage for RSTN (typical hysteresis of 80mV)
VIL,RSTN
Low-level input voltage for RSTN (typical hysteresis of 80mV)
TA
Operating free-air temperature
fscl
I2C CK frequency at SCL_CTL (standard I2C mode (1))
(1)
4
0.75
V
0.3
0
V
85
°C
100
kHz
The local interface through SCL_CTL and SDA_CTL should follow standard mode I2C specifications
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TVB1440
ECCN: 3E991
TVB1440
www.ti.com
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
7.4 Thermal Information
THERMAL METRIC (1)
TVB1440
RθJA
Junction-to-ambient thermal resistance
35.1
RθJC(top)
Junction-to-case (top) thermal resistance
21.5
RθJB
Junction-to-board thermal resistance
11.7
ψJT
Junction-to-top characterization parameter
1.2
ψJB
Junction-to-board characterization parameter
11.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.7
(1)
UNIT
RGZ (48 Pin)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
(1)
TYP
MAX
UNIT
ICC
Supply current 4 lanes operation
130
230
mA
ISTDN
Shutdown supply current (1)
1.5
3
mA
IOD
Squelch (output disable) supply current
35
50
mA
VOD0
238
340
442
VOD1
357
510
663
484
690
897
700
1000
1300
VOD2
Output differential voltage swing
VOD3
PE0
0
PE1
3
Output pre-emphasis
PE2
dB
6
PE3
9
ROUT
Driver output impedance
I(TXSHORT)
Output pins short circuit current limit
V(SQUELCH)
Squelch threshold voltage for input signals (default)
(1)
mVpp
Ω
50
50
80
mA
mVpp
Values are VDD supply measurements; VCC supply measurements are 5 mA (typical) and 8 mA (max), with zero current in shutdown
mode.
7.6 Timing Requirements
MIN
tramp1
Time VDD must stable before VCC is applied
tramp2
tramp3
TYP
MAX
UNIT
10
µS
Time RSTN must remain asserted until VCC/VDD voltage has reached minimum
recommended operation
100
µS
Time device will be available for operation after a valid reset
400
mS
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TVB1440
5
ECCN: 3E991
TVB1440
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
www.ti.com
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
300
UNIT
tPD
Propagation delay time
tsk1
Intra-pair output skew (Figure 1)
20
ps
tsk2
Inter-pair output skew (Figure 1)
100
ps
Δtjit
Total peak-to-peak residual jitter
VOD0; PE0; EQ = 8dB; clean source; minimum input and output cabling; PRBS7 data
pattern.
15
ps
tsq_enter
Squelch entry time
Time from a loss of valid input signal to ML output off
120
µS
tsq_exit
Squelch exit time
Time from valid input signal available while in squelch mode to ML outputs on
1
µS
10
ps
Figure 1. Output Skew Definitions
6
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TVB1440
ECCN: 3E991
TVB1440
www.ti.com
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
7.8 Typical Characteristics
23
10
22
Total Output Jitter (ps) (pk-pk)
12
8
Gain (Hz)
6
4
2
0
-2
6 dB Setting
10 dB Setting
15 dB Setting
-4
-6
10M
21
20
19
18
17
16
15
14
100M
1G
Frequency (Hz)
10G
0
D001
20
40
60
80
Total Input Jitter (ps) (pk-pk)
100
120
D002
Figure 2. Typical EQ Gain Curves (simulations)
Figure 3. Jitter Performance with Optimal EQ Settings
Figure 4. 3.75-Gbps Input With 20 Inch Trace
Figure 5. 3.75-Gbps Output with 20 Inch Input Trace and
8-dB EQ Setting
Figure 6. 5-Gbps Input with 20 Inches Trace
Figure 7. 5-Gbps Output with 20 Inch Input Trace and
13-dB EQ Setting
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TVB1440
7
ECCN: 3E991
TVB1440
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
www.ti.com
8 Detailed Description
8.1 Overview
TVB1440 is a 4 channel HS re-driver signal conditioner for TV applications. I2C control provides the wide ranges
of flexibility to configure the device for optimal signal conditioning so that video data link between a source and
sink can achieve high fidelity. TVB1440 allows larger distance between a Chipset and TCON boards through its
excellent jitter cleaning capability.
The TVB1440 is optimized for power conscience applications. Apart from its low active power, TVB1440 contains
activity detection circuitry on the data link input that transitions to a low-power output disable mode in the
absence of a valid input signal. This activity detect circuit can be disabled if desired. The device also has a
shutdown mode when exercised results in 2 mW.
The TVB1440 receiver and driver provide input and output common mode voltage bias. It is required that both
receive and transmit end of the device is ac coupled in application use cases. Suggested value for the ac
coupling capacitors is 75-200 nF.
8.2 Functional Block Diagram
VDD
ADDR
ADDR
RRST=150k
VCC
VDD
GND
RSTN
EN
RESET
EN
REN=200k
VIterm
VBIAS
VCC
50
50
50
IN0p
EQ
50
OUT0p
Driver
IN0n
OUT0n
VIterm
50
VBIAS
50
50
50
IN1p
OUT1p
Driver
EQ
IN1n
OUT1n
VIterm
50
VBIAS
50
50
50
IN2p
EQ
IN2n
OUT2p
Driver
VIterm
50
50
50
IN3p
50
OUT3p
EQ
Driver
IN3n
OUT3n
ADDR
SCL_ CTL
SDA_ CTL
OUT2n
VBIAS
EQ_CTL
I2 C
Target
PE_CTL
CTRL
VOD_CTL
EN
8
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TVB1440
ECCN: 3E991
TVB1440
www.ti.com
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
8.3 Feature Description
8.3.1 Equalization
TVB1440 provides flexible continuous time linear equalization (CTLE) to compensate for large trace or cable loss
at its input resulting improved eye at the output signals. It has selectable control for receive equalization
accessible through I2C.
8.3.2 Configurable Output
Transmitter in each channel has 4 levels of pre-emphasis and 4 levels of output voltage swing settings which
enable optimum video signal performance from the TVB1440 to downstream receiver.
8.3.3 Squelch
TVB1440 has active Squelch feature that allows automatic shutdown of output drivers when it does not have
valid input signal. The feature can be disabled through I2C if not desired.
8.4 Device Functional Modes
8.4.1 Active Mode
Normal operation mode. The data lanes of TVB1440 work normally.
8.4.2 Shutdown Mode
Device is in lowest power mode. This mode is invoked by de-asserting RSTN or EN low.
8.4.3 Squelch Mode
The device does not have valid input signal. Output drivers are turned off.
8.5 Programming
8.5.1 Local I2C Interface
It is required to use the TVB1440’s local I2C interface to configure the TVB1440’s receivers (IN[3:0]P/N) and
transmitters (OUT[3:0]P/N). The TVB1440’s internal registers are accessed through the SCL_CTL pin and
SDA_CTL pin. The 7-bit I2C slave address of the TVB1440 is determined by the ADDR pin.
Table 1. TVB1440 I2C Slave Address Options
ADDR
7-BIT I2C SLAVE ADDRESS
READ SLAVE ADDRESS
WRITE SLAVE ADDRESS
Low (VIL)
7’b0101100
‘h59
‘h58
VCC/2 (VIM)
7’b0101101
‘h5B
‘h5A
High (VIH)
7’b0101110
‘h5D
‘h5C
Before adjusting the TVB1440’s registers, a writing a zero to bit 2 of address 04h is required to enable the
receiver and transmitter adjustments.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TVB1440
9
ECCN: 3E991
TVB1440
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
www.ti.com
8.5.2 Receiver (IN[3:0]P/N) Adjustments
8.5.2.1 Equalization Level
It is recommended to use the TVB1440 local I2C interface to configure the TVB1440 receiver equalization level.
Software should then enable equalization control by writing a one to EQ_I2C_ENABLE bit (bit 7 at address 05h).
After EQ_I2C_ENABLE is set, then software can program the equalization for each lane (IN[3:0]) to the
appropriate value. Refer to Table 2 for details on equalization settings for each lane.
Table 2. TVB1440 Equalization Levels
Address
Bits(s)
04h
2
Description
Access
Receiver and transmitter adjustment.
0 – configure receiver and transmitter using I2C (required)
1 – reserved (default)
RW
EQ_LEVEL_LANE0. This field selects the EQ gain level for Lane 0 (IN0P/N).
000 – 0 dB
001 – 2 dB (3.75Gbps); 2.5 dB (5Gbps)
010 – 3.5 dB (3.75Gbps); 5 dB (5Gbps)
011 – 5 dB (3.75Gbps); 6 dB (5Gbps)
100 – 6.5 dB (3.75Gbps); 8 dB (5Gbps)
101 – 8 dB (3.75Gbps); 11 dB (5Gbps)
110 – 9.5 dB (3.75Gbps); 13 dB (5Gbps)
111 – 12 dB (3.75Gbps); 15 dB (5Gbps)
RW
EQ_I2C_ENABLE. This field allows EQ control through I2C
0 – reserved (default)
1 – EQ level is set by I2C (required)
RW
05h
2:0
05h
7
07h
2:0
EQ_LEVEL_LANE1. This field selects the EQ gain level for Lane 1 (IN1P/N. Bit definition identical to
that of EQ_LEVEL_LANE0.
RW
09h
2:0
EQ_LEVEL_LANE2. This field selects the EQ gain level for Lane 2 (IN2P/N). Bit definition identical
to that of EQ_LEVEL_LANE0.
RW
0Bh
2:0
EQ_LEVEL_LANE3. This field selects the EQ gain level for Lane 3 (IN3P/N. Bit definition identical to
that of EQ_LEVEL_LANE0.
RW
8.5.2.2 Squelch Level
The TVB1440 squelch level defaults to 80mVpp. If it is necessary to adjust the squelch level, it can be done by
changing the SQUELCH_SENSITIVITY register located in the TVB1440’s Local I2C register space.
Table 3. Squelch Sensitivity Levels
Address
Bits(s)
5:4
03h
3
10
Description
Access
SQUELCH_SENSITIVITY. Main link squelch sensitivity is selected by this field, and determines the
transitions to and from the Output Disable mode.
00 – Main Link IN0P/N squelch detection threshold is set to 40mVpp.
01 – Main Link IN0P/N squelch detection threshold is set to 80mVpp. (Default)
10 – Main Link IN0P/N squelch detection threshold is set to 160mVpp.
11 – Main Link IN0P/N squelch detection threshold is set to 250mVpp.
RW
SQUELCH_ENABLE.
0 – Main Link IN0P/N squelch detection is enabled (default)
1 – Main Link IN0P/N squelch detection is disabled.
RW
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TVB1440
ECCN: 3E991
TVB1440
www.ti.com
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
8.5.3 Main Link Output [OUT[3:0]P/N] Adjustments
The TVB1440 Main link outputs (OUT[3:0]) must be set in link address space by following specified I2C access
method.
8.5.3.1 LINK Address Space
Access to and from the TVB1440 LINK address space is indirectly addressable through the local I2C registers as
illustrated in the Figure 8.
TVB1440's Local I2C
Address Space
1Ch
Local I2C
Acceses
TVB1440's Link
Address Space
LINK_ADDR_HIGH
1Dh
LINK_ADDR_MID
1Eh
LINK_ADDR_LOW
1Fh
LINK_DATA
20-bit LINK Register
Data Read/Write
Figure 8. Accessing TVB1440 LINK Registers
The configuration of these registers can be performed through the local I2C interface, where three registers (from
1Ch to 1Eh) are used as the address to the LINK register and another one (1Fh) as a data to be read/written.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TVB1440
11
ECCN: 3E991
TVB1440
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
www.ti.com
8.5.4 Example Script
The script below is for a Total Phase Aardvark I2C controller. Details on the Total Phase Aardvark I2C controller
can be obtained from the Total Phase website. This example is for a 5.0 Gbps data rate with 4 active lanes.
space
space
======Program the device=====
04 00 />
space
======Program Link Bandwidth Settings to 5Gbps======LINK 00100h=====
1C 00 />
1D 01 />
1E 00 />
1F 14 />
space
space
======Program Num of Lanes to 4.s======LINK 00101h=====
1C 00 />
1D 01 />
1E 01 />
1F 04 />
space
======Program VOD L1 and Pre-Emphasis L0 for Lane 0======LINK 00103h=====
1C 00 />
1D 01 />
1E 03 />
1F 01 />
space
======Program VOD L1 and Pre-Emphasis L0 for Lane 1======LINK 00104h=====
1C 00 />
1D 01 />
1E 04 />
1F 01 />
space
======Program VOD L1 and Pre-Emphasis L0 for Lane 2======LINK 00105h=====
1C 00 />
1D 01 />
1E 05 />
1F 01 />
space
======Program VOD L1 and Pre-Emphasis L0 for Lane 3======LINK 00106h=====
1C 00 />
1D 01 />
1E 06 />
1F 01 />
space
======Set Power Mode to Normal======LINK 00600h=====
1C 00 />
1D 06 />
1E 00 />
1F 01 />
space
=====May want to adjust Squelch Level===
03 10 />
space
=====Enable EQ===
05 80 />
space
=====Set EQ level to 11dB(5Gbps) for lane 0===
05 85 />
space
=====Set EQ level to 11dB(5Gbps) for lane 1===
07 05 />
space
=====Set EQ level to 11dB(5Gbps) for lane 2===
09 05 />
space
=====Set EQ level to 11dB(5Gbps) for lane 3===
0B 05 />
12
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TVB1440
ECCN: 3E991
TVB1440
www.ti.com
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
8.6 Register Maps
Table 4. TVB1440 LINK Registers
LINK Address
00100h
00101h
00103h
00104h
00105h
00106h
00600h
NAME
LINK_BW_SET
LANE_COUNT_SET
LANE0_SET
LANE1_SET
LANE2_SET
LANE3_SET
SET_POWER
Value Written
Value Read
06h
00h
工商网监
湘ICP备2023018690号
