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TXS0206A
SCES833B – NOVEMBER 2011 – REVISED APRIL 2016
TXS0206A SD Card Voltage-Translation Transceiver
1 Features
3 Description
•
The TXS0206A is a level shifter for interfacing
microprocessors with MultiMediaCards (MMCs),
secure digital (SD) cards, and Memory Stick™ cards.
1
•
Level Translator
– VCCA and VCCB Range of 1.1 V to 3.6 V
– Fast Propagation Delay (4.4 ns Maximum
When Translating Between 1.8 V and 3 V)
ESD Protection Exceeds JESD 22
– 2500-V Human-Body Model (A114-B)
– 250-V Machine Model (A115-A)
– 1500-V Charged-Device Model (C101)
2 Applications
•
•
•
•
Mobile Phones
Tablet PCs
Notebooks
Ultrabook Computers
The voltage-level translator has two supply voltage
pins. VCCA as well as VCCB can be operated over the
full range of 1.1 V to 3.6 V. The TXS0206A enables
system designers to easily interface applications
processors or digital basebands to memory cards and
SDIO peripherals operating at a different I/O voltage
level.
The TXS0206A is offered in a 20-bump wafer chip
scale package (WCSP). This package has
dimensions of 1.96 mm × 1.56 mm, with a 0.4-mm
ball pitch for effective board-space savings. Memory
cards are widely used in mobile phones, PDAs, digital
cameras, personal media players, camcorders, settop boxes, etc. Low static power consumption and
small package size make the TXS0206A an ideal
choice for these applications.
Device Information(1)
PART NUMBER
TXS0206A
PACKAGE
BODY SIZE
DSBGA (20)
1.96 mm × 1.56 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SD/MMC
Controller
TXS0206A
9 1 2 3 4 5 6 78
Application Example
SD/MMC
Card
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TXS0206A
SCES833B – NOVEMBER 2011 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements—VCCA = 1.2 V ± 0.1 V ........... 7
Timing Requirements—VCCA = 1.8 V ± 0.15 V ......... 8
Timing Requirements—VCCA = 3.3 V ± 0.3 V ........... 8
Switching Characteristics—VCCA = 1.2 V ± 0.1 V .... 9
Switching Characteristics—VCCA = 1.8 V ± 0.15 V
................................................................................. 10
Switching Characteristics—VCCA = 3.3 V ± 0.3 V . 11
Operating Characteristics —VCCA = 1.2 V ............ 12
Operating Characteristics —VCCA = 1.8 V ............ 13
Operating Characteristics — VCCA = 3.3 V ........... 13
Typical Characteristics .......................................... 14
7
8
Parameter Measurement Information ................ 15
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
18
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
9.3 System Examples ................................................... 21
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2012) to Revision B
Page
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
•
Deleted the ordering information. See POA at the end of the datasheet............................................................................... 1
2
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SCES833B – NOVEMBER 2011 – REVISED APRIL 2016
5 Pin Configuration and Functions
YFP Package
20–Pin DSBGA
Top View
1 2 3 4
A
B
C
D
E
Pin Assignments
1
2
3
4
A
DAT2A
VCCA
WP
DAT2B
B
DAT3A
CD
VCCB
DAT3B
C
CMDA
GND
GND
CMDB
D
DAT0A
CLKA
CLKB
DAT0B
E
DAT1A
CLK-f
EN
DAT1B
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
A1
DAT2A
I/O
Data bit 2 connected to host. Referenced to VCCA. Includes a 40-kΩ pullup resistor to VCCA.
A2
VCCA
Pwr
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
A3
WP
O
Connected to write protect on the mechanical connector. The WP pin has an internal 100-kΩ (± 30%)
pullup resistor to VCCA. Leave unconnected if not used.
A4
DAT2B
I/O
Data bit 2 connected to memory card. Referenced to VCCB. Includes a 40-kΩ pullup resistor to VCCB.
B1
DAT3A
I/O
Data bit 3 connected to host. Referenced to VCCA. Includes a 40-kΩ pullup resistor to VCCA.
B2
CD
O
Connected to card detect on the mechanical connector. The CD pin has an internal 100-kΩ (± 30%)
pullup resistor to VCCA. Leave unconnected if not used.
B3
VCCB
Pwr
B-port supply voltage. VCCB powers all B-port I/Os.
B4
DAT3B
I/O
Data bit 3 connected to memory card. Referenced to VCCB. Includes a 40-kΩ pullup resistor to VCCB.
C1
CMDA
I/O
Command bit connected to host. Referenced to VCCA. Includes a 40-kΩ pullup resistor to VCCA.
C2
GND
—
Ground
C3
GND
—
Ground
C4
CMDB
I/O
Command bit connected to memory card. Referenced to VCCB. Includes a 40-kΩ pullup resistor to VCCB.
D1
DAT0A
I/O
Data bit 0 connected to host. Referenced to VCCA. Includes a 40-kΩ pullup resistor to VCCA.
D2
CLKA
I
Clock signal connected to host. Referenced to VCCA.
D3
CLKB
O
Clock signal connected to memory card. Referenced to VCCB.
D4
DAT0B
I/O
Data bit 0 connected to memory card. Referenced to VCCB. Includes a 40-kΩ pullup resistor to VCCB.
E1
DAT1A
I/O
Data bit 1 connected to host. Referenced to VCCA. Includes a 40-kΩ pullup resistor to VCCA.
E2
CLK-f
O
Clock feedback to host for resynchronizing data to a processor. Leave unconnected if not used.
Enable/disable control. Pull EN low to place all outputs in Hi-Z state. Referenced to VCCA.
E3
EN
I
E4
DAT1B
I/O
Data bit 1 connected to memory card. Referenced to VCCB. Includes a 40-kΩ pullup resistor to VCCB.
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SCES833B – NOVEMBER 2011 – REVISED APRIL 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCCA
Supply voltage, A-Port
VCCB
Supply voltage, B-Port
VI
Input voltage
MIN
MAX
UNIT
–0.5
4.6
V
V
–0.5
4.6
I/O ports (A port)
–0.5
4.6
I/O ports (B port)
–0.5
4.6
Control inputs
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off
state
VO
Voltage range applied to any output in the high or low state
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCCA or GND
±100
mA
150
°C
Tstg
(1)
Storage temperature
–65
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
Machine model (MM)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
See (1)
VCCA
VCCB
MIN
MAX
UNIT
VCCA
Supply voltage
1.1
3.6
V
VCCB
Supply voltage
1.1
3.6
V
VCCI – 0.2
VCCI
VCCI × 0.65
VCCI
0
0.15
High-level input
voltage
VIH
Low-level input
voltage
VIL
VO
Output voltage
IOH
A-Port CMD and
DATA I/Os
B-Port CMD and
DATA I/Os
1.1 V to 1.95 V
1.1 V to 1.95 V
1.95 V to 3.6 V
1.95 V to 3.6 V
EN and CLKA
1.1 V to 3.6 V
1.1 V to 3.6 V
A-Port CMD and
DATA I/Os
B-Port CMD and
DATA I/Os
1.1 V to 1.95 V
1.1 V to 1.95 V
1.95 V to 3.6 V
1.95 V to 3.6 V
EN and CLKA
1.1 V to 3.6 V
1.1 V to 3.6 V
0
VCCI × 0.35
Active state
0
VCCO
3-state
0
3.6
High-level output current (CLK-f output)
1.1 V to 3.6 V
–100
1.1 V to 1.3 V
–0.5
1.4 V to 1.6 V
1.65 V to 1.95 V
IOL
Low-level output current (CLK-f output)
–2
–8
1.1 V to 3.6 V
100
1.1 V to 1.3 V
0.5
2
IOL
Low-level output current (CLK output)
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
1.1 V to 3.6 V
1.1 V to 3.6 V
mA
μA
mA
4
3 V to 3.6 V
High-level output current (CLK output)
µA
1
1.1 V to 3.6 V
2.3 V to 2.7 V
IOH
V
–4
3 V to 3.6 V
1.65 V to 1.95 V
V
–1
1.1 V to 3.6 V
2.3 V to 2.7 V
1.4 V to 1.6 V
V
8
1.1 V to 3.6 V
–100
1.1 V to 1.3 V
–0.5
1.4 V to 1.6 V
–1
1.65 V to 1.95 V
–2
2.3 V to 2.7 V
–4
3 V to 3.6 V
–8
1.1 V to 3.6 V
100
1.1 V to 1.3 V
0.5
1.4 V to 1.6 V
1
1.65 V to 1.95 V
2
2.3 V to 2.7 V
4
3 V to 3.6 V
8
–40
μA
mA
µA
mA
5
ns/V
85
°C
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
TXS0206A
THERMAL METRIC (1)
YFP (DSBGA)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
(1)
71.1
°C/W
Junction-to-case (top) thermal resistance
0.5
°C/W
Junction-to-board thermal resistance
10.4
°C/W
2
°C/W
10.4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
IOH = –0.5 mA
A port
(CLK-f output)
VOH
A port
(DAT and CMD
outputs)
A port
(CLK-f output)
VOL
VOH
B port
(DAT output)
(1)
6
MIN
1.1 V to 3.6 V 1.65 V to 3.6 V
TYP (1)
MAX
UNIT
VCCA × 0.8
1.65 V to 3.6 V
0.8
IOH = –1 mA
1.4 V
1.65 V to 3.6 V
1.05
IOH = –2 mA
1.65 V
1.65 V to 3.6 V
1.2
IOH = –4 mA
2.3 V
1.65 V to 3.6 V
1.75
IOH = –8 mA
3V
1.65 V to 3.6 V
2.3
IOH = –20 μA
1.1 V to 3.6 V 1.65 V to 3.6 V
VCCA × 0.8
IOL = 100 μA
1.1 V to 3.6 V 1.65 V to 3.6 V
V
VCCA × 0.2
IOL = 0.5 mA
1.1 V
1.65 V to 3.6 V
0.35
IOL = 1 mA
1.4 V
1.65 V to 3.6 V
0.35
IOL = 2 mA
1.65 V
1.65 V to 3.6 V
0.45
IOL = 4 mA
2.3 V
1.65 V to 3.6 V
0.55
IOL = 8 mA
3V
1.65 V to 3.6 V
0.7
1.1 V
1.65 V to 3.6 V
0.4
IOL = 180 μA
1.4 V
1.65 V to 3.6 V
0.4
IOL = 220 μA
1.65 V
1.65 V to 3.6 V
0.4
IOL = 300 μA
2.3 V
1.65 V to 3.6 V
0.4
3V
1.65 V to 3.6 V
IOL = 400 μA
B port
(CLK output)
VCCB
1.1 V
IOL = 135 μA
A port
(DAT and CMD
outputs)
VCCA
V
V
0.55
IOH = –100 μA
1.1 V to 3.6 V 1.65 V to 3.6 V
IOH = –2 mA
1.1 V to 3.6 V
1.65 V
1.2
IOH = –4 mA
1.1 V to 3.6 V
2.3 V
1.75
IOH = –8 mA
1.1 V to 3.6 V
3V
2.3
IOH = –20 μA
1.1 V to 3.6 V 1.65 V to 3.6 V
VCCB × 0.8
V
VCCB × 0.8
All typical values are at TA = 25°C.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
B port
VOL
B port
(DAT output)
TEST CONDITIONS
VCCA
VCCB
TYP (1)
MIN
MAX
IOL = 100 μA
1.1 V to 3.6 V 1.65 V to 3.6 V
IOL = 2 mA
1.1 V to 3.6 V
1.65 V
0.45
IOL = 4 mA
1.1 V to 3.6 V
2.3 V
0.55
IOL = 8 mA
1.1 V to 3.6 V
3V
0.7
IOL = 135 μA
1.1 V to 3.6 V 1.65 V to 3.6 V
0.4
IOL = 220 μA
1.1 V to 3.6 V
1.65 V
0.4
IOL = 300 μA
1.1 V to 3.6 V
2.3 V
0.4
3V
0.55
UNIT
VCCB × 0.2
V
V
IOL = 300 μA
1.1 V to 3.6 V
II
Control inputs
VI = VCCA or GND
1.1 V to 3.6 V 1.65 V to 3.6 V
±1
μA
ICCA
A port
VI = VCCI, IO = 0
1.1 V to 3.6 V 1.65 V to 3.6 V
7
μA
ICCB
B port
VI = VCCI, IO = 0
1.1 V to 3.6 V 1.65 V to 3.6 V
11
μA
Cio
Ci
A port
5.5
6.5
B port
7
9.5
Control inputs
VI = VCCA or GND
3.5
4.5
Clock input
VI = VCCA or GND
3
4
MAX
UNIT
pF
pF
6.6 Timing Requirements—VCCA = 1.2 V ± 0.1 V
over recommended operating free-air temperature range (unless otherwise noted)
VCC
Push-pull
driving
VCCB = 1.8 V ± 0.15 V
40
VCCB = 3.3 V ± 0.3 V
40
Open-drain
driving
VCCB = 1.8 V ± 0.15 V
1
Command
Data rate
Clock
Push-pull
driving
Data
tW
1
40
VCCB = 3.3 V ± 0.3 V
40
VCCB = 1.8 V ± 0.15 V
40
VCCB = 3.3 V ± 0.3 V
40
VCCB = 1.8 V ± 0.15 V
25
VCCB = 3.3 V ± 0.3 V
25
Open-drain
driving
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
10
VCCB = 3.3 V ± 0.3 V
8.3
VCCB = 1.8 V ± 0.15 V
25
VCCB = 3.3 V ± 0.3 V
25
Clock
Push-pull
driving
Data
VCCB = 3.3 V ± 0.3 V
VCCB = 1.8 V ± 0.15 V
Push-pull
driving
Command
Pulse
duration
MIN
Mbps
MHz
Mbps
ns
µs
ns
ns
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6.7 Timing Requirements—VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range (unless otherwise noted)
VCC
VCCB = 1.8 V ± 0.15 V
60
VCCB = 3.3 V ± 0.3 V
60
Open-drain
driving
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
60
VCCB = 3.3 V ± 0.3 V
60
VCCB = 1.8 V ± 0.15 V
60
VCCB = 3.3 V ± 0.3 V
60
Data rate
Clock
Push-pull
driving
Data
Push-pull
driving
VCCB = 1.8 V ± 0.15 V
17
VCCB = 3.3 V ± 0.3 V
17
Open-drain
driving
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
8.3
VCCB = 3.3 V ± 0.3 V
8.3
VCCB = 1.8 V ± 0.15 V
17
VCCB = 3.3 V ± 0.3 V
17
Command
tW
MAX
Push-pull
driving
Command
Pulse
duration
MIN
Clock
Push-pull
driving
Data
UNIT
Mbps
MHz
Mbps
ns
µs
ns
ns
6.8 Timing Requirements—VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted)
VCC
60
VCCB = 3.3 V ± 0.3 V
60
Open-drain
driving
VCCB = 1.8 V ± 0.15 V
1
Data rate
Clock
Push-pull
driving
Data
VCCB = 3.3 V ± 0.3 V
55
VCCB = 1.8 V ± 0.15 V
60
VCCB = 3.3 V ± 0.3 V
60
17
VCCB = 3.3 V ± 0.3 V
17
Open-drain
driving
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
9
VCCB = 3.3 V ± 0.3 V
9
VCCB = 1.8 V ± 0.15 V
17
VCCB = 3.3 V ± 0.3 V
17
Push-pull
driving
8
1
55
VCCB = 1.8 V ± 0.15 V
Clock
Data
VCCB = 3.3 V ± 0.3 V
VCCB = 1.8 V ± 0.15 V
Push-pull
driving
Command
Pulse
duration
MAX
VCCB = 1.8 V ± 0.15 V
Command
tW
MIN
Push-pull
driving
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UNIT
Mbps
MHz
Mbps
ns
µs
ns
ns
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6.9 Switching Characteristics—VCCA = 1.2 V ± 0.1 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CMDA
CMDB
CMDB
CMDA
CLKA
CLKB
tpd
DATxA
DATxB
DATxB
DATxA
CLKA
CLK-f
EN
B-port
ten
EN
A-port
EN
B-port
tdis
EN
A-port
CMDA rise time
trA
CLK-f rise time
DATxA rise time
CMDB rise time
trB
CLKB rise time
DATxB rise time
CMDA fall time
tfA
CLK-f fall time
DATxA fall time
CMDB fall time
tfB
CLKB fall time
DATxB fall time
tSK(O)
Channel-to-channel
skew
VCC
MIN
MAX
VCCB = 1.8 V ± 0.15 V
5.7
VCCB = 3.3 V ± 0.3 V
4.4
VCCB = 1.8 V ± 0.15 V
6.7
VCCB = 3.3 V ± 0.3 V
5.8
VCCB = 1.8 V ± 0.15 V
6.2
VCCB = 3.3 V ± 0.3 V
4.5
VCCB = 1.8 V ± 0.15 V
7.6
VCCB = 3.3 V ± 0.3 V
7.5
VCCB = 1.8 V ± 0.15 V
6.3
VCCB = 3.3 V ± 0.3 V
4.6
VCCB = 1.8 V ± 0.15 V
12
VCCB = 3.3 V ± 0.3 V
7.9
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
412
VCCB = 3.3 V ± 0.3 V
363
VCCB = 1.8 V ± 0.15 V
423
VCCB = 3.3 V ± 0.3 V
UNIT
ns
µs
ns
422
VCCB = 1.8 V ± 0.15 V
3.5
8.4
VCCB = 3.3 V ± 0.3 V
3.4
8.1
VCCB = 1.8 V ± 0.15 V
1
4.7
VCCB = 3.3 V ± 0.3 V
1
4.1
VCCB = 1.8 V ± 0.15 V
3.5
8.4
VCCB = 3.3 V ± 0.3 V
3.4
8.1
VCCB = 1.8 V ± 0.15 V
1.4
6.5
VCCB = 3.3 V ± 0.3 V
0.6
3.1
VCCB = 1.8 V ± 0.15 V
0.6
5.9
VCCB = 3.3 V ± 0.3 V
0.5
4.3
VCCB = 1.8 V ± 0.15 V
1.4
10.9
VCCB = 3.3 V ± 0.3 V
0.6
5
VCCB = 1.8 V ± 0.15 V
2.4
5.7
VCCB = 3.3 V ± 0.3 V
2
5.1
VCCB = 1.8 V ± 0.15 V
0.8
2.5
VCCB = 3.3 V ± 0.3 V
0.8
3
VCCB = 1.8 V ± 0.15 V
2.4
5.7
VCCB = 3.3 V ± 0.3 V
1.9
5.1
VCCB = 1.8 V ± 0.15 V
1.2
5.4
VCCB = 3.3 V ± 0.3 V
0.6
3.6
VCCB = 1.8 V ± 0.15 V
0.6
6.3
VCCB = 3.3 V ± 0.3 V
0.5
4
VCCB = 1.8 V ± 0.15 V
0.6
6.3
VCCB = 3.3 V ± 0.3 V
0.5
3.6
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
ns
ns
ns
ns
ns
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Switching Characteristics—VCCA = 1.2 V ± 0.1 V (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
Push-pull driving
Command
Open-drain driving
Max data rate
Clock
Data
VCC
MIN
MAX
VCCB = 1.8 V ± 0.15 V
40
VCCB = 3.3 V ± 0.3 V
40
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
40
VCCB = 3.3 V ± 0.3 V
60
VCCB = 1.8 V ± 0.15 V
40
VCCB = 3.3 V ± 0.3 V
40
UNIT
Mbps
MHz
Mbps
6.10 Switching Characteristics—VCCA = 1.8 V ± 0.15 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CMDA
CMDB
CMDB
CMDA
CLKA
CLKB
tpd
DATxA
DATxB
DATxB
DATxA
CLKA
CLK-f
EN
B-port
ten
EN
A-port
EN
B-port
tdis
EN
A-port
CMDA rise time
trA
CLK-f rise time
DATxA rise time
CMDB rise time
trB
CLKB rise time
DATxB rise time
10
VCC
MIN
MAX
VCCB = 1.8 V ± 0.15 V
4.9
VCCB = 3.3 V ± 0.3 V
3.3
VCCB = 1.8 V ± 0.15 V
5.6
VCCB = 3.3 V ± 0.3 V
3.6
VCCB = 1.8 V ± 0.15 V
5.4
VCCB = 3.3 V ± 0.3 V
3.4
VCCB = 1.8 V ± 0.15 V
5
VCCB = 3.3 V ± 0.3 V
4.4
VCCB = 1.8 V ± 0.15 V
5.4
VCCB = 3.3 V ± 0.3 V
3.5
VCCB = 1.8 V ± 0.15 V
10.2
VCCB = 3.3 V ± 0.3 V
5.7
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
411
VCCB = 3.3 V ± 0.3 V
411
VCCB = 1.8 V ± 0.15 V
413
VCCB = 3.3 V ± 0.3 V
ns
µs
ns
361
VCCB = 1.8 V ± 0.15 V
2.1
4.5
VCCB = 3.3 V ± 0.3 V
2.1
4.1
VCCB = 1.8 V ± 0.15 V
0.6
2.5
VCCB = 3.3 V ± 0.3 V
0.6
2.3
VCCB = 1.8 V ± 0.15 V
1.8
4.5
VCCB = 3.3 V ± 0.3 V
1.8
4.2
VCCB = 1.8 V ± 0.15 V
1.4
6.6
VCCB = 3.3 V ± 0.3 V
0.7
3.8
VCCB = 1.8 V ± 0.15 V
0.5
5.8
VCCB = 3.3 V ± 0.3 V
0.5
4.4
VCCB = 1.8 V ± 0.15 V
1.4
10.8
VCCB = 3.3 V ± 0.3 V
0.7
8
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UNIT
ns
ns
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Switching Characteristics—VCCA = 1.8 V ± 0.15 V (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CMDA fall time
tfA
CLK-f fall time
DATxA fall time
CMDB fall time
tfB
CLKB fall time
DATxB fall time
Channel-to-channel
skew
tSK(O)
Push-pull driving
Command
Open-drain driving
Max data rate
Clock
Data
VCC
MIN
MAX
VCCB = 1.8 V ± 0.15 V
0.4
3.4
VCCB = 3.3 V ± 0.3 V
0.3
2.9
VCCB = 1.8 V ± 0.15 V
0.3
2.8
VCCB = 3.3 V ± 0.3 V
0.3
2.8
VCCB = 1.8 V ± 0.15 V
0.4
3.4
VCCB = 3.3 V ± 0.3 V
0.3
2.9
VCCB = 1.8 V ± 0.15 V
1.1
6.3
VCCB = 3.3 V ± 0.3 V
0.6
3.7
VCCB = 1.8 V ± 0.15 V
0.6
8.7
VCCB = 3.3 V ± 0.3 V
0.5
4.1
VCCB = 1.8 V ± 0.15 V
1.2
7
VCCB = 3.3 V ± 0.3 V
0.2
4
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
60
VCCB = 3.3 V ± 0.3 V
60
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
60
VCCB = 3.3 V ± 0.3 V
60
VCCB = 1.8 V ± 0.15 V
60
VCCB = 3.3 V ± 0.3 V
60
UNIT
ns
ns
ns
Mbps
MHz
Mbps
6.11 Switching Characteristics—VCCA = 3.3 V ± 0.3 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CMDA
CMDB
CMDB
CLKA
CMDA
CLKB
tpd
DATxA
DATxB
DATxB
DATxA
CLKA
CLK-f
EN
B-port
ten
EN
EN
A-port
B-port
tdis
EN
A-port
VCC
MIN
MAX
VCCB = 1.8 V ± 0.15 V
5.3
VCCB = 3.3 V ± 0.3 V
3.2
VCCB = 1.8 V ± 0.15 V
5.1
VCCB = 3.3 V ± 0.3 V
3
VCCB = 1.8 V ± 0.15 V
4.8
VCCB = 3.3 V ± 0.3 V
3.1
VCCB = 1.8 V ± 0.15 V
5.1
VCCB = 3.3 V ± 0.3 V
3.2
VCCB = 1.8 V ± 0.15 V
9.6
VCCB = 3.3 V ± 0.3 V
5.1
VCCB = 1.8 V ± 0.15 V
6.8
VCCB = 3.3 V ± 0.3 V
4.2
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
410
VCCB = 3.3 V ± 0.3 V
364
VCCB = 1.8 V ± 0.15 V
396
VCCB = 3.3 V ± 0.3 V
398
UNIT
ns
µs
ns
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Switching Characteristics—VCCA = 3.3 V ± 0.3 V (continued)
over operating free-air temperature range (unless otherwise noted)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
CMDA rise time
trA
CLK-f rise time
DATxA rise time
CMDB rise time
trB
CLKB rise time
DATxB rise time
CMDA fall time
tfA
CLK-f fall time
DATxA fall time
CMDB fall time
tfB
CLKB fall time
DATxB fall time
Channel-to-channel
skew
tSK(O)
Push-pull driving
Command
Open-drain driving
Max data rate
Clock
Data
VCC
MIN
MAX
VCCB = 1.8 V ± 0.15 V
1.4
4.2
VCCB = 3.3 V ± 0.3 V
1.4
4.2
VCCB = 1.8 V ± 0.15 V
0.5
1.5
VCCB = 3.3 V ± 0.3 V
0.5
1.4
VCCB = 1.8 V ± 0.15 V
1.4
3.4
VCCB = 3.3 V ± 0.3 V
1.3
3
VCCB = 1.8 V ± 0.15 V
1.4
6.4
VCCB = 3.3 V ± 0.3 V
0.9
4
VCCB = 1.8 V ± 0.15 V
0.6
5.9
VCCB = 3.3 V ± 0.3 V
0.5
4.4
VCCB = 1.8 V ± 0.15 V
1.4
14
VCCB = 3.3 V ± 0.3 V
0.9
14
VCCB = 1.8 V ± 0.15 V
0.8
2.3
VCCB = 3.3 V ± 0.3 V
0.8
2.3
VCCB = 1.8 V ± 0.15 V
0.4
1.3
VCCB = 3.3 V ± 0.3 V
0.4
1.3
VCCB = 1.8 V ± 0.15 V
0.8
2.2
VCCB = 3.3 V ± 0.3 V
0.7
2
VCCB = 1.8 V ± 0.15 V
0.8
6.2
VCCB = 3.3 V ± 0.3 V
0.8
5
VCCB = 1.8 V ± 0.15 V
0.6
7.8
VCCB = 3.3 V ± 0.3 V
0.5
4.3
VCCB = 1.8 V ± 0.15 V
0.7
6.8
VCCB = 3.3 V ± 0.3 V
0.6
5
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
60
VCCB = 3.3 V ± 0.3 V
60
VCCB = 1.8 V ± 0.15 V
1
VCCB = 3.3 V ± 0.3 V
1
VCCB = 1.8 V ± 0.15 V
55
VCCB = 3.3 V ± 0.3 V
55
VCCB = 1.8 V ± 0.15 V
60
VCCB = 3.3 V ± 0.3 V
60
UNIT
ns
ns
ns
ns
ns
Mbps
MHz
Mbps
6.12 Operating Characteristics —VCCA = 1.2 V
TA = 25°C
TEST
CONDITIONS
PARAMETER
A-port input,
B-port output
CpdA (1)
B-port input,
A-port output
A-port input,
B-port output
B-port input,
A-port output
(1)
12
VCCB TYP
1.8 V
3.3 V
CLK Enabled
15.1
15
DATA Enabled
9.26
9.19
12.4
11.9
0.1
0.1
DATA Disabled
1.3
1.3
DATA Disabled
0.1
0.1
DATA Enabled
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
CLK Disabled
UNIT
pF
Power dissipation capacitance per transceiver.
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Operating Characteristics —VCCA = 1.2 V (continued)
TA = 25°C
TEST
CONDITIONS
PARAMETER
A-port input,
B-port output
CpdB (1)
B-port input,
A-port output
A-port input,
B-port output
B-port input,
A-port output
VCCB TYP
1.8 V
3.3 V
26.7
30.3
25.6
27
16.38
19.91
0.1
0.1
CLK Disabled
0.1
0.1
DATA Disabled
1.1
0.8
DATA Enabled
CLK Enabled
DATA Enabled
DATA Disabled
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
UNIT
pF
6.13 Operating Characteristics —VCCA = 1.8 V
TA = 25°C
TEST
CONDITIONS
PARAMETER
A-port input,
B-port output
CpdA (1)
B-port input,
A-port output
A-port input,
B-port output
CpdB (1)
3.3 V
CLK Enabled
17.5
17.1
DATA Enabled
9.96
9.82
15.6
14
0.1
0.1
DATA Enabled
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
CLK Disabled
DATA Disabled
1.3
1.3
B-port input,
A-port output
DATA Disabled
0.1
0.1
A-port input,
B-port output
DATA Enabled
26
28.5
25.8
27
16.69
19.6
0.1
0.1
CLK Disabled
0.1
0.1
DATA Disabled
1.1
0.8
B-port input,
A-port output
A-port input,
B-port output
B-port input,
A-port output
(1)
VCCB TYP
1.8 V
CLK Enabled
DATA Enabled
DATA Disabled
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
UNIT
pF
pF
Power dissipation capacitance per transceiver.
6.14 Operating Characteristics — VCCA = 3.3 V
TA = 25°C
TEST
CONDITIONS
PARAMETER
A-port input,
B-port output
CpdA
(1)
B-port input,
A-port output
A-port input,
B-port output
B-port input,
A-port output
(1)
VCCB TYP
1.8 V
3.3 V
CLK Enabled
17.5
17.1
DATA Enabled
12.50
13.29
15.6
14
0.1
0.1
DATA Disabled
1.3
1.3
DATA Disabled
0.1
0.1
DATA Enabled
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
CLK Disabled
UNIT
pF
Power dissipation capacitance per transceiver.
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Operating Characteristics — VCCA = 3.3 V (continued)
TA = 25°C
A-port input,
B-port output
1.8 V
3.3 V
26
28.5
25.8
27
16.67
19.92
0.1
0.1
CLK Disabled
0.1
0.1
DATA Disabled
1.1
0.8
DATA Enabled
CLK Enabled
B-port input,
A-port output
CpdB (1)
VCCB TYP
TEST
CONDITIONS
PARAMETER
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
DATA Enabled
A-port input,
B-port output
DATA Disabled
B-port input,
A-port output
UNIT
pF
6.15 Typical Characteristics
0.6
0.6
Low-Level Output Voltage (V)
Low-Level Output Voltage (V)
0.7
0.5
0.4
0.3
0.2
VCCA
= 1.2
1.2 V
V
VCCA =
VCCA =
VCCA
= 1.8
1.8 V
V
0.1
0.0
0.4
0.3
0.2
0.1
0.0
0.0
0.3
0.5
0.8
1.0
1.3
1.5
1.8
Low-Level Current with VIL = 0 V (mA)
2.0
0
5
10
15
20
25
Low-Level Current with VIL = 0 V (mA)
C001
Figure 1. Low-Level Output Voltage (VOL(DATxB)) vs LowLevel Current (IOL(DATxA))
14
0.5
30
C002
Figure 2. Low-Level Output Voltage (CLKB) vs Low-Level
Current (CLKA)
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7 Parameter Measurement Information
VCCI
VCCO
VCCI
VCCO
DUT
IN
DUT
IN
OUT
OUT
1M
15 pF
15 pF
1M
DATA RATE, PULSE DURATION, PROPAGATION DELAY,
OUTPUT RISE AND FALL TIME MEASUREMENT USING
AN OPEN-DRAIN DRIVER
DATA RATE, PULSE DURATION, PROPAGATION DELAY,
OUTPUT RISE AND FALL TIME MEASUREMENT USING
A PUSH-PULL DRIVER
2 × VCCO
50 k
From Output
Under Test
15 pF
S1
Open
50 k
LOAD CIRCUIT FOR ENABLE/DISABLE
TIME MEASUREMENT
TEST
S1
tPZL/tPLZ
tPHZ/tPZH
2 × VCCO
Open
tw
VCCI
VCCI/2
Input
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VCCO/2
0.9
VCCO
0.1
VCCO
VOH
VCCO/2
VOL
tr
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VCCO
VCCO/2
0.1
VCCO
VOL
tPHZ
tPZH
0.9
VOH
VCCO
VCCO/2
0V
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The TXS0206A is a complete application-specific voltage-translator designed to bridge the digital switching
compatibility gap and interface logic threshold levels between a micrprocessor with MMC, SD, and Memory
Stick™ cards. It is intended to be used in a point-to-point topology when interfacing these devices that may or
may not be operating at different interface voltages.
8.2 Functional Block Diagram
VCCA
VCCB
EN
CLKA
CLKB
CLK-f
VCCA
VCCB
One-Shot
R1
R2
Translator
One-Shot
CMDA
CMDB
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
One-Shot
R1
R2
Translator
One-Shot
DAT0A
DAT0B
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
One-Shot
R1
R2
Translator
One-Shot
DAT1A
DAT1B
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
One-Shot
R1
R2
Translator
One-Shot
DAT2A
DAT2B
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
One-Shot
R1
R2
Translator
One-Shot
DAT3A
DAT3B
Gate Control
One-Shot
Translator
One-Shot
VCCA
100 kW
WP
100 kW
CD
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8.3 Feature Description
8.3.1 Architecture
The CLKA, CLKB, and CLK-f subsystem interfaces consist of a fully-buffered voltage translator design that has
its output transistors to source and sink current optimized for drive strength. CLKA is a CMOS input and
therefore must not be left floating.
The SDIO lines comprise a semi-buffered auto-direction-sensing based translator architecture (see Figure 4) that
does not require a direction-control signal to control the direction of data flow of the A to B ports (or from B to A
ports).
VCCA
VCCB
R1
One-Shot
T1
One-Shot
T2
R2
Translator
SDIO-DATx(A)
SDIO-DATx(B)
Bias
N1
T3
One-Shot
Translator
T4
One-Shot
Figure 4. Architecture of an SDIO Switch-Type Cell
Each of these bidirectional SDIO channels independently determines the direction of data flow without a
direction-control signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is
how this auto-direction feature is realized.
The following two key circuits are employed to facilitate the "switch-type" voltage translation function:
1. Integrated pullup resistors to provide dc-bias and drive capabilities
2. An N-channel pass-gate transistor topology (with a high RON of approximately 300 Ω) that ties the A-port to
the B-port
3. Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B
ports
For bidirectional voltage translation, pullup resistors are included on the device for dc current sourcing capability.
The VGATE gate bias of the N-channel pass transistor is set at a level that optimizes the switch characteristics for
maximum data rate as well as minimal static supply leakage. Data can flow in either direction without guidance
from a control signal.
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Feature Description (continued)
The edge-rate acceleration circuitry speeds up the output slew rate by monitoring the input edge for transitions,
helping maintain the data rate through the device.
During a low-to-high signal rising-edge, the O.S. circuits turn on the PMOS transistors (T1, T3) and its associated
driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase
to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever
occurs first. This edge-rate acceleration provides high ac drive by bypassing the internal pullup resistors during
the low-to-high transition to speed up the rising-edge signal.
During a high-to-low signal falling-edge, the O.S. circuits turn on the NMOS transistors (T2, T4) and its associated
driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase
to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever
occurs first.
To minimize dynamic ICC and the possibility of signal contention, the user should wait for the O.S. circuit to turnoff before applying a signal in the opposite direction. The worst-case duration is equal to the minimum pulsewidth number provided in the Timing Requirements—VCCA = 1.2 V ± 0.1 V section of this data sheet.
Once the O.S. is triggered and switched off, both the A and B ports must go to the same state (i.e. both High or
both Low) for the one-shot to trigger again. In a DC state, the output drivers maintain a Low state through the
pass transistor. The output drivers maintain a High through the "smart pullup resistors" that dynamically change
value based on whether a Low or a High is being passed through the SDIO lines, as follows:
• R1 and R2 values are a nominal 40 kΩ when the output is driving a low
• R1 and R2 values are a nominal 4 kΩ when the output is driving a high
• R1 and R2 values are a nominal 40 kΩ when the device is disabled via the EN pin or by pulling the either
VCCA or VCCB to 0 V.
• The threshold at which the resistance changes is approximately VCCx/2
The reason for using these "smart" pullup resistors is to allow the TXS0206 to realize a lower static power
consumption (when the I/Os are low), support lower VOL values for the same size pass-gate transistor, and
improved simultaneous switching performance.
8.4 Device Functional Modes
Table 1 lists the functional modes of the TXS0206A.
Table 1. Function Table
18
EN
TRANSLATOR I/Os
L
Disabled, pulled to VCCA, VCCB through 40 kΩ
H
Active
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Systems engineers working with SD and MMC memory cards face a dilemma. These cards operate at a higher
voltage node than the latest multimedia application processors, which have moved to smaller process technology
nodes that support a maximum I/O interface voltage of 1.2 V. The problem is bridging the gap between these two
voltage nodes while maintaining digital switching compatibility. The TXS0206A was designed specifically to
address this. It is an auto direction sensing voltage level shifter that can interface with high speed SD and MMC
cards because it supports a clock frequency of up to 60 MHz and each data channel supports up to 60 Mbps.
9.2 Typical Application
1.8 V
A Side
B Side
2.9 V
CLK
CLK
Feedback CLK
CMD
CMD
Data 0–3
Level-Shifter
CPU
Antenna
Pins 10, 11
Data 0–3
EN
WP, CD
MMC, SD Card,
or MS Card
WP, CD 1.8-V Pullup
WP, CD
Integrated Pullup/Pulldown Resistors
Figure 5. Typical Application Circuit
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 2
Table 2. Design Parameters
PARAMETERS
VALUES
Input voltage
1.1 V to 3.6 V
Output voltage
1.1 V to 3.6 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the microprocessor that is driving the TXS0206A to determine the input voltage
range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low, the
value must be less than the VIL of the input port.
• Output voltage range
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– Use the supply voltage of the memory card that the TXS0206A is driving to determine the output voltage
range.
9.2.2.1 External Pulldown Resistors
When using the TXS0206A device with MMCs, SD, and Memory Stick™ to ensure that a valid receiver input
voltage high (VIH) is achieved, the value of any pulldown resistors (external or internal to a memory card) must
not be smaller than a 10-kΩ value. The impact of adding too heavy (less than 10-kΩ value) a pulldown resistor to
the data and command lines of the TXS0206A device and the resulting 4-kΩ pullup / 10-kΩ pulldown voltage
divider network has a direct impact on the VIH of the signal being sent into the memory card and its associated
logic.
The resulting VIH voltage for the 10-kΩ pulldown resistor value would be:
VCC × 10 kΩ / (10 kΩ+ 4 kΩ) = 0.714 × VCC
This is marginally above a valid input high voltage for a 1.8-V signal (i.e., 0.65 × VCC).
The resulting VIH voltage for 20-kΩ pulldown resistor value would be:
VCC × 20 kΩ / (20 kΩ + 4 kΩ) = 0.833 × VCC
Which is above the valid input high voltage for a 1.8-V signal of 0.65 × VCC.
9.2.3 Application Curves
Figure 6. 1.8 V to 3.3 V Translation at 25 MHz
20
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9.3 System Examples
VCCA
VCCB
C3
0.1 µF
U1A
VCCB
C4
0.1 µF
C1
0.1 µF
J1
U2
A2
VDDA
D1
DAT0
E1
A1
DAT1
DAT2
B1
DAT3
C1
CMD
D2
CLK
E2
CLKin
C2
GND
CD
C3
VCCA
VCCB
DAT0A
DAT1A
DAT2A
DAT3A
CMDA
D4 DAT0B
DAT0B
DAT1B E4 DAT1B
DAT2B A4 DAT2B
DAT3B B4 DAT3B
C4 CMDB
CMDB
D3 CLKB
CLKB
CLKA
CLK-f
DAT2B
DAT3B
CMDB
B3
CLKB
DAT0B
DAT1B
Processor
SD/SDIO MMC
CD
DAT2
DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1
10
CD (Physical)
11
GND
12
GND
CD
GND
GND
0
1
2
3
4
5
6
7
8
B2 CD
54794-0978
Micro SD
TXS0206A
Figure 7. Interfacing With SD/SDIO Card
VCCA
VCCB
C3
0.1 µF
U1A
VCCB
C4
0.1 µF
C1
0.1 µF
J1
U2
VDDA
DAT0
DAT1
DAT2
DAT3
CMD
CLK
CLKin
GND
CD
A2
D1
E1
A1
B1
C1
D2
E2
C2
C3
VCCA
VCCB
DAT0A
DAT1A
DAT2A
DAT3A
CMDA
CLKA
CLK-f
DAT2B
DAT3B
CMDB
B3
D4 DAT0B
DAT0B
DAT1B E4 DAT1B
DAT2B A4 DAT2B
DAT3B B4 DAT3B
C4 CMDB
CMDB
D3 CLKB
CLKB
CLKB
DAT0B
DAT1B
CD
B2 CD
WP
Processor
SD/SDIO MMC
DAT2
DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1
10
CD (Physical)
11
GND
12
GND
14 WP (Physical)
CD
GND
GND
0
1
2
3
4
5
6
7
8
Standard SD Card
TXS0206A
VCCA
Figure 8. Interfacing With Seperate WP and CD Pin
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System Examples (continued)
VCCA
VCCB
C3
0.1 µF
U1A
VCCB
C4
0.1 µF
C1
0.1 µF
U2
VDDA
DAT0
DAT1
DAT2
DAT3
CMD
CLK
CLKin
GND
A2
D1
E1
A1
B1
C1
D2
E2
C2
C3
VCCA
VCCB
DAT0A
CMDB
2
DAT1B
3
E4 DAT1B
DAT1B
A4 DAT2B
DAT2B
B4 DAT3B
DAT3B
DAT0B
4
DAT2B
5
CD
6
C4 CMDB
CMDB
D3 CLKB
CLKB
DAT3B
7
CLKB
8
DAT0B
D4 DAT0B
DAT1A
DAT2A
DAT3A
CMDA
CLKA
CLK-f
1
B3
GND
9
GND
CD
CD
Memory Stick™
Controller
B2 CD
10
TXS0206
VSS
BS
DATA1 (see Note)
DATA0/SDIO (see Note)
DATA2 (see Note)
INS
DATA3 (see Note)
SCLK
VCC
VSS
Memory Stick™
Connector
Figure 9. Interfacing With Memory Stick™ Card
10 Power Supply Recommendations
The TXS0206A does not require power sequencing between VCCA and VCCB during power-up so the powersupply rails can be ramped in any order.
The EN pin is referenced to VCCA and when configured to low, will place all outputs into a high-impedance state.
To ensure the high-impedance state of the outputs during power up or power down, the EN pin must be tied to
GND through a pulldown resistor and must not be enabled until VCCA and VCCB are fully ramped and stable. The
minimum value of the pulldown resistor to ground is determined by the current-sourcing capability of the driver
controlling the EN pin.
Finally, the EN pin may be shorted to VCCA if the application does not require use of the high-impedance state at
any time.
11 Layout
11.1 Layout Guidelines
To
•
•
•
•
22
ensure reliability of the device, TI recommends following common printed-circuit board layout guidelines.
Bypass capacitors should be used on power supplies.
Short trace lengths should be used to avoid excessive loading
PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than
the one shot duration, approximately 30 ns, ensuring that any reflection encounters low impedance at the
source driver
With very heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail,
so it is recommended that this lumped-load capacitance be considered and kept below 50 pF to avoid O.S.
retriggering, bus contention, output signal oscillations, or other adverse system-level affects.
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11.2 Layout Example
Polygonal Copper Pour
VIA to Power Plane (Inner Layer)
1 PF
VIA to GND Plane (Inner Layer)
VIA to Bottom Layer
To Connector
1
2
3
4
To Host
To Memory Card
A
To Host
To Memory Card
B
C
To Host
To Memory Card
D
To Host
E
To Memory Card
To Host
To Memory Card
TXS0206AYFP
(Top View)
To Host
To Host
Figure 10. TXS0206A Example Layout (Top Layer)
To Connector
Polygonal Copper Pour
VIA to Power Plane (Inner Layer)
VIA to GND Plane (Inner Layer)
VIA to Top Layer
1
2
3
4
A
B
C
D
To Host
To Memory Card
E
TXS0206AYFP
(Top View)
Figure 11. TXS0206A Example Layout (Bottom Layer)
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
Introduction to Logic, SLVA700.
TXS0206A Evaluation Module, SCEU008.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TXS0206AYFPR
ACTIVE
DSBGA
YFP
20
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TXS0206A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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