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UCC27212DPRT

UCC27212DPRT

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    WSON10_EP

  • 描述:

    IC GATE DRVR HALF-BRIDGE 10WSON

  • 数据手册
  • 价格&库存
UCC27212DPRT 数据手册
Order Now Product Folder Support & Community Tools & Software Technical Documents UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 UCC27212 120-V Boot, 4-A Peak, High-Frequency Half-Bridge Driver 1 Features 3 Description • • • • • • • • • • The UCC27212 device has a peak output current of 4-A source and 4-A sink, which allows for the ability to drive large power MOSFETs. The device features an on-chip 120-V rated bootstrap diode eliminating the need for external discrete diodes. The input structure can directly handle –10 V, which increases robustness and is also independent of supply voltage. The UCC27212 offers 5 V UVLO which helps lower power losses and increased input hysteresis that allows for interface to analog or digital PWM controllers with enhanced noise immunity. The switching node of the UCC27212 (HS pin) can handle –18-V maximum, which allows the high-side channel to be protected from inherent negative voltages. 1 4-A Sink, 4-A Source Output Currents Maximum Boot Voltage 120-V DC 7-V to 17-V VDD Operating Range 20-V ABS Maximum VDD Operating Range 5-V Turn-off Under Voltage Lockout (UVLO) Input Pins Can Tolerate –10 V to +20 V 7.2-ns Rise and 5.5-ns Fall Time (1000-pF Load) 20-ns Typical Propagation Delay 4-ns Typical Delay Matching Specified from –40°C to +140°C 2 Applications • • • • DC-DC Power Supplies Merchant Telecom Rectifiers Half-Bridge and Full-Bridge Converters Push-Pull and Active-Clamp Forward Converters Typical Application Diagram 12 V Device Information(1) PART NUMBER UCC27212 Propagation Delays vs Supply Voltage T = 25°C 32 100 V CONTROL LI DRIVE HI SECONDARY SIDE CIRCUIT HS LO DRIVE LO UCC27212 ISOLATION AND FEEDBACK Propagation Delay (ns) HB PWM CONTROLLER TDLRR TDLFF TDHRR TDHFF 28 HO BODY SIZE (NOM) 4.0 mm x 4.0 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. VDD HI PACKAGE WSON (10) 24 20 16 12 8 4 0 8 Copyright © 2017, Texas Instruments Incorporated 12 16 Supply Voltage (V) 20 D001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 1 1 1 3 4 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings ............................................................ 5 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 6 Switching Characteristics .......................................... 7 Typical Characteristics ............................................ 10 Detailed Description ............................................ 13 7.1 Overview ................................................................. 13 7.2 Functional Block Diagram ....................................... 14 7.3 Feature Description................................................. 14 2 7.4 Device Functional Modes........................................ 15 8 Application and Implementation ........................ 16 8.1 Application Information............................................ 16 8.2 Typical Application ................................................. 16 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 10.2 Layout Example .................................................... 22 11 Device and Documentation Support ................. 23 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 23 23 12 Mechanical, Packaging, and Orderable Information ........................................................... 23 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 UCC27212 www.ti.com SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (June 2017) to Revision A Page • Changed " 5-V to 17-V VDD Operating Range, (20-V ABS Maximum)" to "7-V to 17-V VDD Operating Range, (20-V ABS Maximum)" ..................................................................................................................................................................... 1 • Changed extended output pulse from 325-ns MAX to 325-ns TYP. ..................................................................................... 8 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 3 UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 www.ti.com 5 Pin Configuration and Functions DPR Package SON-10 Top View VDD 1 HB 2 10 3RZHU3$' Œ LO 9 VSS 8 LI HO 3 HS 4 7 HI N/C 5 6 N/C Not to scale Pin Functions PIN (1) (2) (3) 4 I/O DESCRIPTION NO. NAME 2 HB P High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022 µF to 0.1 µF. 7 HI I High-side input. (1) 3 HO O High-side output. Connect to the gate of the high-side power MOSFET. 4 HS P High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of bootstrap capacitor to this pin. 8 LI I Low-side input. (1) 10 LO O Low-side output. Connect to the gate of the low-side power MOSFET. 5 N/C — No internal connection. 6 N/C — No internal connection. Pad PowerPAD ™ (2) G Used on the DDA, DRM and DPR packages only. Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance. 1 VDD P Positive supply to the lower-gate driver. Decouple this pin to VSS (GND). Typical decoupling capacitor range is 0.22 µF to 4.7 µF. (3) 9 VSS G Negative supply terminal for the device which is generally grounded. For cold temperature applications TI recommends the upper capacitance range. Follow the Layout Guidelines for PCB layout. The thermal pad is not directly connected to any leads of the package; however, it is electrically and thermally connected to the substrate which is the ground of the device. HI or LI input is assumed to connect to a low impedance source signal. The source output impedance is assumed less than 100 Ω. If the source impedance is greater than 100 Ω, add a bypassing capacitor, each, between HI and VSS and between LI and VSS. The added capacitor value depends on the noise levels presented on the pins, typically from 1 nF to 10 nF should be effective to eliminate the possible noise effect. When noise is present on two pins, HI or LI, the effect is to cause HO and LO malfunctions to have wrong logic outputs. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 UCC27212 www.ti.com SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VDD (2), VHB – VHS Supply voltage range VLI, VHI Input voltages on LI and HI Output voltage on LO VHO Output voltage on HO VHS Voltage on HS VHB TJ 20 V V –2 VDD + 0.3 V VHS – 0.3 VHB + 0.3 V VHS – 2 VHB + 0.3 V Repetitive pulse < 100 ns (3) –1 100 V –(24 V – VDD) 115 V Voltage on HB –0.3 120 V Operating virtual junction temperature range –40 150 °C –65 150 °C Repetitive pulse < 100 ns (3) Storage temperature, Tstg (2) (3) V VDD + 0.3 DC (1) UNIT 20 –10 Repetitive pulse < 100 ns (3) DC MAX –0.3 DC VLO MIN –0.3 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to VSS unless otherwise noted. Currents are positive into and negative out of the specified terminal. Verified at bench characterization. VDD is the value used in an application design. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) Charged-device model (CDM), per JEDEC specification JESD22C101 (2) UNIT ±2000 ±1500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 5 UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range, all voltages are with respect to VSS; currents are positive into and negative out of the specified terminal. –40°C < TJ = TA < 140°C (unless otherwise noted) VDD Supply voltage range, VHB – VHS VHS Voltage on HS VHS Voltage on HS (repetitive pulse < 100 ns) VHB Voltage on HB MIN NOM MAX 7 12 17 UNIT V –1 100 V –(20 V – VDD) 110 V VHS + 8 115 V 50 V/ns 140 °C Voltage slew rate on HS Operating junction temperature –40 6.4 Thermal Information UCC27212 THERMAL METRIC (1) DPR (SON) UNIT 10 PINS RθJA Junction-to-ambient thermal resistance 36.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 36.0 °C/W RθJB Junction-to-board thermal resistance 14.0 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 14.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics over operating free-air temperature range, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = –40°C to +140°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.05 0.085 0.17 mA 2.1 2.5 6.5 mA 0.015 0.065 0.1 mA 1.5 2.5 5.1 mA SUPPLY CURRENTS, VDD = VHB = 12 V IDD VDD quiescent current V(LI) = V(HI) = 0 V IDDO VDD operating current f = 500 kHz, CLOAD = 0 IHB Boot voltage quiescent current V(LI) = V(HI) = 0 V IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 IHBS HB to VSS quiescent current V(HS) = V(HB) = 115 V IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 0.0005 1 µA 0.07 1.2 mA 0.02 0.065 0.14 mA 2.1 2.5 6.5 mA 0.01 0.04 0.08 mA mA SUPPLY CURRENTS, VDD = VHB = 6.8 V IDD VDD quiescent current V(LI) = V(HI) = 0 V IDDO VDD operating current f = 500 kHz, CLOAD = 0 IHB Boot voltage quiescent current V(LI) = V(HI) = 0 V IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 IHBS HB to VSS quiescent current V(HS) = V(HB) = 115 V IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 1.5 2.5 5.1 0.0005 1 µA 0.07 1.2 mA V INPUT, VDD = VHB = 12 V VHIT Input voltage threshold 1.7 2.3 2.55 VLIT Input voltage threshold 1.2 1.6 1.9 VIHYS Input voltage hysteresis RIN Input pulldown resistance V 700 mV 68 kΩ INPUT, VDD = VHB = 6.8 V VHIT Input voltage threshold 1.6 2.0 2.6 V VLIT Input voltage threshold 1.1 1.5 2.1 V 6 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 UCC27212 www.ti.com SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 Electrical Characteristics (continued) over operating free-air temperature range, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = –40°C to +140°C, (unless otherwise noted) PARAMETER TEST CONDITIONS VIHYS Input voltage hysteresis RIN Input pulldown resistance MIN TYP MAX UNIT 500 mV 68 kΩ UNDER-VOLTAGE LOCKOUT (UVLO), VDD = VHB = 12 V VDDR VDD turnon threshold VDDHYS Hysteresis VHBR VHB turnon threshold VHBHYS Hysteresis 4.9 5.7 6.4 V 0.4 4.35 5.3 V 6.3 V 0.3 V BOOTSTRAP DIODE, VDD = VHB = 12 V VF Low-current forward voltage IVDD-HB = 100 µA 0.65 0.8 VFI High-current forward voltage IVDD-HB = 100 mA 0.85 0.95 V RD Dynamic resistance, ΔVF/ΔI IVDD-HB = 100 mA and 80 mA 0.5 0.85 Ω 0.3 V BOOTSTRAP DIODE, VDD = VHB = 6.8 V VF Low-current forward voltage IVDD-HB = 100 µA 0.65 0.8 V VFI High-current forward voltage IVDD-HB = 100 mA 0.85 0.95 V RD Dynamic resistance, ΔVF/ΔI IVDD-HB = 100 mA and 80 mA 0.5 0.85 Ω 0.3 LO GATE DRIVER, VDD = VHB = 12 V VLOL Low-level output voltage 0.05 0.1 0.19 V VLOH High level output voltage 0.1 0.16 0.29 V Peak pullup current (1) Peak pulldown current (1) 3.7 A 4.5 A LO GATE DRIVER, VDD = VHB = 6.8 V VLOL Low-level output voltage ILO = 100 mA 0.04 0.13 0.35 V VLOH High level output voltage ILO = –100 mA, VLOH = VDD – VLO 0.12 0.23 0.42 V Peak pullup current VLO = 0 V 1.3 A Peak pulldown current VLO = 12 V for VDD = 6.8V 1.7 A HO GATE DRIVER, VDD = VHB = 12 V VHOL Low-level output voltage 0.05 0.1 0.19 V VHOH High-level output voltage 0.1 0.16 0.29 V Peak pullup current (1) Peak pulldown current (1) 3.7 A 4.5 A HO GATE DRIVER, VDD = VHB = 6.8 V VLOL Low-level output voltage IHO = 100 mA 0.04 0.13 0.35 V VLOH High level output voltage IHO = –100 mA, VHOH = VHB – VHO 0.12 0.23 0.42 V Peak pullup current VHO = 0 V 1.3 A Peak pulldown current VHO = 12 V for VDD = 6.8V 1.7 A (1) Ensured by design. 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PROPAGATION DELAYS, VDD = VHB = 12 V TDLFF VLI falling to VLO falling CLOAD = 0 10 16 30 ns TDHFF VHI falling to VHO falling CLOAD = 0 10 16 30 ns TDLRR VLI rising to VLO rising CLOAD = 0 10 20 42 ns TDHRR VHI rising to VHO rising CLOAD = 0 10 20 42 ns Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 7 UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 www.ti.com Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PROPAGATION DELAYS, VDD = VHB = 6.8 V TDLFF VLI falling to VLO falling CLOAD = 0 10 24 50 ns TDHFF VHI falling to VHO falling CLOAD = 0 10 24 50 ns TDLRR VLI rising to VLO rising CLOAD = 0 13 28 57 ns TDHRR VHI rising to VHO rising CLOAD = 0 13 28 57 ns TJ = 25°C 4 9.5 ns TJ = –40°C to +140°C 4 17 ns TJ = 25°C 4 9.5 ns TJ = –40°C to +140°C 4 17 ns TJ = 25°C 8 TJ = –40°C to +140°C 8 TJ = 25°C 6 TJ = –40°C to +140°C 6 DELAY MATCHING, VDD = VHB = 12 V TMON TMOFF From HO OFF to LO ON From LO OFF to HO ON DELAY MATCHING, VDD = VHB = 6.8 V TMON From HO OFF to LO ON TMOFF From LO OFF to HO ON ns 18 ns ns 18 ns OUTPUT RISE AND FALL TIME, VDD = VHB = 12 V tR LO rise time CLOAD = 1000 pF, from 10% to 90% 7.8 ns tR HO rise time CLOAD = 1000 pF, from 10% to 90% 7.8 ns tF LO fall time CLOAD = 1000 pF, from 90% to 10% 6.0 ns tF HO fall time CLOAD = 1000 pF, from 90% to 10% 6.0 ns tR LO, HO CLOAD = 0.1 µF, (3 V to 9 V) 0.36 0.6 µs tF LO, HO CLOAD = 0.1 µF, (9 V to 3 V) 0.20 0.4 µs OUTPUT RISE AND FALL TIME, VDD = VHB = 6.8 V tR LO rise time CLOAD = 1000 pF, from 10% to 90% 9.5 ns tR HO rise time CLOAD = 1000 pF, from 10% to 90% 13.0 ns tF LO fall time CLOAD = 1000 pF, from 90% to 10% 9.5 ns tF HO fall time CLOAD = 1000 pF, from 90% to 10% 13.0 ns tR LO, HO CLOAD = 0.1 µF, (30% to 70%) 0.45 0.7 µs tF LO, HO CLOAD = 0.1 µF, (70% to 30%) 0.2 0.5 µs 100 ns MISCELLANEOUS Minimum input pulse width that changes the output Bootstrap diode turnoff time (1) (2) Extended output pulse (1) (2) (3) 8 IF = 20 mA, IREV = 0.5 A (3) when VDD = VHB = 6.8 V, VHS = 100 V, and input pulse width is 100 ns 20 ns 325 ns Ensured by design. IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode. Typical values for TA = 25°C. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 UCC27212 www.ti.com SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 LI Input (HI, LI) HI TDLRR, TDHRR LO Output (HO, LO) TDLFF, TDHFF HO Figure 1. Timing Diagram Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 9 UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 www.ti.com 6.7 Typical Characteristics 100 IDD Operating Current (mA) Quiescent Current (µA) 100 80 60 40 20 10 1 CL = 0 pF, T = −40°C CL = 0 pF, T = 25°C CL = 0 pF, T = 140°C CL = 1000 pF, T = 25°C CL = 1000 pF, T = 140°C CL = 4700 pF, T = 140°C 0.1 IDD IHB 0 0 2 4 6 8 10 12 14 Supply Voltage (V) 16 18 0.01 20 T = 25°C 10 Figure 2. Quiescent Current vs Supply Voltage Figure 3. IDD Operating Current vs Frequency Boot Operating Current (mA) IDD Operating Current (mA) 10 1 CL = 0 pF, T = −40°C CL = 0 pF, T = 25°C CL = 0 pF, T = 140°C CL = 1000 pF, T = 25°C CL = 1000 pF, T = 140°C CL = 4700 pF, T = 140°C 0.1 10 100 Frequency (kHz) 10 1 0.1 0.01 1000 CL = 0 pF, T = −40°C CL = 0 pF, T = 25°C CL = 0 pF, T = 140°C CL = 1000 pF, T = 25°C CL = 1000 pF, T = 140°C CL = 4700 pF, T = 140°C 10 5 5 Input Threshold Voltage (V) 6 4 3 2 1 0 Rising Falling 8 1000 Figure 5. Boot Voltage Operating Current vs Frequency (HB To HS) 6 −1 100 Frequency (kHz) VHB – VHS = 12 V Figure 4. IDD Operating Current vs Frequency Input Threshold Voltage (V) G002 100 VDD = 12 V 12 16 Supply Voltage (V) 20 4 3 2 1 0 Rising Falling −1 −40 −20 0 20 40 60 80 Temperature (°C) 100 120 140 VDD = 12 V T = 25°C Figure 6. Input Threshold vs Supply Voltage 10 1000 VDD = 12 V 100 0.01 100 Frequency (kHz) Figure 7. Input Thresholds vs Temperature Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 UCC27212 www.ti.com SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 Typical Characteristics (continued) 0.2 VOL − LO/HO Output Voltage (V) V OH – LO/HO Output Voltage (V) 0.32 0.28 0.24 0.2 0.16 0.12 VDD = VHB = 8 V VDD = VHB = 12 V VDD = VHB = 16 V VDD = VHB = 20 V 0.08 0.04 0 −40 −20 0 20 40 60 80 Temperature (°C) 100 120 0.12 0.08 VDD = VHB = 8 V VDD = VHB = 12 V VDD = VHB = 16 V VDD = VHB = 20 V 0.04 0 −40 140 IHO = ILO = 100 mA 0.16 −20 0 20 40 60 80 Temperature (°C) 100 120 140 IHO = ILO = 100 mA Figure 8. LO and HO High-Level Output Voltage vs Temperature Figure 9. LO and HO Low-Level Output Voltage vs Temperature 8 1.5 7.6 1.2 Hysteresis (V) Threshold (V) 7.2 6.8 6.4 0.9 0.6 6 0.3 5.6 VDD Rising Threshold HB Rising Threshold 5.2 −40 −20 0 20 40 60 80 Temperature (°C) 100 120 VDD UVLO Hysteresis HB UVLO Hysteresis 0 −40 140 −20 0 G009 Figure 10. Undervoltage Lockout Threshold vs Temperature 20 40 60 80 Temperature (°C) 100 120 140 G010 Figure 11. Undervoltage Lockout Threshold Hysteresis vs Temperature 32 40 32 28 24 20 16 12 TDLRR TDLFF TDHRR TDHFF 8 4 0 −40 −20 0 20 40 60 80 Temperature (°C) 100 120 140 VDD = VHB = 12 V Propagation Delay (ns) Propagation Delay (ns) 36 24 16 TDLRR TDLFF TDHRR TDHFF 8 0 −40 −20 0 20 40 60 80 Temperature (°C) 100 120 140 VDD = VHB = 12 V Figure 12. Propagation Delays vs Temperature Figure 13. Propagation Delays vs Temperature Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 11 UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 www.ti.com 32 32 28 28 24 20 16 12 TDLRR TDLFF TDHRR TDHFF 8 4 0 8 12 16 Supply Voltage (V) Propagation Delay (ns) Propagation Delay (ns) Typical Characteristics (continued) 24 20 16 12 TDLRR TDLFF TDHRR TDHFF 8 4 0 20 8 T = 25°C Figure 15. Propagation Delays vs Supply Voltage (VDD = VHB) 10 5 Pulldown Current Pullup Current 8 4 Output Current (A) Delay Matching (ns) 20 T = 25°C Figure 14. Propagation Delays vs Supply Voltage (VDD = VHB) 6 4 2 0 −2 −40 12 16 Supply Voltage (V) 3 2 1 TMON TMOFF −20 0 20 40 60 80 Temperature (°C) 100 120 140 VDD = VHB = 12 V 0 0 2 4 6 8 Output Voltage (V) 10 12 G016 VDD = VHB = 12 V Figure 16. Delay Matching vs Temperature Figure 17. Output Current vs Output Voltage 100 Diode Current (mA) 10 1 0.1 0.01 0.001 500 550 600 650 700 750 Diode Voltage (mV) 800 850 G017 Figure 18. Diode Current vs Diode Voltage 12 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 UCC27212 www.ti.com SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 7 Detailed Description 7.1 Overview The UCC27212 device represents Texas Instruments’ latest generation of high-voltage gate drivers, which are designed to drive both the high-side and low-side of N-Channel MOSFETs in a half- and full-bridge or synchronous-buck configuration. The floating high-side driver can operate with supply voltages of up to 120 V, which allows for N-Channel MOSFET control in half-bridge, full-bridge, push-pull, two-switch forward, and active clamp forward converters. The UCC27212 device feature 4-A source and sink capability, industry best-in-class switching characteristics and a host of other features listed in Table 1. These features combine to ensure efficient, robust and reliable operation in high-frequency switching power circuits. Table 1. UCC27212 Highlights FEATURE BENEFIT 4-A source and sink current with 0.9-Ω output resistance High peak current ideal for driving large power MOSFETs with minimal power loss (fast-drive capability at Miller plateau) Input pins (HI and LI) can directly handle –10 VDC up to 20 VDC Increased robustness and ability to handle undershoot and overshoot can interface directly to gate-drive transformers without having to use rectification diodes. 120-V internal boot diode Provides voltage margin to meet telecom 100-V surge requirements Switch node (HS pin) able to handle –18 V maximum for 100 ns Allows the high-side channel to have extra protection from inherent negative voltages caused by parasitic inductance and stray capacitance Robust ESD circuitry to handle voltage spikes Excellent immunity to large dV/dT conditions 18-ns propagation delay with 7.2-ns rise time and 5.5-ns fall time Best-in-class switching characteristics and extremely low-pulse transmission distortion 2-ns (typical) delay matching between channels Avoids transformer volt-second offset in bridge Symmetrical UVLO circuit Ensures high-side and low-side shut down at the same time TTL optimized thresholds with increased hysteresis Complementary to analog or digital PWM controllers; increased hysteresis offers added noise immunity In the UCC27212 device, the high side and low side each have independent inputs that allow maximum flexibility of input control signals in the application. The boot diode for the high-side driver bias supply is internal to the UCC27212. The UCC27212 is the TTL or logic compatible version. The high-side driver is referenced to the switch node (HS), which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to VSS, which is typically ground. The UCC27212 functions are divided into the input stages, UVLO protection, level shift, boot diode, and output driver stages. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 13 UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 www.ti.com 7.2 Functional Block Diagram 2 HB 3 HO 4 HS 8 LO 7 VSS UVLO LEVEL SHIFT HI VDD 5 1 UVLO LI 6 Copyright © 2017, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Input Stages The input stages provide the interface to the PWM output signals. The input stages of the UCC27212 device have impedance of 70-kΩ nominal and input capacitance is approximately 2 pF. Pulldown resistance to VSS (ground) is 70 kΩ. The logic level compatible input provides a rising threshold of 2.3 V and a falling threshold of 1.6 V. There is enough input hysteresis to avoid noise related jitter issues on the input. 7.3.2 Undervoltage Lockout (UVLO) The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified threshold. The rising VDD threshold is 5.7 V with 0.4-V hysteresis. The VHB UVLO disables only the high-side driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold is 5.3 V with 0.4 V hysteresis. 14 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 UCC27212 www.ti.com SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 Feature Description (continued) 7.3.3 Level Shift The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver. 7.3.4 Boot Diode The boot diode necessary to generate the high-side bias is included in the UCC27212 family of drivers. The diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable operation. 7.3.5 Output Stages The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The lowside output stage is referenced from VDD to VSS and the high side is referenced from VHB to VHS. 7.4 Device Functional Modes The device operates in normal mode and UVLO mode. See the Undervoltage Lockout (UVLO) section for information on UVLO operation mode. In the normal mode the output state is dependent on states of the HI and LI pins. Table 2 lists the output states for different input pin combinations. Table 2. Device Logic Table LI PIN HO (1) L L L L L H L H H L H L H H H H HI PIN (1) (2) LO (2) HO is measured with respect to HS. LO is measured with respect to VSS. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 15 UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information To affect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching devices. With the advent of digital power, this situation will be often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers, and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the controller into the driver. Finally, emerging wide band-gap power device technologies such as GaN based switches, which are capable of supporting very high switching frequency operation, are driving very special requirements in terms of gate drive capability. These requirements include operation at low VDD voltages (5 V or lower), low propagation delays and availability in compact, low-inductance packages with good thermal capability. Gate-driver devices are extremely important components in switching power, and they combine the benefits of high-performance, low-cost component count and board-space reduction as well as simplified system design. 8.2 Typical Application 12 V 100 V VDD HB HI LI CONTROL PWM CONTROLLER DRIVE HI SECONDARY SIDE CIRCUIT HO HS LO DRIVE LO UCC27212-Q1 ISOLATION AND FEEDBACK Copyright © 2017, Texas Instruments Incorporated Figure 19. UCC27212 Typical Application 16 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 UCC27212 www.ti.com SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 Typical Application (continued) 8.2.1 Design Requirements For this design example, use the parameters listed in Table 3. Table 3. Design Specifications DESIGN PARAMETER EXAMPLE VALUE Supply voltage, VDD 12 V Voltage on HS, VHS 0 V to 100 V Voltage on HB, VHB 12 V to 112 V Output current rating, IO –4 A to 4 A Operating frequency 500 kHz Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 17 UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 www.ti.com 8.2.2 Detailed Design Procedure 8.2.2.1 Power Dissipation Power dissipation of the gate driver has two portions as shown in Equation 1. PDISS = PDC + PSW (1) Use Equation 2 to calculate the DC portion of the power dissipation (PDC). PDC = IQ × VDD where • IQ is the quiescent current for the driver. (2) The quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through, and so forth). The UCC27212 features very low quiescent currents (less than 0.17 mA, refer to the table and contain internal logic to eliminate any shoot-through in the output driver stage. Thus the effect of the PDC on the total power dissipation within the gate driver can be safely assumed to be negligible. The power dissipated in the gate-driver package during switching (PSW) depends on the following factors: • Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to input bias supply voltage VDD) • Switching frequency • Use of external gate resistors. When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 3. EG = ½CLOAD × VDD2 where • • CLOAD is load capacitor VDD is bias voltage feeding the driver (3) There is an equal amount of energy dissipated when the capacitor is charged and when it is discharged. This leads to a total power loss given by Equation 4. PG = CLOAD × VDD2 × fSW where • fSW is the switching frequency (4) The switching load presented by a power MOSFET/IGBT is converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when switching a capacitor which is calculated using the equation QG = CLOAD × VDD to provide Equation 5 for power. PG = CLOAD × VDD2 × fSW = QG × VDD × fSW (5) This power PG is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on and off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor. 18 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 UCC27212 www.ti.com SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 8.2.3 Application Curves Figure 20. Negative 10-V Input Figure 21. Step Input Figure 22. Symmetrical UVLO Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 19 UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 www.ti.com 9 Power Supply Recommendations The bias supply voltage range for which the UCC27212 device is recommended to operate is from 7 V to 17 V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the V(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating). Keeping a 3-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin is 17 V. The UVLO protection feature also involves a hysteresis function, which means that when the VDD pin bias voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD(hys). Therefore, ensuring that, while operating at or near the 7 V range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below the V(OFF) threshold, which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system start-up the device does not begin operation until the VDD pin voltage has exceeded the V(ON) threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin. Although this fact is well known, it is important to recognize that the charge for source current pulses delivered by the HO pin is also supplied through the same VDD pin. As a result, every time a current is sourced out of the HO pin, a corresponding current pulse is delivered into the device through the VDD pin. Thus, ensure that a local bypass capacitor is provided between the VDD and GND pins and located as close to the device as possible for the purpose of decoupling is important. A low-ESR, ceramic surface-mount capacitor is required. TI recommends using a capacitor in the range 0.22 µF to 4.7 µF between VDD and GND. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore a 0.022-µF to 0.1-µF local decoupling capacitor is recommended between the HB and HS pins. 20 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 UCC27212 www.ti.com SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 10 Layout 10.1 Layout Guidelines To • • • • • • • • • improve the switching characteristics and efficiency of a design, the following layout rules must be followed. Locate the driver as close as possible to the MOSFETs. Locate the VDD – VSS and VHB-VHS (bootstrap) capacitors as close as possible to the device (see ). Pay close attention to the GND trace. Use the thermal pad of the package as GND by connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the MOSFET, but must not be in the high current path of the MOSFET drain or source current. Use similar rules for the HS node as for GND for the high-side driver. For systems using multiple UCC27212 devices, TI recommends that dedicated decoupling capacitors be located at VDD–VSS for each device. Care must be taken to avoid placing VDD traces close to LO, HS, and HO signals. Use wide traces for LO and HO closely following the associated GND or HS traces. A width of 60 to 100 mils is preferable where possible. Use as least two or more vias if the driver outputs or SW node must be routed from one layer to another. For GND, the number of vias must be a consideration of the thermal pad requirements as well as parasitic inductance. Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high impedance leads. A poor layout can cause a significant drop in efficiency or system malfunction, and it can even lead to decreased reliability of the whole system. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 21 UCC27212 SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 www.ti.com 10.2 Layout Example HB Bypassing Cap (Bottom Layer) Ground plane (Bottom Layer) VDD Bypassing Cap To LO Load Ext. Gate Resistance (LO) Ext. Gate Resistance (HO) To HO Load Figure 23. UCC27212 Layout Example 10.2.1 Thermal Considerations The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal characteristics of the package. For a gate driver to be useful over a particular temperature range, the package must allow for efficient removal of the heat produced while keeping the junction temperature within rated limits. The thermal metrics for the driver package are listed in . For detailed information regarding the table, refer to the Application Note from Texas Instruments entitled Semiconductor and IC Package Thermal Metrics (SPRA953). The UCC27212 device is offered in SOIC (8) and VSON (8). The section lists the thermal performance metrics related to the SOT-23 package. 22 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 UCC27212 www.ti.com SLUSCO1A – JUNE 2017 – REVISED APRIL 2018 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • PowerPAD™ Thermally Enhanced Package, Application Report • PowerPAD™ Made Easy, Application Report 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: UCC27212 23 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCC27212DPRR ACTIVE WSON DPR 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 UCC 27212 UCC27212DPRT ACTIVE WSON DPR 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 UCC 27212 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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