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UCC2800-Q1, UCC2801-Q1, UCC2802-Q1
UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
UCC280x-Q1 Low-Power BiCMOS Current-Mode
PWM Controllers
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to 125°C
TA
– Device HBM classification level 2: ±2 kV
– Device CDM classification level C5: >1000 V
100-μA typical starting supply current
500-μA typical operating supply current
Operation up to 1 MHz
Internal soft start
Internal fault soft start
Internal leading-edge blanking of the current
sense signal
1-A totem-pole output
70-ns typical response from current-sense to gate
drive output
1.5% tolerance voltage reference
Same pinout as UC3842 and UC3842A
Switch mode power supplies (SMPS)
DC-to-DC converters
Power modules
Automotive PSU
Battery-operated PSU
3 Description
The UCC280x-Q1 family of high-speed, low-power
integrated circuits contain all of the control and drive
components required for off-line and DC-to-DC fixed
frequency current-mode switching mode power
supplies with minimal parts count.
These devices have the same pin configuration as
the UCx84x family, and also offer the added features
of internal full-cycle soft start and internal leadingedge blanking of the current-sense input.
Device Information(1)
PART NUMBER
UCC2800-Q1,
UCC2801-Q1,
UCC2802-Q1,
UCC2803-Q1,
UCC2804-Q1,
UCC2805-Q1
PACKAGE
SOIC (8)
BODY SIZE (NOM)
3.91 mm × 4.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
Vin
Vout
UCC2803
7 VCC
OUT 6
8 REF
CS 3
FB 2
Cin
Cout
4 RC
GND
5
COMP
1
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC2800-Q1, UCC2801-Q1, UCC2802-Q1
UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
6
8.1
8.2
8.3
8.4
8.5
8.6
6
6
6
7
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 11
9.3 Feature Description................................................. 11
9.4 Device Functional Modes ....................................... 24
10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Application ............................................... 26
11 Power Supply Recommendations ..................... 35
12 Layout................................................................... 35
12.1 Layout Guidelines ................................................ 35
12.2 Layout Example .................................................... 37
13 Device and Documentation Support ................. 38
13.1
13.2
13.3
13.4
13.5
Community Resources..........................................
Trademarks ...........................................................
Related Links ........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
14 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2008) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added More details in Absolute max section ........................................................................................................................ 6
•
Changed Power Supply Recommendation section ............................................................................................................. 35
2
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UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
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SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
5 Description (continued)
The UCC280x-Q1 family offers a variety of package options, temperature range options, choice of maximum duty
cycle, and choice of critical voltage levels. Lower reference parts such as the UCC2803-Q1 and UCC2805-Q1 fit
best into battery-operated systems, while the higher reference and higher UVLO hysteresis of the UCC2802-Q1
and UCC2804-Q1 make these ideal choices for use in off-line power supplies.
The UCC280x-Q1 series is specified for operation from –40°C to 125°C.
6 Device Comparison Table
Device Comparison Table
PART NUMBER
MAXIMUM DUTY CYCLE
REFERENCE VOLTAGE
TURNON THRESHOLD
TURNOFF THRESHOLD
UCC2800-Q1
100%
5V
7.2 V
6.9 V
UCC2801-Q1
50%
5V
9.4 V
7.4 V
UCC2802-Q1
100%
5V
12.5 V
8.3 V
UCC2803-Q1
100%
4V
4.1 V
3.6 V
UCC2804-Q1
50%
5V
12.5 V
8.3 V
UCC2805-Q1
50%
4V
4.1 V
3.6 V
Temperature and Package Selection Table
UCC280x-Q1
Copyright © 2002–2020, Texas Instruments Incorporated
TEMPERATURE RANGE
AVAILABLE PACKAGES
–40°C to 125°C
D
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3
UCC2800-Q1, UCC2801-Q1, UCC2802-Q1
UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
www.ti.com
7 Pin Configuration and Functions
UCC280x-Q1 D Package
8-Pin SOIC
Top View
COMP
1
8
REF
FB
2
7
VCC
CS
3
6
OUT
RC
4
5
GND
Pin Functions
PIN
NAME
SOIC
I/O
DESCRIPTION
COMP is the output of the error amplifier and the input of the PWM comparator.
COMP
1
O
The error amplifier in the UCC280x-Q1 family is a true, low output impedance, 2MHz operational amplifier. As such, the COMP terminal can both source and sink
current. However, the error amplifier is internally current-limited, so the user can
command zero duty cycle by externally forcing COMP to GND.
The UCC280x-Q1 family features built-in full-cycle soft start. Soft start is
implemented as a clamp on the maximum COMP voltage.
CS is the input to the current sense comparators. The UCC280x-Q1 family has
two different current sense comparators: the PWM comparator and an overcurrent
comparator.
CS
3
I
The UCC280x-Q1 family contains digital current sense filtering, which disconnects
the CS terminal from the current sense comparator during the 100-ns interval
immediately following the rising edge of the OUT pin. This digital filtering, also
called leading-edge blanking, means that in most applications, no analog filtering
(RC filter) is required on CS. Compared to an external RC filter technique, the
leading-edge blanking provides a smaller effective CS to OUT propagation delay.
Note, however, that the minimum non-zero On-time of the OUT signal is directly
affected by the leading-edge-blanking and the CS to OUT propagation delay.
The overcurrent comparator is only intended for fault sensing, and exceeding the
overcurrent threshold causes a soft-start cycle.
FB is the inverting input of the error amplifier. For best stability, keep FB lead
length as short as possible and FB stray capacitance as small as possible.
FB
2
I
GND
5
—
GND is reference ground and power ground for all functions on this part.
NC
—
—
No connection pins
OUT is the output of a high-current power driver capable of driving the gate of a
power MOSFET with peak currents exceeding ±750 mA. OUT is actively held low
when VCC is below the UVLO threshold.
OUT
6
O
The high-current power driver consists of FET output devices, which can switch all
of the way to GND and all of the way to VCC. The output stage also provides a
very low impedance to overshoot and undershoot. This means that in many cases,
external schottky clamp diodes are not required.
PWR GND
—
—
Power ground of the IC
4
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UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
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SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
Pin Functions (continued)
PIN
NAME
SOIC
I/O
DESCRIPTION
RC is the oscillator timing pin. For fixed frequency operation, set timing capacitor
charging current by connecting a resistor from REF to RC. Set frequency by
connecting a timing capacitor from RC to GND. For best performance, keep the
timing capacitor lead to GND as short and direct as possible. If possible, use
separate ground traces for the timing capacitor and all other functions.
The frequency of oscillation can be estimated with the following equations:
1.5
R´C
1.0
f =
R´C
f =
RC
4
I
(1)
where
•
•
•
frequency is in Hz
resistance is in Ω
capacitance is in farads
(2)
The recommended range of timing resistors is between 10 k and 200 k, and timing
capacitor is 100 pF to 1000 pF. Never use a timing resistor less than 10 k.
REF is the voltage reference for the error amplifier, and also for many other
functions on the IC. REF is also used as the logic power supply for high-speed
switching logic on the IC.
REF
8
O
When VCC is greater than 1 V and less than the UVLO threshold, REF is pulled to
ground through a 5-kΩ resistor. This means that REF can be used as a logic
output indicating power system status. It is important for reference stability that
REF is bypassed to GND with a ceramic capacitor as close to the pin as possible.
An electrolytic capacitor may also be used in addition to the ceramic capacitor. A
minimum of 0.1-μF ceramic is required. Additional REF bypassing is required for
external loads greater than 2.5 mA on the reference.
To prevent noise problems with high speed switching transients, bypass REF to
ground with a ceramic capacitor very close to the IC package.
VCC
7
I
VCC is the power input connection for this device. In normal operation, VCC is
powered through a current limiting resistor. Although quiescent VCC current is
very low, total supply current is higher depending on OUT current. Total VCC
current is the sum of quiescent VCC current and the average OUT current.
Knowing the operating frequency and the MOSFET gate charge (Qg), average
OUT current can be calculated from:
IOUT = Qg ´ f
(3)
To prevent noise problems, bypass VCC to GND with a ceramic capacitor as
close to the VCC pin as possible. An electrolytic capacitor may also be used in
addition to the ceramic capacitor. There must be a minimum of 1 µF in parallel
with a 0.1-µF ceramic capacitor from VCC to ground placed close to the device.
Copyright © 2002–2020, Texas Instruments Incorporated
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5
UCC2800-Q1, UCC2801-Q1, UCC2802-Q1
UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
www.ti.com
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MAX
UNIT
VCC voltage (3)
MIN
12
V
(3)
30
mA
VCC current
OUT current
±1
A
OUT energy (capacitive load)
20
µJ
6.3 or VCC + 0.3 (4)
V
Analog inputs (FB, CS, RC, COMP)
–0.3
N or J package
Power dissipation at TA < 25°C
1
D package
0.65
L package
1.375
Lead temperature, soldering (10 s)
W
300
°C
Storage Temperature, Tstg
–65
150
°C
Junction Temperature, TJ
-55
150
°C
(1)
(2)
(3)
(4)
All voltages are with respect to GND. All currents are positive into the specified terminal.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
In normal operation Vcc is powered through a current limit resistor. The resistor must be sized so that the VCC voltage under all
operating conditions is below 12 V but above the turnoff threshold. Absolute maximum of 12 V applies when VCC is driven from a low
impedance source such that ICC does not exceed 30mA. Failure to limit VCC and ICC to these limits may result in permanent damage
of the device. This is further discussed in the Power Supply Recommendations.
Return the minimum (lesser) value of the two.
8.2 ESD Ratings
VALUE
UNIT
D PACKAGES
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
Charged-device model (CDM), per AEC Q100-011
±2500
(1)
V
±1500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specifications.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VVCC
VCC bias supply voltage from low impedance source
VFB, VCS,
VRC, VCOMP
Voltage on analog pins
VOUT
Gate driver output voltage
IVCC
Supply bias current
25
mA
IOUT
Average OUT pin current
20
mA
IREF
REF pin output current
5
mA
fOSC
Oscillator frequency
1
MHz
TA
Operating free-air temperature
–55
125
°C
TJ
Junction Temperature
-55
125
°C
6
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11
V
–0.1
6 or VVCC
V
–0.1
VVCC
V
Copyright © 2002–2020, Texas Instruments Incorporated
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UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
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SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
8.4 Thermal Information
UCC280x-Q1
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
107.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.3
°C/W
RθJB
Junction-to-board thermal resistance
48.7
°C/W
ψJT
Junction-to-top characterization parameter
6.6
°C/W
ψJB
Junction-to-board characterization parameter
48
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
–40°C ≤ TA ≤ 125°C for UCC280x-Q1. VCC = 10 V (1), RT = 100 k from REF to RC, CT = 330 pF from RC to GND, 0.1-uF
capacitor from VCC to GND, 0.1-uF capacitor from VREF to GND, and TA= TJ (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.925
5
5.075
3.94
4
4.06
UNIT
REFERENCE
TJ= 25°C, I = 0.2 mA, UCC2800-Q1, UCC2801-Q1, UCC2802-Q1,
and UCC2804-Q1
Output voltage
TJ= 25°C, I = 0.2 mA, UCC2803-Q1 and UCC2805-Q1
Load regulation
0.2 mA < I < 5 mA
Line regulation
UCC280x-Q1
30
1.9
TJ = –40°C to 125°C, VCC = 10 V to
clamp (IVCC = 25 mA)
2.5
UCC280x-Q1
UCC2800-Q1, UCC2801-Q1, UCC2802-Q1, and UCC2804-Q1 (2)
Total variation
10
TJ = 25°C, VCC = 10 V to clamp (IVCC = 25 mA)
UCC2803-Q1 and UCC2805-Q1 (2)
Output noise voltage
10 Hz ≤ f ≤ 10 kHz, TJ= 25°C (3)
Long term stability
TA = 125°C, 1000 hours (3)
Output short circuit
4.88
5
5.1
3.9
4
4.08
V
mV
mV/V
V
130
µV
5
mV
–5
–35
mA
OSCILLATOR
Oscillator frequency
UCC2800-Q1, UCC2801-Q1, UCC2802-Q1, UCC2804-Q1 (4)
40
46
52
UCC2803-Q1 and UCC2805-Q1 (4)
26
31
36
Temperature stability (3)
2.5
Amplitude peak-to-peak
2.25
Oscillator peak voltage
2.4
kHz
%
2.55
2.45
V
V
ERROR AMPLIFIER
Input voltage
COMP = 2.5 V, UCC2800-Q1, UCC2801-Q1, UCC2802-Q1, and
UCC2804-Q1
2.44
2.5
2.56
COMP = 2 V, UCC2803-Q1 and UCC2805-Q1
1.95
2
2.05
Input bias current
–1
Open loop voltage gain
60
COMP sink current
FB = 2.7 V, COMP = 1.1 V
COMP source current
FB = 1.8 V, COMP = REF – 1.2 V
Gain bandwidth product (3)
(1)
(2)
(3)
(4)
UCC280x-Q1
1
µA
3.5
mA
80
dB
0.3
–0.2
–0.5
V
–0.8
2
mA
MHz
Adjust VCC above the start threshold before setting at 10 V.
Total variation includes temperature stability and load regulation.
Ensured by design. Not 100% tested in production.
Oscillator frequency for the UCCx800, UCC2802, and UCC2803 is the output frequency. Oscillator frequency for the UCC2801,
UCC2804, and UCC2805 is twice the output frequency.
Copyright © 2002–2020, Texas Instruments Incorporated
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UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
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Electrical Characteristics (continued)
–40°C ≤ TA ≤ 125°C for UCC280x-Q1. VCC = 10 V(1), RT = 100 k from REF to RC, CT = 330 pF from RC to GND, 0.1-uF
capacitor from VCC to GND, 0.1-uF capacitor from VREF to GND, and TA= TJ (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UCC2800-Q1, UCC2802-Q1, and UCC2803-Q1
97
99
100
UCC2801-Q1, UCC2804-Q1, and UCC2805-Q1
48
49
50
1.1
1.65
1.8
0.9
1
1.1
V
200
nA
PWM
Maximum duty cycle
%
CURRENT SENSE
Gain (5)
Maximum input signal
COMP = 5 V (6)
Input bias current
–200
CS blank time
50
100
150
ns
1.42
1.55
1.68
V
0.45
0.9
1.35
V
I = 20 mA, all parts
0.1
0.4
I = 200 mA, all parts
0.35
0.9
I = 50 mA, VCC = 5 V, UCC2803-Q1 and UCC2805-Q1
0.15
0.4
Overcurrent threshold
COMP to CS offset
V/V
CS = 0 V
OUTPUT
OUT low level
I = 20 mA, VCC = 0 V, all parts
V
0.7
1.2
0.15
0.4
1
1.9
I = 50 mA, VCC = 5 V, UCC2803-Q1 and UCC2805-Q1
0.4
0.9
Rise time
CL = 1 nF
41
70
ns
Fall time
CL = 1 nF
44
75
ns
I = 20 mA, all parts
OUT high VSAT (VCC-OUT)
I = 200 mA, all parts
V
UNDERVOLTAGE LOCKOUT
Start threshold (7)
Stop threshold (7)
UCC2800-Q1
6.6
7.2
7.8
UCC2801-Q1
8.6
9.4
10.2
UCC2802-Q1 and UCC2804-Q1
11.5
12.5
13.5
UCC2803-Q1 and UCC2805-Q1
3.7
4.1
4.5
UCC2800-Q1
6.3
6.9
7.5
UCC2801-Q1
6.8
7.4
8
UCC2802-Q1 and UCC2804-Q1
7.6
8.3
9
UCC2803-Q1 and UCC2805-Q1
Start to stop hysteresis
V
V
3.2
3.6
4
UCC2800-Q1
0.12
0.3
0.48
UCC2801-Q1
1.6
2
2.4
UCC2802-Q1 and UCC2804-Q1
3.5
4.2
5.1
UCC2803-Q1 and UCC2805-Q1
0.2
0.5
0.8
4
10
ms
V
SOFT START
COMP rise time
FB = 1.8 V, rise from 0.5 V to REF – 1 V
OVERALL
Start-up current
VCC < start threshold
0.1
0.2
mA
Operating supply current
FB = 0 V, CS = 0 V
0.5
1
mA
VCC internal Zener voltage
ICC = 10 mA (7) (8)
12
13.5
15
V
0.5
1
VCC internal Zener voltage minus
start threshold voltage
(5)
(6)
(7)
(8)
8
UCC2802-Q1 and UCC2804-Q1
(7)
V
Gain is defined by: A = ΔVCOMP / Δ VCS. 0 ≤ VCS ≤ 0.8 V
Parameter measured at trip point of latch with Pin 2 at 0 V.
Start threshold, stop threshold, and Zener shunt thresholds track one another.
The device is fully operating in clamp mode, as the forcing current is higher than the normal operating supply current.
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UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
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SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
8.6 Typical Characteristics
4.00
3.98
3.96
VREF (V)
3.94
3.92
3.90
3.88
3.86
3.84
3.82
4
Figure 1. Error Amplifier Gain and Phase Response
4.4
4.6
4.8
5
5.2
VCC (V)
5.4
5.6
5.8
6
Figure 2. UCC2803-Q1 and UCC2805-Q1VREF vs VCC,
ILOAD = 0.5 mA
1000
1000
Oscillator Freq. (kHz)
Oscillator Freq. (kHz)
4.2
10
0p
F
100
20
0p
33 F
0p
F
100
10
0p
F
20
0p
33
F
0p
F
1n
F
1n
10
10
10
100
10
1000
1000
RT (k )
RT (k )
Figure 3. UCC2800-Q1, UCC2801-Q1, UCC2802-Q1, and
UCC2804-Q1 Oscillator Frequency vs RT and CT
Figure 4. UCC2803-Q1 and UCC2805-Q1 Oscillator
Frequency
vs RT and CT
100
50
99.5
pF
00
30
pF
=3
00
pF
48
=1
=2
pF
pF
96.5
48.5
CT
00
30
pF
=3
00
CT
=2
97
=1
98
97.5
49
CT
CT
98.5
CT
Maximum Duty Cycle (%)
49.5
99
CT
Maximum Duty Cycle (%)
F
100
47.5
96
47
95.5
46.5
95
10
100
1000
Oscillator Frequency (kHz)
Figure 5. UCC2800-Q1, UCC2802-Q1, and UCC2803-Q1
Maximum Duty Cycle vs Oscillator Frequency
Copyright © 2002–2020, Texas Instruments Incorporated
10
100
1000
Oscillator Frequency (kHz)
Figure 6. UCC2801-Q1, UCC2804-Q1, and UCC2805-Q1
Maximum Duty Cycle vs Oscillator Frequency
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UCC2800-Q1, UCC2801-Q1, UCC2802-Q1
UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
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Typical Characteristics (continued)
16
8
14
7
12
C
VC
8
C
CC
V
=
1n
8V,
6
o Load
10V, N
VCC =
4
VCC = 8V,
2
0
0
100
200
300
400
500
600
700
VC
5
F
ICC (mA)
ICC (mA)
10
nF
,1
0V
6
nF
,1
0V
=1
800
nF
V, 1
4
C
VC
=8
3
VCC =
2
No Load
=1
o Loa
10V, N
d
, No Load
VCC = 8V
1
0
0
900 1000
100
200
300
400
500
600
700
800
900 1000
Oscillator Frequency (kHz)
Oscillator Frequency (kHz)
Figure 7. UCC2800-Q1 ICC vs Oscillator Frequency
Figure 8. UCC2805-Q1 ICC vs Oscillator Frequency
COMP to CS Offset (Volts)
1.1
1.0
0.9
0.8
Slope = 1.8mV/°C
0.7
0.6
0
-55-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 10. COMP to CS Offset vs Temperature, CS = 0 V
Figure 9. Dead Time vs CT, RT = 100 k
10
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UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
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SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
9 Detailed Description
9.1 Overview
The UCC280x-Q1 family of high-speed, low-power integrated circuits contain all of the control and drive
components required for off-line and DC-to-DC fixed-frequency, current-mode switching mode power supplies
with minimal parts count.
These devices have the same pin configuration as the UCx84x family, and also offer the added features of
internal full-cycle soft start and internal leading-edge blanking of the current-sense input.
9.2 Functional Block Diagram
FB
COMP
CS
2
1
3
VCC
7
UCCx801
UCCx804
UCCx805
only
Leading Edge
Blanking
1.5V
VCC
OK
REF/2
Over-Current
T Q
S Q
OUT
0.65R
R
4V
Voltage
Reference
REF
OK
Oscillator
S Q
6
R
S Q
PWM
Latch
13.5V
R
0.5V
Logic
Power
R
Full Cycle
Soft Start
1V
j=4ms
GND
5
8
4
REF
RC
Copyright © 2016, Texas Instruments Incorporated
9.3 Feature Description
The UCC280x-Q1 family offers numerous advantages that allow the power supply design engineer to meet these
challenging requirements.
Features include:
• Bi-CMOS process
• Low starting supply current: typically 100 μA
• Low operating supply current: typically 500 μA
• Pinout compatible with UC3842 and UC3842A families
• 5-V operation (UCC2803-Q1 and UCC2805-Q1)
• Leading edge blanking of current sense signal
• On-chip soft start
• Internal full cycle restart delay
• 1.5% voltage reference
• Up to 1-MHz oscillator
• Low self-biasing output during UVLO
• Very few external components required
• 70-ns response from current sense to output
• Available in surface-mount or PDIP package
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UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
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Feature Description (continued)
The UCC280x-Q1 family of devices are pinout compatible with the UCx84x and UCx84xA families. However,
they are not plug-in compatible. In general, the UCC280x-Q1 requires fewer external components and consumes
less operating current.
9.3.1 Detailed Pin Description
9.3.1.1 COMP
Unlike other devices, the error amplifier in the UCC280x-Q1 family is a true, low output impedance, 2-MHz
operational amplifier. As such, the COMP terminal can both source and sink current. However, the error amplifier
is internally current-limited, so that one can command zero duty cycle by externally forcing COMP to GND.
The UCC280x-Q1 has a true low output impedance error amplifier which both sources and sinks current. The
error amplifier associated with the UC3842 family is an open collector in parallel with a current source.
The UCC280x-Q1 has power-up soft start and fault soft start built on-chip with a fixed COMP rise time to 5 V in
4 ms. Therefore, no external soft-start circuitry is required, saving 1 resistor, 1 capacitor, and 1 PNP transistor.
9.3.1.2 FB
FB is the inverting input of the error amplifier. For best stability, keep FB lead length as short as possible and FB
stray capacitance as small as possible.
The UCC280x-Q1 features a 2-MHz bandwidth error amplifier versus 1 MHz on the UC3842 family. Feedback
techniques are identical to the UC3842 family.
9.3.1.3 CS
CS is the PWM comparator and an overcurrent comparator. The UCC280x-Q1 family contains digital current
sense filtering, which disconnects the CS terminal from the current sense comparator during the 100-ns interval
immediately following the rising edge of the OUT pin. This digital filtering, also called leading-edge blanking,
means that in most applications, no analog filtering (RC filter) is required on CS. Compared to an external RC
filter technique, the leading-edge blanking provides a smaller effective CS to OUT propagation delay. Note,
however, that the minimum non-zero on-time of the OUT signal is directly affected by the leading-edge-blanking
and the CS to OUT propagation delay. The overcurrent comparator is only intended for fault sensing, and
exceeding the overcurrent threshold causes a soft-start cycle.
The UCC280x-Q1 current sense is significantly different from its predecessor. The UC3842 family current sense
input connects to only the PWM comparator. The UCC280x-Q1 current sense input connects to two
comparators: the PWM comparator and the overcurrent comparator. Internal leading edge blanking masks the
first 100 ns of the current sense signal. This may eliminate the requirement for an RC current sense filter and
prevent false triggering due to leading edge noises. Connect CS directly to MOSFET source current sense
resistor. The gain of the current sense amplifier on the UCC280x-Q1 family is typically 1.65 V/V versus typically 3
V/V with the UC3842 family.
9.3.1.4 RC
RC is the oscillator timing pin. For fixed frequency operation, set timing capacitor charging current by connecting
a resistor from REF to RC. Set frequency by connecting timing capacitor from RC to GND. For the best
performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate
ground traces for the timing capacitor and all other functions.
The UCC280x-Q1’s oscillator allows for operation to 1 MHz versus 500 kHz with the UC3842 family. Both
devices make use of an external resistor to set the charging current for the capacitor, which determines the
oscillator frequency. For the UCC2802-Q1 and UCC2804-Q1, use Equation 4.
1.5
f =
R´C
(4)
For the UCC2803 and UCC2805, use Equation 5.
1.0
f =
R´C
12
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(5)
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SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
Feature Description (continued)
In these two equations, switching frequency (f) is in Hz, R is in Ω, and C is in farads.
The two equations are different due to different reference voltages. The recommended range of timing resistor
values is between 10 kΩ and 200 kΩ; the recommended range of timing capacitor values is between 100 pF and
1000 pF. The peak-to-peak amplitude of the oscillator waveform is 2.45 V versus 1.7 V in UC3842 family. For
best performance, keep the timing capacitor lead to GND as short as possible. TI recommends separate ground
traces for the timing capacitor and all other pins. The maximum duty cycle for the UCC2802-Q1 and UCC2803Q1 is approximately 99%; the maximum duty cycle for the UCC2803-Q1 and UCC2804-Q1 is approximately
49%. The duty cycle cannot be easily modified by adjusting RT and CT, unlike the UC3842A family. The
maximum duty cycle limit is set by the ratio of the external oscillator charging resistor RT and the internal
oscillator discharge transistor on-resistance, like the UC3842. However, maximum duty cycle limits less than
90% (for the UCC2802-Q1 and UCC2803-Q1) and less than 45% (for the UCC2804-Q1 and UCC2805-Q1) can
not reliably be set in this manner. For better control of maximum duty cycle, consider using the UCCx807-Q1.
9.3.1.5 GND
GND pin is the signal and power returning ground. TI recommends separating the signal return path and the high
current gate driver path so that the signal is not affected by the switching current.
9.3.1.6 OUT
OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET with peak
currents exceeding 750 mA. OUT is actively held low when VCC is below the UVLO threshold. The high-current
power driver consists of FET output devices, which can switch all of the way to GND and all of the way to VCC.
The output stage also provides a low impedance to overshoot and undershoot. This means that in many cases,
external Schottky clamp diodes are not required.
The output of the UCC280x-Q1 is a CMOS output versus a Bipolar output on the UC3842 family. Peak output
current remains the same ±1 A. The CMOS output provides very smooth rising and falling waveforms, with
virtually no overshoot or undershoot. Additionally, the CMOS output provides a low resistance to the supply in
response to overshoot, and a low resistance to ground in response to undershoot. Because of this, Schottky
diodes may not be necessary on the output. Furthermore, the UCC2802-Q1 has a self-biasing, active low output
during UVLO. This feature eliminates the gate to source bleeder resistor associated with the MOSFET gate drive.
Finally, no MOSFET gate voltage clamp is necessary with the UCC280x-Q1 as the on-chip Zener diode
automatically clamps the output to VCC.
9.3.1.7 VCC
VCC is the power input connection for this device. In normal operation, VCC is powered through a current
limiting resistor. Although quiescent VCC current is very low, total supply current is higher, depending on the
OUT current. Total VCC current is the sum of quiescent VCC current and the average OUT current. Knowing the
operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from
Equation 6.
IOUT = Qg ´ f
(6)
The UCC280x-Q1 has a lower VCC (supply voltage) clamp of 13.5 V typical versus 30 V on the UC3842. For
applications that require a higher VCC voltage, a resistor must be placed in series with VCC to increase the
source impedance. The maximum value of this resistor is calculated with Equation 7.
Rmax=
VIN:min; -VVCC:max;
IVCC +Qg ×f
(7)
In Equation 7, VIN(min) is the minimum voltage that is used to supply VCC, VVCC(max) is the maximum VCC
clamp voltage and IVCC is the IC supply current without considering the gate driver current and Qg is the external
power MOSFET gate charge and f is the switching frequency.
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UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
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Feature Description (continued)
Additionally, the UCC280x-Q1 has an on-chip Zener diode to regulate VCC to 13.5 V. The turnon and turnoff
thresholds for the UCC280x-Q1 family are significantly different: 12.5 V and 8 V for the UCC2802-Q1 and
UCC2804-Q1;
4.1 V and 3.6 V for the UCC2803-Q1 and UCC2805-Q1. 5-V PWM operation is now possible. To ensure against
noise related problems, filter VCC with an electrolytic and bypass with a ceramic capacitor to ground. Keep the
capacitors close to the IC pins.
9.3.1.8 Pin 8 (REF)
REF is the voltage reference for the error amplifier and also for many other functions on the IC. REF is also used
as the logic power supply for high-speed switching logic on the IC. When VCC is greater than 1 V and less than
the UVLO threshold, REF is pulled to ground through a 5-kΩ resistor. This means that REF can be used as a
logic output indicating power system status. It is important for reference stability that REF is bypassed to GND
with a ceramic capacitor as close to the pin as possible. An electrolytic capacitor may also be used in addition to
the ceramic capacitor. A minimum of 0.1-μF ceramic capacitor is required. Additional REF bypassing is required
for external loads greater than 2.5 mA on the reference. To prevent noise problems with high-speed switching
transients, bypass REF to ground with a ceramic capacitor close to the IC package.
The UCC2802-Q1 and UCC2804-Q1 have a 5-V reference. The UCC2803-Q1 and UCC2805-Q1 have a 4-V
reference; both ±1.5% versus ±2% on the UC3842-Q1 family. The output short-circuit current is lower 5 mA
versus 30 mA. REF must be bypassed to ground with a ceramic capacitor to prevent oscillation and noise
problems. REF can be used as a logic output; as when VCC is lower than the UVLO threshold, REF is held low.
9.3.2 Undervoltage Lockout (UVLO)
The UCC280x-Q1 devices feature undervoltage lockout protection circuits for controlled operation during powerup and power-down sequences. Both the supply voltage (VCC) and the reference voltage (Vref) are monitored
by the UVLO circuitry. An active low, self-biasing totem pole output during UVLO design is also incorporated for
enhanced power switch protection.
Undervoltage lockout thresholds for the UCC2802-Q1, UCC2803-Q1, UCC2804-Q1, and UCC2805-Q1 devices
are different from the previous generation of UCx842-Q1, UCx843-Q1, UCx844-Q1, and UCx845-Q1 PWMs.
Basically, the thresholds are optimized for two groups of applications: off-line power supplies and DC-DC
converters.
The UCC2802-Q1 and UCC2804-Q1 feature typical UVLO thresholds of 12.5 V for turnon and 8.3 V for turnoff,
providing 4.3 V of hysteresis.
For low voltage inputs, which include battery and 5-V applications, the UCC2803-Q1 and UCC2805-Q1 turn on at
4.1 V and turn off at 3.6 V with 0.5 V of hysteresis.
The UCC2800-Q1 and UCC2801-Q1 have UVLO thresholds optimized for automotive and battery applications.
During UVLO the IC draws approximately 100 μA of supply current. Once crossing the turnon threshold the IC
supply current increases typically to about 500 μA, over an order of magnitude lower than bipolar counterparts.
Figure 11. IC Supply Current at UVLO
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UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
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SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
Table 1. UVLO Level Comparison Table
DEVICE
Vton (V)
Vtoff (V)
UCC2800-Q1
7.2
6.9
UCC2801-Q1
9.4
7.4
UCC2802-Q1, UCC2804-Q1
12.5
8.3
UCC2803-Q1, UCC2805-Q1
4.1
3.6
9.3.3 Self-Biasing, Active Low Output
The self-biasing, active low clamp circuit shown in Figure 12 eliminates the potential for problematic MOSFET
turnon. As the PWM output voltage rises while in UVLO, the P device drives the larger N type switch ON, which
clamps the output voltage low. Power to this circuit is supplied by the externally rising gate voltage, so full
protection is available regardless of the ICs supply voltage during undervoltage lockout.
2V
VCC = OPEN
VOUT
VCC = 2 V
VCC = 0 V
VCC = 1 V
1V
50 mA
100 mA
IOUT
Figure 12. Internal Circuit Holding OUT Low
During UVLO
Figure 13. OUT Voltage vs OUT Current
During UVLO
9.3.4 Reference Voltage
The traditional 5-V amplitude bandgap reference voltage of the UC3842-Q1 family can be also found on the
UCC2800-Q1, UCC2801-Q1, UCC2802-Q1, and UCC2804-Q1 devices. However, the reference voltage of the
UCC2803-Q1 and UCC2805-Q1 device is 4 V. This change was necessary to facilitate operation with input
supply voltages below 5 V. Many of the reference voltage specifications are similar to the UC3842 devices
although the test conditions have been changed, indicative of lower-current PWM applications. Similar to their
bipolar counterparts, the BiCMOS devices internally pull the reference voltage low during UVLO, which can be
used as a UVLO status indication.
UCC380X
REF
R
TO
R
0.1 µF
BYPASS
E/A+
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Required Reference Bypass
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UCC2803-Q1, UCC2804-Q1, UCC2805-Q1
SGLS121D – DECEMBER 2002 – REVISED JUNE 2020
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Note that the 4-V reference voltage on the UCC2803-Q1 and UCC2805-Q1 is derived from the supply voltage
(VCC) and requires about 0.5 V of headroom to maintain regulation. Whenever Vcc is below approximately 4.5
V, the reference voltage also drops outside of its specified range for normal operation. The relationship between
VCC and VREF during this excursion is shown in Figure 15.
4.0 V
3.9 V
VREF
3.8 V
3.7 V
3.6 V
3.5 V
3.6 V 3.8 V 4.0 V 4.2 V 4.4 V 4.6 V 4.8 V 5.0 V
VCC
Figure 15. UCC2803-Q1 REF Output vs VVCC
The noninverting input to the error amplifier is tied to half of the PWM's reference voltage, VREF. Note that this
input is 2 V on the UCC2803-Q1 and UCC2805-Q1 and 2.5 V on the higher reference voltage parts: the
UCC2800-Q1, UCC2801-Q1, UCC2802-Q1, and UCC2804-Q1.
9.3.5 Oscillator
The UCC280x-Q1 oscillator generates a sawtooth waveform on RC. The rise time is set by the time constant of
RT and CT. The fall time is set by CT and an internal transistor on-resistance of approximately 130 Ω. During the
fall time, the output is OFF and the maximum duty cycle is reduced below 50% or 100%, depending on the part
number. Larger timing capacitors increase the discharge time and reduce the maximum duty cycle and
frequency.
REF
8
0.2V
+
RT
R
+
RC
4
Q
S
2.65V
CT
Figure 16. Oscillator Equivalent Circuit
The oscillator section of the UCC2800-Q1 through UCC2805 BiCMOS devices has few similarities to the
UC3842 type — other than single pin programming. It does still use a resistor to the reference voltage and
capacitor to ground to program the oscillator frequency up to 1 MHz. Timing component values must be changed
because a much lower charging current is desirable for low-power operation. Several characteristics of the
oscillator have been optimized for high-speed, noise-immune operation. The oscillator peak-to-peak amplitude
has been increased to 2.45 V typical versus 1.7 V on the UC3842 family. The lower oscillator threshold has been
dropped to approximately 0.2 V while the upper threshold remains fairly close to the original 2.8 V at
approximately
2.65 V.
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Discharge current of the timing capacitor has been increased to nearly 20-mA peak as opposed to roughly 8 mA.
This can be represented by approximately 130 Ω in series with the discharge switch to ground. A higher current
was necessary to achieve brief dead times and high duty cycles with high-frequency operation. Practical
applications can use these new ICs to a 1-MHz switching frequency.
2.65 V
VCT
0.2 V
0V
fCONV
Figure 17. Oscillator Waveform
1000
800
600
ƒ (kHz)
400
200
CT = 100 p
100
80
60
CT = 180 p
CT = 270 p
CT = 390 p
CT = 470 p
40
20
0
20
40
60
80
100
120
RT (kW)
Figure 18. Oscillator Frequency vs RT For Several CT
9.3.6 Synchronization
Synchronization of these PWM controllers is best obtained by the universal technique shown in Figure 19. The
ICs oscillator is programmed to free run at a frequency about 20% lower than that of the synchronizing
frequency. A brief positive pulse is applied across the 50-Ω resistor to force synchronization. Typically, a 1-V
amplitude pulse of 100-ns width is sufficient for most applications.
The ICs can also be synchronized to a pulse train input directly to the oscillator RC pin. Note that the IC
internally pulls low at this node once the upper oscillator threshold is crossed. This 130-Ω impedance to ground
remains active until the pin is lowered to approximately 0.2 V. External synchronization circuits must
accommodate these conditions.
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REF
RT
RC
CT
SYNC
§ 50
Figure 19. Synchronizing the Oscillator
9.3.7 PWM Generator
Maximum duty cycle is higher for these devices than for their UC384x predecessor. This is primarily due to the
higher ratio of timing capacitor discharge to charge current, which can exceed one hundred to one in a typical
BiCMOS application. Attempts to program the oscillator maximum duty cycle much below the specified range by
adjusting the timing component values of RT and CT must be avoided. There are two reasons to stay away from
this design practice. First, the ICs high discharge current would necessitate higher charging currents than
necessary for programming, defeating the purpose of low power operation. Secondly, a low-value timing resistor
prevents the capacitor from discharging to the lower threshold and initiating the next switching cycle.
9.3.8 Minimum Off-Time Setting (Dead-Time Control)
Dead time is the term used to describe the ensured OFF time of the PWM output during each oscillator cycle. It
is used to ensure that even at maximum duty cycle, there is enough time to reset the magnetic circuit elements,
and prevent saturation. The dead time of the UCC280x-Q1 PWM family is determined by the internal 130-Ω
discharge impedance and the timing capacitor value. Larger capacitance values extend the dead time whereas
smaller values results in higher maximum duty cycles for the same operating frequency. A curve for dead time
versus timing capacitor values is provided in Figure 20. Increasing the dead time is possible by adding a resistor
between the RC pin of the IC and the timing components, as shown in Figure 21. The dead time increases with
the discharge resistor value to about 470 Ω as indicated from the curve in Figure 22. Higher resistances must be
avoided as they can decrease the dead time and reduce the oscillator peak-to-peak amplitude. Sinking too much
current (1 mA) by reducing RT will freeze the oscillator OFF by preventing discharge to the lower comparator
threshold voltage of 0.2 V. Adding this discharge control resistor has several impacts on the oscillator
programming. First, it introduces a DC offset to the capacitor during the discharge – but not the charging portion
of the timing cycle, thus lowering the usable peak-to-peak timing capacitor amplitude. Because of the reduced
peak-to-peak amplitude, the exact value of CT may require adjustment from UC3842 type designs to obtain the
correct initial oscillator frequency. One alternative is keep the same value timing capacitor and adjust both the
timing and discharge resistor values because these are readily available in finer numerical increments.
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200
180
REF
160
RT
Td (ns)
140
RD
120
RC