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ULN2003LV
SLRS059B – APRIL 2012 – REVISED JUNE 2015
ULN2003LV 7-Channel Relay and Inductive Load Sink Driver
1 Features
3 Description
•
•
•
The ULN2003LV is a low-voltage and low power
upgrade of TI’s popular ULN2003 family of 7-channel
Darlington transistor array. The ULN2003LV sink
driver features 7 low output impedance drivers to
support low voltage relay and inductive coil
applications. The low impedance drivers minimize onchip power dissipation; up to 5 times lower for typical
3V relays. The ULN2003LV driver is pin-to-pin
compatible with ULN2003 family of devices in similar
packages.
1
•
•
•
•
•
•
•
•
•
(1)
7-Channel High Current Sink Drivers
Supports up to 8V Ouput Pullup Voltage
Supports a Wide Range of 3V-to-5V Relay and
Inductive Coils
Low Output VOL of 0.4V (Typical) With
– 100mA (Typical) Current Sink per Channel at
3.3V Logic Input(1)
– 140mA (Typical) Current Sink per Channel at
5.0V Logic Input(1)
Compatible to 3.3V and 5.0V Microcontrollers and
Logic Interface
Internal Free-Wheeling Diodes for Inductive Kickback Protection
Input Pulldown Resistors Allows3-stating the Input
Driver
Input RC-Snubber to Eliminate Spurious
Operation in Noisy Environment
Low Input and Output Leakage Currents
Easy to use Parallel Interface
ESD Protection Exceeds JESD 22
– 2kV HBM, 500V CDM
Available in 16-Pin SOIC and TSSOP Packages
Total current sink may be limited by the internal junction
temperature, absolute maximum current levels etc - refer to
the Electrical Specifications section for details.
2 Applications
•
•
•
Relay and Inductive Load Driver in Various
Telecom, Consumer, and Industrial Applications
Lamp and LED Displays
Logic Level Shifter
The ULN2003LV supports 3.3V to 5V CMOS logic
input interface thus making it compatible to a wide
range of micro-controllers and other logic interfaces.
The ULN2003LV features an improved input interface
that minimizes the input DC current drawn from the
external drivers. The ULN2003LV features an input
RC snubber that greatly improves its performance in
noisy operating conditions. The ULN2003LV channel
inputs feature an internal input pull-down resistor thus
allowing input logic to be tri-stated. The ULN2003LV
may also support other logic input levels, for
example, TTL and 1.8V, refer to the Application
Information section for details.
The ULN2003LV provides flexibility of increasing
current sink capability through combining several
adjacent channels in parallel. Under typical conditions
the ULN2003LV can support up to 1.0A of load
current when all 7-channels are connected in parallel.
The ULN2003LV can also be used in a variety of
applications requiring a sink drivers like driving LEDs
and Logic Level Shifting.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ULN2003LVDR
SOIC (16)
3.90 mm x 9.90 mm
ULN2003LVPWR
TSSOP (16)
4.40 mm x 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Function Diagram
IN1
1
16
OUT1
IN2
2
15
OUT2
IN3
3
14
OUT3
IN4
4
13
OUT4
IN5
5
12
OUT5
IN6
6
11
OUT6
IN7
7
10
OUT7
GND
8
9
COM
ULN2003LV TSSOP/SOIC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ULN2003LV
SLRS059B – APRIL 2012 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ........................................ 8
7.3 Feature Description .................................................. 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application .................................................. 10
8.3 System Examples ................................................... 12
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
On-Chip Power Dissipation...................................
Thermal Considerations ........................................
16
16
16
17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2012) to Revision B
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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Product Folder Links: ULN2003LV
ULN2003LV
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SLRS059B – APRIL 2012 – REVISED JUNE 2015
5 Pin Configuration and Functions
D or PW Package
16-Pin SOIC or TSSOP
Top View
IN1
1
16
OUT1
IN2
2
15
OUT2
IN3
3
14
OUT3
IN4
4
13
OUT4
IN5
5
12
OUT5
IN6
6
11
OUT6
IN7
7
10
OUT7
GND
8
9
COM
16-Pin
SOIC/TSSOP
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
IN1
1
Input
IN2
2
Input
IN3
3
Input
IN4
4
Input
IN5
5
Input
IN6
6
Input
IN7
7
Input
GND
8
Ground
Ground Reference Pin
COM
9
Output
Internal Free-Wheeling Diode Common Cathode Pin
OUT7
10
Output
OUT6
11
Output
OUT5
12
Output
OUT4
13
Output
OUT3
14
Output
OUT2
15
Output
OUT1
16
Output
Logic Input Pins IN1 through IN7
Channel Output Pins OUT7 through OUT1
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3
ULN2003LV
SLRS059B – APRIL 2012 – REVISED JUNE 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Specified at TJ = –40°C to 125°C unless otherwise noted. (1)
MIN
MAX
UNIT
–0.3
5.5
V
Pins OUT1 – OUT7 to GND voltage
8
V
Pin COM to GND voltage
8
V
700
mA
VIN
Pins IN1- IN7 to GND voltage
VOUT
VCOM
Maximum GND-pin continuous current (TJ > +125°C)
IGND
Maximum GND-pin continuous current (TJ < +100°C)
1.0
A
16 Pin - SOIC
0.58
W
16 Pin -TSSOP
0.45
W
PD
Total device power dissipation at TA = 85°C
TA
Operating free-air ambient temperature
–40
85
°C
TJ
Operating virtual junction temperature
–55
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VOUT
Channel off-state output pullup voltage
8
V
VCOM
COM pin voltage
8
V
IOUT(ON)
Per channel continuous sink current
TJ
Operating junction temperature
(1)
VINx = 3.3 V
100 (1)
VINx = 5.0 V
140 (1)
–40
125
mA
ºC
Refer to Absolute Maximum Ratings for TJ dependent absolute maximum GND-pin current
6.4 Thermal Information
ULN2003LV
THERMAL METRIC (1)
D (SOIC)
PW (TSSOP)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
112
142
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
69
74
°C/W
RθJB
Junction-to-board thermal resistance
69
87
°C/W
ψJT
Junction-to-top characterization parameter
33
22
°C/W
ψJB
Junction-to-board characterization parameter
69
87
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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ULN2003LV
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SLRS059B – APRIL 2012 – REVISED JUNE 2015
6.5 Electrical Characteristics
Specified over the recommended junction temperature range TJ = –40°C to 125°C unless otherwise noted. Typical values are
at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUTS IN1 THROUGH IN7 PARAMETERS
VI(ON)
IN1–IN7 logic high input voltage
Vpull-up = 3.3 V, Rpullup = 1 kΩ, IOUTX = 3.2 mA
VI(OFF)
IN1–IN7 logic low input voltage
Vpullup = 3.3 V, Rpullup = 1 kΩ,
(IOUTX = VIH).
VSUP
Logic Inputs
(1.8V to 5V)
ULN2003LV
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
IN1 NOR IN2
IN3 NOR IN4
VSUP
IN1 NOR IN2 NOR IN3
GND
VSUP
COM
Figure 12. ULN2003LV as a NOR driver
14
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SLRS059B – APRIL 2012 – REVISED JUNE 2015
System Examples (continued)
8.3.5 1.8-V Relay Driver
To drive lower voltage relays, like 1.8V, connect two or more adjacent channels in parallel as shown in Figure 13.
Connecting several channels in parallel lowers the channel output resistance and thus minimizes VOL for a fixed
current.
VSUP
1.8V Relays
ULN2003LV
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
1.8V Logic
1.8V Logic
1.8V Logic
GND
VSUP
COM
Figure 13. ULN2003LV Driving 1.8V Relays
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ULN2003LV
SLRS059B – APRIL 2012 – REVISED JUNE 2015
www.ti.com
9 Power Supply Recommendations
The COM pin is the power supply pin of this device to power the gate drive circuitry. Although not required but
depending on the power supply, TI recommends to put a bypass capacitor of 100 nF across the Vcom pin and
Gnd.
10 Layout
10.1 Layout Guidelines
Thin traces can be used on the input due to the low current logic that is typically used to drive ULN2003LV. Take
care to separate the input channels as much as possible, as to eliminate cross-talk. Thick traces are
recommended for the output, in order to drive high currents that may be needed. Wire thickness can be
determined by the trace material's current density and desired drive current. Since all of the channels currents
return to a common ground, it is best to size that trace width to be very wide. Some applications require up to 1
A.
10.2 Layout Example
1
IN1
OUT1
16
2
IN2
OUT2
15
3
IN3
OUT3
14
4
IN4
OUT4
13
5
IN5
OUT5
12
6
IN6
OUT6
11
7
IN7
OUT7
10
8
Gnd
COM
9
Cbypass 0.1uF
Figure 14. Layout Example Recommendation
10.3 On-Chip Power Dissipation
Use Equation 3 to calculate ULN2003LV on-chip power dissipation PD:
N
PD = å VOLi ´ ILi
i=1
where
•
•
16
N is the number of channels active together.
VOLi is the OUTi pin voltage for the load current ILi.
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(3)
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Product Folder Links: ULN2003LV
ULN2003LV
www.ti.com
SLRS059B – APRIL 2012 – REVISED JUNE 2015
10.4 Thermal Considerations
TI recommends to limit ULN2003LV IC’s die junction temperature to less than 125°C. The IC junction
temperature is directly proportional to the on-chip power dissipation. Use the following equation to calculate the
maximum allowable on-chip power dissipation for a target IC junction temperature:
PD(MAX) =
(T
J(MAX)
- TA )
qJA
where
•
•
•
TJ(MAX) is the target maximum junction temperature.
TA is the operating ambient temperature.
RθJA is the package junction to ambient thermal resistance.
(4)
10.4.1 Improving Package Thermal Performance
The package RθJA value under standard conditions on a High-K board is listed in the Dissipation Ratings. RθJA
value depends on the PCB layout. An external heat sink and/or a cooling mechanism, like a cold air fan, can help
reduce RθJA and thus improve device thermal capabilities. Refer to TI’s design support web page at
www.ti.com/thermal for a general guidance on improving device thermal performance.
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ULN2003LV
SLRS059B – APRIL 2012 – REVISED JUNE 2015
www.ti.com
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ULN2003LVDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
UN2003LV
ULN2003LVPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
UN2003LV
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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