BCM43903KUBGT

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CYW43903 PRELIMINARY WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor The Cypress CYW43903 embedded wireless system-on-a-chip (SoC) is uniquely suited for Internet-of-Things applications. It supports all rates specified in the IEEE 802.11 b/g/n specifications.The device includes an ARM Cortex-based applications processor, a single stream IEEE 802.11n MAC/baseband/radio, a power amplifier (PA), and a receive low-noise amplifier (LNA). It also supports optional antenna diversity for improved RF performance in difficult environments. The CYW43903 is an optimized SoC targeting embedded Internet-of-Things applications in the industrial and medical sensor, home appliance markets. Using advanced design techniques and process technology to reduce active and idle power, the device is designed for embedded applications that require minimal power consumption and a compact size. The device includes a PMU for simplifying system power topology and allows for direct operation from a battery while maximizing battery life. Features Application Processor Features mizing the need to wake up the applications processor for standard WLAN functions (to further minimize power consumption while maintaining the ability to upgrade to future features in the field). ■ ARM Cortex-R4 32-bit RISC processor. ■ 1 MB of on-chip SRAM for code and data. ■ An on-chip cryptography core ■ 640 KB of ROM containing WICED SDK components such as RTOS and TCP/IP stack. ■ 17 GPIOs supported. ■ Q-SPI serial flash interface to support up to 40 Mbps of peak transfer. ■ Support for UART (3), SPI or CSC master, interfaces. (Cypress Serial Control (CSC) is an I2C-compatible interface.) ■ Software architecture supported by standard WICED SDK allows easy migration from existing discrete MCU designs and to future devices. ■ Security support: Key IEEE 801.11x Features ■ Single-band 2.4 GHz IEEE 802.11n compliant. ■ Single-stream spatial multiplexing up to 72 Mbps. ■ Supports 20 MHz channels with optional SGI. ■ Full IEEE 802.11 b/g legacy compatibility with enhanced performance. ■ On-chip power and low-noise amplifiers. ■ ■ WPA and WPA2 (Personal) support for powerful encryption and authentication. ❐ AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility. ❐ Reference WLAN subsystem provides Cisco Compatible Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, and CCX 5.0). ❐ Wi-Fi Protected Setup and Wi-Fi Easy-Setup Worldwide regulatory support: Global products supported with worldwide design approval. ❐ ■ General Features ■ Supports battery voltage range from 3.0V to 4.8V with an internal switching regulator. An internal fractional nPLL allows support for a wide range of reference clock frequencies. ■ Programmable dynamic power management. ■ 6 Kb OTP memory for storing board parameters. Integrated ARM Cortex-R4 processor with tightly coupled memory for complete WLAN subsystem functionality, mini- ■ 151-ball WLBGA (4.91mm x 5.85mm, 0.4 mm pitch). Cypress Semiconductor Corporation Document Number: 002-14826 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 23, 2021 PRELIMINARY CYW43903 Figure 1. Functional Block Diagram CYW43903 1 MB RAM, 640 KB ROM UART SPI APPS ARM Cortex-R4 32 KB (I), 32 KB (D) ICACHE CSC PWM (6) PWM CSC SPI SPI or CSC AXI to AXI Bridge GPIO GPIO (17) TCM 512 KB RAM 320 KB ROM JTAG WLAN ARM Cortex-R4 AXI-to-AXI Bridge Crytography Engine AXI AXI DMA 32 kHz External LPO WLAN APPS Domain IEEE 802.11 MAC RF Switch Controls 1 x 1, IEEE 802.11n PHY Always-On Domain REG_ON HIB_REG_ON_IN AXI SR_Eng PMU Control VBAT PS RAM LNA PMU TX Switch PS VIO 2.4 GHz Radio AXI-to-AXI Bridge 2.4 GHz 37.4 MHz Crystal PA TX Switch CSC = Cypress Serial Control. An I2C‐compatible interface. WRF_PAOUT_2G WRF_RFIN_2G Document Number: 002-14826 Rev. *H Page 2 of 65 PRELIMINARY CYW43903 Contents 1. Overview ............................................................ 5 1.1 Introduction ......................................................... 5 1.1.1 Features .................................................. 6 1.2 Standards Compliance ........................................ 7 2. Power Supplies and Power Management ....... 8 2.1 Power Supply Topology ...................................... 8 2.2 CYW43903 Power Management Unit Features .. 8 2.3 Power Management .......................................... 11 2.4 PMU Sequencing .............................................. 11 2.5 Power-Off Shutdown ......................................... 12 2.6 Power-Up/Power-Down/Reset Circuits ............. 12 3. Frequency References ................................... 13 3.1 Crystal Interface and Clock Generation ............ 13 3.2 External Frequency Reference ......................... 14 3.3 External 32.768 kHz Low-Power Oscillator ....... 15 4. Applications Subsystem ................................ 16 7.2.8 MAC-PHY Interface ................................24 7.3 IEEE 802.11™ b/g/n PHY ...................................25 8. WLAN Radio Subsystem ............................... 26 8.1 Receiver Path .....................................................26 8.2 Transmit Path .....................................................26 8.3 Calibration ..........................................................26 9. Pinout and Signal Descriptions..................... 27 9.1 Ball Map .............................................................27 9.2 Ball List ...............................................................28 9.3 Signal Descriptions ............................................30 10. GPIO Signals and Strapping Options ........... 34 10.1 Overview ............................................................34 10.2 Weak Pull-Down and Pull-Up Resistances ........34 10.3 Strapping Options ..............................................34 10.4 Alternate GPIO Signal Functions .......................35 11. Pin Multiplexing .............................................. 36 4.1 Overview ........................................................... 16 4.2 Applications CPU and Memory Subsystem ...... 16 12. I/O States ......................................................... 38 4.3 Memory-to-Memory DMA Core ......................... 16 13. Electrical Characteristics............................... 40 4.4 Cryptography Core ............................................ 16 13.1 Absolute Maximum Ratings ...............................40 5. Applications Subsystem External Interfaces 17 13.2 Environmental Ratings .......................................41 5.1 GPIO ................................................................. 17 5.2 Cypress Serial Control ...................................... 17 5.3 JTAG and ARM Serial Wire Debug ................... 17 5.4 PWM ................................................................. 18 5.5 SPI Flash ........................................................... 18 5.6 UART ................................................................ 18 5.7 SPI .................................................................... 19 6. Global Functions............................................. 20 6.1 External Coexistence Interface ......................... 20 6.2 One-Time Programmable Memory .................... 20 6.3 Hibernation Block .............................................. 20 6.4 System Boot Sequence ..................................... 21 7. Wireless LAN Subsystem............................... 22 7.1 WLAN CPU and Memory Subsystem ............... 22 7.2 IEEE 802.11n MAC ........................................... 22 7.2.1 PSM ....................................................... 23 7.2.2 WEP ...................................................... 23 7.2.3 TXE ........................................................ 23 7.2.4 RXE ....................................................... 24 7.2.5 IFS ......................................................... 24 7.2.6 TSF ........................................................ 24 7.2.7 NAV ....................................................... 24 Document Number: 002-14826 Rev. *H 13.3 Electrostatic Discharge Specifications ...............41 13.4 Recommended Operating Conditions and DC Characteristics ...................................................41 13.5 Power Supply Segments ....................................43 13.6 GPIO, UART, and JTAG Interfaces DC Characteristics ...................................................43 14. WLAN RF Specifications................................ 44 14.1 Introduction ........................................................44 14.2 2.4 GHz Band General RF Specifications ..........44 14.3 WLAN 2.4 GHz Receiver Performance Specifications .....................................................45 14.4 WLAN 2.4 GHz Transmitter Performance Specifications .....................................................47 14.5 General Spurious Emissions Specifications .......48 14.5.1 Transmitter Spurious Emissions Specifications .........................................48 14.5.2 Receiver Spurious Emissions Specifications .........................................48 15. Internal Regulator Electrical Specifications. 49 15.1 Core Buck Switching Regulator .........................49 15.2 3.3V LDO (LDO3P3) ..........................................50 15.3 CLDO .................................................................51 15.4 LNLDO ...............................................................52 Page 3 of 65 PRELIMINARY CYW43903 15.5 BBPLL LDO ....................................................... 53 19. Thermal Information ....................................... 61 16. System Power Consumption ......................... 54 19.1 Package Thermal Characteristics ......................61 16.1 WLAN Current Consumption ............................. 54 16.1.1 2.4 GHz Mode ....................................... 54 19.2 Junction Temperature Estimation and PSIJT Versus THETAJC ............................................................. 61 17. SPI Flash Characteristics............................... 55 17.1 SPI Flash Timing ............................................... 55 17.1.1 Read-Register Timing ............................ 55 17.1.2 Write-Register Timing ............................ 56 17.1.3 Memory Fast-Read Timing .................... 57 17.1.4 Memory-Write Timing ............................ 58 17.1.5 SPI Flash Parameters ........................... 59 19.3 Environmental Characteristics ...........................61 20. Mechanical Information.................................. 62 21. Ordering Information...................................... 63 22. Additional Information ................................... 63 22.1 Acronyms and Abbreviations .............................63 22.2 IoT Resources ....................................................63 18. Power-Up Sequence and Timing ................... 60 22.3 Errata .................................................................63 18.1 Sequencing of Reset and Regulator Control Signals .............................................................. 60 18.1.1 Description of Control Signals ............... 60 18.1.2 Control Signal Timing Diagrams ............ 60 Document History Page ................................................. 64 Document Number: 002-14826 Rev. *H Sales, Solutions, and Legal Information ...................... 65 Page 4 of 65 PRELIMINARY CYW43903 1. Overview 1.1 Introduction The Cypress CYW43903 is a single-chip device that provides the highest level of integration for an embedded system-on-a-chip with integrated IEEE 802.11 b/g/n MAC/baseband/radio and a separate ARM Cortex-R4 applications processor. It provides a small formfactor solution with minimal external components to drive down cost for mass volumes and allows for an embedded system with flexibility in size, form, and function. Comprehensive power management circuitry and software ensure that the system can meet the needs of highly embedded systems that require minimal power consumption and reliable operation. Figure 2 shows the interconnect of all the major physical blocks in the CYW43903 and their associated external interfaces, which are described in greater detail in Applications Subsystem External Interfaces. Figure 2. Block Diagram and I/O CYW43903 RF TX SPI Flash APPS Subsystem WLAN Subsystem ARM Cortex‐R4 160 MHz 32 KB I‐cache 32 KB D‐cache ARM Cortex‐R4 160 MHz 448 KB ROM TCM 576 KB SRAM TCM 1 MB SRAM 640 KB ROM 802.11n 1x1 2.4 GHz RF RX GPIO[16:0] 2x 2-Wire UART 4-Wire UART SPI/CSC CSC JTAG/SWD WAKE Switch Control Antenna Diversity VDDIOs GND Note: Another SPI interface can be defined by reconfiguring GPIO_8 through GPIO_11 and another CSC interface can be defined by reconfiguring GPIO_12 and GPIO_13 (see Table 11, “Pin Multiplexing,”). Document Number: 002-14826 Rev. *H Page 5 of 65 PRELIMINARY CYW43903 1.1.1 Features The CYW43903 supports the following features: ■ ARM Cortex-R4 clocked at 160 MHz. ■ 1 MB of SRAM and 640 KB ROM available for the applications processor. ■ One high-speed 4-wire UART interface with operation up to 4 Mbps. ■ Two low-speed 2-wire UART interfaces multiplexed on general purpose I/O (GPIO) pins. ■ One dedicated CSC1 interface. Note: Another CSC interface can be defined by reconfiguring GPIOs. See Table 11, “Pin Multiplexing,”. ■ One SPI master interface with operation up to 24 MHz. Either or both of the SPI interfaces can be used as CSC master interfaces. This is in addition to the two dedicated CSC interfaces. Note: In addition to the dedicated CSC interface, the SPI interface can be used as a CSC master interface. Note: Another SPI interface can be defined by reconfiguring GPIOs. See Table 11, “Pin Multiplexing,”. ■ One SPI master interface for serial flash. ■ Six dedicated PWM outputs. ■ 17 GPIOs. ■ IEEE 802.11 b/g/n 1×1 2.4 GHz radio. ■ Single- and dual-antenna support. 1.Cypress Serial Control (CSC) is an I2C-compatible interface. Document Number: 002-14826 Rev. *H Page 6 of 65 PRELIMINARY CYW43903 1.2 Standards Compliance The CYW43903 supports the following standards: ■ IEEE 802.11n ■ IEEE 802.11b ■ IEEE 802.11g ■ IEEE 802.11d ■ IEEE 802.11h ■ IEEE 802.11i ■ Security: ■ ❐ WEP ❐ WPA Personal ❐ WPA2 Personal ❐ WMM ❐ WMM-PS (U-APSD) ❐ WMM-SA ❐ AES (hardware accelerator) ❐ TKIP (hardware accelerator) ❐ CKIP (software support) Proprietary Protocols: ❐ CCXv2 ❐ CCXv3 ❐ CCXv4 ❐ CCXv5 ❐ WFAEC The CYW43903 supports the following additional standards: ■ IEEE 802.11r—Fast Roaming (between APs) ■ IEEE 802.11w—Secure Management Frames ■ IEEE 802.11 Extensions: ■ IEEE 802.11e QoS enhancements (already supported as per the WMM specification) ■ IEEE 802.11i MAC enhancements ■ IEEE 802.11k radio resource measurement Document Number: 002-14826 Rev. *H Page 7 of 65 PRELIMINARY CYW43903 2. Power Supplies and Power Management 2.1 Power Supply Topology One core buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43903. All regulators are programmable via the PMU. These blocks simplify power supply design for application and WLAN functions in embedded designs. A single VBAT (3.0V to 4.8V DC maximum) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the CYW43903. The REG_ON control signal is used to power up the regulators and take the appropriate sections out of reset. The CBUCK, CLDO, LNLDO, and other regulators power up when any of the reset signals are deasserted. All regulators are powered down only when REG_ON is deasserted. The regulators may be turned off/on based on the dynamic demands of the digital baseband. The CYW43903 provides a low power-consumption mode whereby the CBUCK, CLDO, and LNLDO regulators are shut down. When in this state, the low-power linear regulator (LPLDO1) supplied by the system VIO supply provides the CYW43903 with all required voltages. 2.2 CYW43903 Power Management Unit Features The CYW43903 supports the following Power Management Unit (PMU) features: ■ VBAT to 1.35Vout (550 mA maximum) core buck (CBUCK) switching regulator ■ VBAT to 3.3Vout (450 mA maximum) LDO3P3 ■ 1.35V to 1.2Vout (350 mA maximum) CLDO with bypass mode for deep-sleep ■ 1.35V to 1.2Vout (55 mA maximum) LDO for BBPLL ■ Additional internal LDOs (not externally accessible) ■ PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from the low power-consumption mode. Figure 3 and Figure 4 show the regulators and a typical power topology. Document Number: 002-14826 Rev. *H Page 8 of 65 PRELIMINARY CYW43903 Figure 3. Typical Power Topology (Page 1 of 2) WLRF TX Mixer and PA (not always) CYW43903 1.2V VBAT Operational: 2.3V to 4.8V Performance: 3.0V to 4.8V Absolute Maximum: 5.5V VDDIO Operational: 3.3V Cap-less LNLDO 1.2V Cap-less LNLDO 1.2V Cap-less VCOLDO 1.2V Cap-less LNLDO 1.2V Cap-less LNLDO 1.2V 15 mA XTAL LDO 1.2V Mini‐PMU (Inside WL Radio) VBAT 1.35V Core Buck Regulator (CBUCK) CLDO WLRF LOGEN WLRF LNA WLRF AFE and TIA WLRF TX WLRF ADC REF WLRF XTAL WLRF RFPLL, PFD, and MMD 1.3V, 1.2V, .095V (AVS) WLAN/CLB/Top, Always On WL PHY WL Subcore WL VDDM (SRAMS in AOS) APPS VDDM VDDIO LPLDO1 1.35V APPS SOCSRAM APPS Subcore REG_ON BBPLL LNLDO 1.2V Supply ball Supply bump/pad Power  switch Ground ball Ground bump/pad No power switch WLAN reset ball External to chip No dedicated power switch, but internal power‐ down modes and block‐specific power switches Document Number: 002-14826 Rev. *H WL BBPLL/DFLL Page 9 of 65 PRELIMINARY CYW43903 Figure 4. Typical Power Topology (Page 2 of 2) CYW43903 2.5V and 3.3V 450 to 800 mA WLRF PA 3.3V VBAT LDO3P3 WLRF Pad VDDIO_RF WL OTP 3.3V 2.5V Cap-less LNLDO WL RF RX, TX, NMOS, Mini-PMU LDOs 2.5V Cap-less LNLDO 2.5V 2.5V Cap-less LNLDO 2.5V WL RF VCO WL RF CP VCOLDO2P5 Inside WL Radio Supply ball Supply bump/pad Power  switch Ground ball Ground bump/pad No power switch External to chip No dedicated power switch, but internal power‐ down modes and block‐specific power switches Document Number: 002-14826 Rev. *H Page 10 of 65 PRELIMINARY CYW43903 2.3 Power Management The CYW43903 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW43903 includes an advanced Power Management Unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW43903 into various power management states appropriate to the environment and activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters (running at a 32.768 kHz LPO clock) in the PMU sequencer are used to turn on and turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) as a function of the mode. Slower clock speeds are used whenever possible. Table 2 provides descriptions for the CYW43903 power modes. Table 2. CYW43903 Power Modes Mode Description Active All WLAN blocks in the CYW43903 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer. Doze The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43903 remains powered up in an idle state. All main clocks (PLL, crystal oscillator, or TCXO) are shut down to minimize active power consumption. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current. Deep-sleep Most of the chip, including both analog and digital domains and most of the regulators, is powered off. Logic states in the digital core are saved and preserved in a retention memory in the Always-On domain before the digital core is powered off. Upon a wake-up event triggered by the PMU timers or an external interrupt, logic states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization. Power-down The CYW43903 is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic re-enabling the internal regulators. 2.4 PMU Sequencing The PMU sequencer minimizes system power consumption. It enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable them. Resource requests can come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by any active resource-request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks. Each resource is in one of the following four states: ■ enabled ■ disabled ■ transition_on ■ transition_off The timer contains 0 when the resource is enabled or disabled and a nonzero value when in a transition state. The timer is loaded with the time_on or time_off value of the resource after the PMU determines that the resource must be enabled or disabled and decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. Document Number: 002-14826 Rev. *H Page 11 of 65 PRELIMINARY CYW43903 During each clock cycle, the PMU sequencer performs the following actions: ■ Computes the required resource set based on requests and the resource dependency table. ■ Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit of the resource and inverts the ResourceState bit. ■ Compares the request with the current resource status and determines which resources must be enabled or disabled. ■ Initiates a disable sequence for each resource that is enabled, is no longer being requested, and has no powered-up dependents. ■ Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. 2.5 Power-Off Shutdown The CYW43903 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other system devices remain operational. When the CYW43903 is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the CYW43903 to be effectively off while keeping the I/O pins powered so that they do not draw extra current from devices connected to the I/O. During a low-power shutdown state, provided VDDIO remains applied to the CYW43903, all outputs are tristated and most inputs signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the CYW43903 to be fully integrated in an embedded device while taking full advantage of the lowest power-saving modes. When the CYW43903 is powered on from this state, it is the same as a normal power-up and does not retain any information about its state from before it was powered down. 2.6 Power-Up/Power-Down/Reset Circuits The CYW43903 has two signals (see Table 3) that enable or disable circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Power-Up Sequence and Timing. Table 3. Power-Up/Power-Down/Reset Control Signals Signal Description REG_ON This signal is used by the PMU to power up the CYW43903. It controls the internal CYW43903 regulators. When this pin is high, the regulators are enabled and the device is out of reset. When this pin is low, the device is in reset and the regulators are disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. HIB_REG_ON_IN This signal is used by the hibernation block to decide whether or not to power down the internal CYW43903 regulators. If HIB_REG_ON_IN is low, the regulators will be disabled. For a signal at HIB_REG_ON_IN to function as intended, HIB_REG_ON_OUT must be connected to REG_ON. Document Number: 002-14826 Rev. *H Page 12 of 65 PRELIMINARY CYW43903 3. Frequency References An external crystal is used for generating all radio frequencies and normal-operation clocking. As an alternative, an external frequency reference can be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. 3.1 Crystal Interface and Clock Generation The CYW43903 can use an external crystal to provide a frequency reference. The recommended crystal oscillator configuration, including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration. Figure 5. Recommended Oscillator Configuration Device boundary C WRF_XTAL_XON 1.3 pF 27 pF 37.4 MHz C x ohms 27 pF Programmable internal shunt caps are  from 0 pF to 7.5 pF in steps of 0.5 pF. WRF_XTAL_XOP 0.4 pF External resistor and programmable  internal resistor value is determined  by crystal drive level. Programmable internal series resistor is from 50 ohms to 500 ohms  in steps of 50 ohms. Boot‐up ROM value is 50 ohms. Note: A reference schematic is available for further details. Contact your Cypress FAE. A fractional-N synthesizer in the CYW43903 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate using a wide selection of frequency references. The recommended default frequency reference is a 37.4 MHz crystal. The signal characteristics for the crystal interface are listed in Table 4. Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details. Document Number: 002-14826 Rev. *H Page 13 of 65 PRELIMINARY CYW43903 3.2 External Frequency Reference As an alternative to a crystal, an external precision frequency reference can be used, provided that it meets the phase noise requirements listed in Table 4. If used, the external clock should be connected to the WRF_XTAL_XON pin through an external 1000 pF coupling capacitor, as shown in Figure 6. The internal clock buffer connected to this pin will be turned off when the CYW43903 goes into sleep mode. When the clock buffer turns on and off, there will be a small impedance variation. Power must be supplied to the WRF_XTAL_VDD1P35 pin. Figure 6. Recommended Circuit to Use With an External Reference Clock 1000 pF Reference  Clock WRF_XTAL_XON NC WRF_XTAL_XOP Table 4. Crystal Oscillator and External Clock—Requirements and Performance External Frequency Reference2 Crystal1 Parameter Frequency Conditions/Notes 2.4 GHz and 5 GHz bands: IEEE 802.11a/b/g/n operation Frequency tolerance over the Without trimming lifetime of the equipment, including temperature3 Min. Typ. Max. Min. Typ. Max. Units – 37.4 – – –37.4 – MHz –20 – 20 –20 – 20 ppm Crystal load capacitance – – 16 – – – – pF ESR – – – 60 – – – Ω Drive level External crystal must be able to tolerate this drive level. 200 – – – – – µW Input impedance (WRF_XTAL_XON) Resistive – – – 30k 100k – Ω Capacitive – – 7.5 – – 7.5 pF WRF_XTAL_XON Input low level DC-coupled digital signal – – – 0 – 0.2 V WRF_XTAL_XON Input high level DC-coupled digital signal – – – 1.0 – 1.26 V WRF_XTAL_XON input voltage (see Figure 6) IEEE 802.11b/g operation only – – – 400 – 1200 mVp-p WRF_XTAL_XON input voltage (see Figure 6) IEEE 802.11n AC-coupled analog input – – – 1 – – Vp-p Duty cycle 37.4 MHz clock – – – 40 50 60 % 37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz 37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz 4 Phase noise (IEEE 802.11b/g) noise4 Phase (IEEE 802.11n, 2.4 GHz) 1. (Crystal) Use WRF_XTAL_XON and WRF_XTAL_XOP. 2. See External Frequency Reference for alternative connection methods. 3. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications. 4. Assumes that external clock has a flat phase noise response above 100 kHz. Document Number: 002-14826 Rev. *H Page 14 of 65 PRELIMINARY CYW43903 3.3 External 32.768 kHz Low-Power Oscillator The CYW43903 uses a secondary low frequency clock for low-power-mode timing. Either the internal low-precision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications. However, one tradeoff caused by this wide LPO tolerance is a small current consumption increase during power save mode that is incurred by the need to wake-up earlier to avoid missing beacons. Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table 5. Table 5. External 32.768 kHz Sleep Clock Specifications Parameter LPO Clock Units Nominal input frequency 32.768 kHz Frequency accuracy ±200 ppm Duty cycle 30–70 % Input signal amplitude 200–3300 mV, p-p Signal type Square-wave or sine-wave – >100k 1.05 μH, cap. + board total – ESR < 20 mΩ, Cout > 1.9 μF, ESL