CY2CC1910OIT

COMLINK™ SERIES CY2CC1910 1:10 Clock Fanout Buffer with Output Enable Features • Low-voltage operation • Full-range support: — 3.3V — 2.5V — 1.8V • 1:10 fanout • Drives either a 50-Ohm or 75-Ohm load • Over voltage tolerant input hot swappable • Low-input capacitance • Low-output skew • Low-propagation delay • Typical (tpd < 4 ns) • High-speed operation: — 100 MHz@1.8V — 200 MHz@2.5V/3.3V • Industrial versions available • Available packages include: SOIC, SSOP Description The Cypress series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industries fastest logic and buffers. The Cypress CY2CC1910 fanout buffer features one input and ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V. Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. Cypress employs unique AVCMOS-type outputs VOI™ (Variable Output Impedance) that dynamically adjust for variable impedance matching and eliminate the need for series damping resistors; they also reduce noise overall. Block Diagram 5 OE# AVCMOS 23 Pin Configuration Q1 GND Q10 VDD Q9 OE# IN GND GND Q8 VDD Q7 GND 21 Q2 19 VDD 18 Q3 Q4 16 3,10 15,22 6 IN AVCMOS Q5 1,12,13 17,24 14 Q6 11 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CY2CC1910 GND Q1 VDD Q2 GND Q3 Q4 GND Q5 VDD Q6 GND 24 pin SOIC/SSOP Q7 9 GND 4 Q8 Q9 2 Q 10 OUTPUT (AVCMOS) Pin Description Pin Number 1, 7, 8, 12, 13, 17, 20, 24 3,10,15,22 5 6 2, 4, 9, 11, 14, 16, 18, 19, 21, 23 Pin Name Ground Power Supply OE# Output Enable IN Input Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1 Output • 3901 North First Street • San Jose • GND VDD Pin Description Power Power LVTTL/LVCMOS LVTTL/LVCMOS AVCMOS CA 95134 • 408-943-2600 Revised December 26, 2002 Cypress Semiconductor Corporation Document #: 38-07347 Rev. *B COMLINK™ SERIES CY2CC1910 Maximum Ratings[1,2] Storage Temperature: ................................ –65°C to + 150°C Ambient Temperature:................................... –40°C to +85°C Supply Voltage to Ground Potential VCC .................................................................. –0.5V to 4.6V Input ................................................................. –0.5V to 5.8V Supply Voltage to Ground Potential (Outputs only) ........................................... –0.5V to VDD + 1V DC Output Voltage.................................... –0.5V to VDD + 1V Power Dissipation........................................................ 0.75W Variable Output Impedance Control (VOI™) Pull Down 3.5 Pull Up 3.5 3 3 2.5 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0 -0.18 -0.16 -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0 Iol (A) Vdd = 3.3 V Vdd = 2.5 V Vdd = 1.8 V Vdd = 3.3 V Ioh (A) Vdd = 2.5 V Vdd = 1.8 V Figure 1. Output Voltage vs. Output Current (TA = 25°C) DC Electrical Characteristics @ 3.3V (see Figure 2) Parameter VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH Parameter Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power-down Disable Input Hysteresis Conditions VDD = Min.,VIN = VIH or VIL VDD = Min.,VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max.,VIN = VDD(Max.) VDD = Min., IIN = –18 mA VDD = Max.,VOUT = GND VDD = GND,VOUT = < 4.5V Min. IOH = –12 mA 2.3 IOL = 12 mA 2 VIN = 2.7V VIN = 0.5V Typ. 3.3 0.2 Max. 0.5 5.8 0.8 1 –1 20 –1.2 –50 100 –0.7 80 Unit V V V V uA uA uA V mA uA mV DC Electrical Characteristics @ 2.5V (see Figure 2) Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power-down Disable Input Hysteresis VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH Conditions VDD = Min.,VIN = VIH or VIL VDD = Min.,VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max.,VIN = VDD(Max.) VDD = Min., IIN = –18 mA VDD = Max.,VOUT = GND VDD = GND, VOUT = < 4.5V VDD = Min.,VIN = VIH or VIL IOH = –7 mA IOH = 12 mA IOL = 12 mA Min. 1.8 1.6 1.6 Typ. Max. VIN = 2.4V VIN = 0.5V –0.7 0.65 5.0 0.8 1 –1 20 –1.2 –50 100 80 Unit V V V V V uA uA uA V mA uA mV Note: 1. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Document #: 38-07347 Rev. *B Page 2 of 8 COMLINK™ SERIES CY2CC1910 DC Electrical Characteristics @ 1.8V (see Figure 6) Parameter VDD VIH VIL VOH VOL Description Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage IOH = –2 mA IOH = 2 mA Test Condition[3] Min. 1.71 0.65VDD[1.1] –0.3 VDD – 0.45[1.2] 0.45 Max. 1.89 4.3 0.35VDD[0.6] Unit V V V V V Capacitance Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Typ. 2.5 6.5 Max. Unit pF pF Power Supply Characteristics (see Figure 2) Parameter ∆ICC ICCD IC Description Delta ICC Quiescent Power Supply Current Test Conditions (IDD @VDD = Max. and VIN = VDD) – (IDD @VDD = Max. and VIN = VDD – 0.6V) Min. Typ. Max. 50 0.63 25 Unit uA mA/ MHz mA Dynamic Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open Total Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open fL = 40 MHZ High-frequency Parametrics Parameter DJ Description Jitter, deterministic Test Conditions 50% duty cycle tW(50–50) The “point to point load circuit” | Output Jitter – Input Jitter | 50% duty cycle tW(50–50) Standard Load Circuit. 50% duty cycle tW(50–50) The “point to point load circuit” Fmax 2.5V Fmax 1.8V Fmax(20) Maximum frequency VDD = 2.5V Maximum frequency VDD = 1.8V Maximum frequency VDD = 3.3V The “point to point load circuit” VIN = 2.4V/0.0V VOUT = 1.7V/0.7V The “6-pF load circuit” VIN = 1.7V/0.0V VOUT = 1.2V/0.4V 20% duty cycle tW(20–80) The “point to point load circuit” VIN = 3.0V/0.0V VOUT = 2.3V/0.4V The “point to point load circuit” VIN = 3.0V/0.0V F = 100 MHz VOUT = 2.0V/0.8V The “point to point load circuit” VIN = 2.4V/0.0V F = 100 MHz VOUT = 1.7V/0.7V The “6-pF load circuit” VIN = 1.7V/0.0V VOUT = 1.2V/0.4V See Figure 4 20 See Figure 2 See Figure 4 See Figure 4 200 See Figure 6 100 See Figure 4 250 See Figure 4 1 See Figure 4 1 See Figure 6 1 ns MHz MHz 160 200 MHz MHz Min. Typ. Max. Unit ps Fmax 3.3V Maximum frequency VDD = 3.3V tW 3.3V tW 2.5V tW 1.8V Minimum pulse VDD = 3.3V Minimum pulse VDD = 2.5V Minimum pulse VDD = 1.8V Note: 3. Test Load conditions: 500 ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency. Document #: 38-07347 Rev. *B Page 3 of 8 COMLINK™ SERIES CY2CC1910 AC Switching Characteristics @ 3.3V VDD = 3.3V ± 5%, Temperature = –40°C to +85°C Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Propagation Delay – Low to High Propagation Delay – High to Low Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase) Figure 10 Pulse Skew: Skew between opposite transitions of the same output (tPHL Figure 9 – tPLH). Package Skew: Skew between outputs of different packages at the same Figure 11 power supply Voltage, temperature and package type. Description Figure 3 Min. 1.5 1.5 Typ. 2.7 2.7 0.8 0.8 0.2 0.2 0.4 Max. Unit 3.5 3.5 nS nS V/nS V/nS nS nS nS AC Switching Characteristics @ 2.5V VDD = 2.5V ± 5%, Temperature = –40°C to +85°C Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Propagation Delay – Low to High Propagation Delay – High to Low Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase) Figure 10 Pulse Skew: Skew between opposite transitions of the same output (tPHL Figure 9 – tPLH). Package Skew: Skew between outputs of different packages at the same power supply Voltage, temperature and package type. Figure 11 Description Figure 3 Min. 1.5 1.5 Typ. 2.7 2.7 0.8 0.8 0.2 0.2 0.4 Max. 3.5 3.5 Unit nS nS V/nS V/nS nS nS nS AC Switching Characteristics @ 1.8V VDD = 1.8V ± 5%, Temperature = –40°C to +85°C Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Propagation Delay – Low to High Propagation Delay – High to Low Output Rise Time 20–80% Output Fall Time 20–80% Output Skew: Skew between outputs of the same package (in phase) Figure 10 Pulse Skew: Skew between opposite transitions of the same output (tPHL Figure 9 – tPLH). Package Skew: Skew between outputs of different packages at the same Figure 11 power supply Voltage, temperature and package type. Description Figure 7 Min. 1.5 1.5 0.2 0.2 Typ. 2.7 2.7 Max. 3.5 3.5 1.5 1.5 0.2 0.2 0.4 Unit nS nS nS nS nS nS nS Parameter Measurement Information: VDD @ 3.3V–2.5V From Output Under Test CL = 50 pF 500 ohm 0.8VDD VDD/2 VDD/2 Input tPLH Output VDD/2 0V tPHL VDD/2 VOH VOL Figure 2. Load Circuit [4,5,6] Figure 3. Voltage Waveforms Propagation Delay Times[7] Notes: 4. CL includes probe and jig capacitance. 5. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50Ω, tR < 2.5 nS, tF < 2.5 nS. 6. The outputs are measured one at a time with one transition per measurement. 7. TPLH and TPHL are the same as tpd. Document #: 38-07347 Rev. *B Page 4 of 8 COMLINK™ SERIES CY2CC1910 From Output Under Test CL = 3 pF 500 ohm Parameter Measurement Information: VDD @ 1.8V From Output Under Test CL = 6 pF 500 ohm Figure 4. Point to Point Load Circuit tw(50-50) Input VDD/2 VDD/2 [4,5,6] 0.8VDD Figure 6. Load Circuit [4,5,6] 1.8V 0.9V 0V tw(20-80) Input VDD/2 0V 0.8VDD Input tPLH 0.9V 0.9V 0V tPHL 0.9V VOH VOL Figure 5. Voltage Waveforms–Pulse Duration[5] Output Figure 7. Voltage Waveforms Propagation Delay Times[7] tw(50-50) Input 0.9V 0.9V 0V tw(20-80) Input 0.9V 0V 1.8V 1.8V Figure 8. Voltage Waveforms–Pulse Duration[5] 3V 1.5V INPUT tPLH tPHL 0V VOH 1.5V OUTPUT tsk (P) = VOL l tPHL - tPLH l Figure 9. Pulse Skew - tsk(p) Document #: 38-07347 Rev. *B Page 5 of 8 COMLINK™ SERIES CY2CC1910 3V 1.5V INPUT tPLH1 tPHL1 0V VOH 1.5V OUTPUT 1 tsk (O) tsk (O) VOL VOH 1.5V OUTPUT 2 VOL tPLH 2 tPLH 2 tsk (P) = l tPLH2 - t PLH1 l o r tPHL2 - t PHL1 l 3V 1.5V Figure 10. Output Skew–tsk(0) INPUT tPLH1 tPHL1 0V VOH 1.5V PACKAGE 1 OUTPUT tsk(t) tsk(t) VOL VOH 1.5V PACKAGE 2 OUTPUT VOL tPLH 2 tPLH 2 tsk(t) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Figure 11. Package Skew–tsk(t) Ordering Information Part Number CY2CC1910SI CY2CC1910SIT CY2CC1910OI CY2CC1910OIT CY2CC1910SC CY2CC1910SCT CY2CC1910OC CY2CC1910OCT 24-pin SOIC 24-pin SOIC–Tape and Reel 24-pin SSOP 24-pin SSOP–Tape and Reel 24-pin SOIC 24-pin SOIC–Tape and Reel 24-pin SSOP 24-pin SSOP–Tape and Reel Package Type Product Flow Industrial, –40° to 85°C Industrial, –40° to 85°C Industrial, –40° to 85°C Industrial, –40° to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Document #: 38-07347 Rev. *B Page 6 of 8 COMLINK™ SERIES CY2CC1910 Package Drawing and Dimensions 24-pin (300-mil) Molded SOIC S13 51-85025-A 24-pin (5.3 mm) Shrunk Small Outline Package O24 51-85078-** VOI is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07347 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. COMLINK™ SERIES CY2CC1910 Document History Page Document Title: CY2CC1910 COMLINKTM SERIES 1:10 Clock Fanout Buffer with Output Enable Document #: 38-07347 REV. ** *A ECN NO. 114317 119149 Issue Date 05/13/02 10/11/02 Orig. of Change TSM RGL New Data Sheet Added 5.8 as the Max. value for VIH in the DC Electrical Characteristics @3.3V table. Changed the Max. value of the VIH from 5.8 to 5.0 in the DC Electrical Characteristics @2.5V table. Changed the value of VIH from VDD+0.3 [2.25] to 4.3 in the DC Electrical Characteristics @1.8V table. Add power up requirements to maximum ratings informations. Description of Change *B 122899 12/26/02 RBI Document #: 38-07347 Rev. *B Page 8 of 8